CN114497242A - Preparation method and application of boron-doped selective emitter - Google Patents
Preparation method and application of boron-doped selective emitter Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 102
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 102
- 239000010703 silicon Substances 0.000 claims abstract description 102
- 238000000151 deposition Methods 0.000 claims abstract description 37
- 238000007639 printing Methods 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 30
- 230000003647 oxidation Effects 0.000 claims description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 28
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 27
- 229910052796 boron Inorganic materials 0.000 claims description 27
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 239000002002 slurry Substances 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 238000007650 screen-printing Methods 0.000 claims description 10
- 229910052582 BN Inorganic materials 0.000 claims description 9
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 239000000919 ceramic Substances 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000010023 transfer printing Methods 0.000 claims description 2
- 229920002050 silicone resin Polymers 0.000 claims 1
- 239000005388 borosilicate glass Substances 0.000 description 60
- 235000012431 wafers Nutrition 0.000 description 52
- 229910004205 SiNX Inorganic materials 0.000 description 8
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 239000007789 gas Substances 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
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Abstract
The invention discloses a preparation method and application of a boron-doped selective emitter, wherein the preparation method of the boron-doped selective emitter comprises the steps of depositing a BSG layer on the surface of a textured silicon wafer, then locally covering a mask layer on the surface of the BSG layer to enable the covering area of the mask layer to be consistent with the metal electrode printing area on the surface of the silicon wafer, then carrying out high-temperature propulsion on the silicon wafer, and finally removing the BSG layer and the mask layer on the silicon wafer. According to the preparation method of the boron-doped selective emitter, after the BSG layer is deposited, only the mask layer needs to be covered locally, and the SE structure can be prepared by high-temperature propulsion under the condition that the BSG layer is not removed.
Description
Technical Field
The invention relates to the field of photovoltaics, in particular to a preparation method and application of a boron-doped selective emitter.
Background
Due to the advantages of long minority carrier lifetime, low temperature coefficient, no photo-thermal induced attenuation caused by B-O recombination and the like, the N-type crystalline silicon cell becomes the key development direction of a new generation of efficient solar cell and is more and more concerned by the industry. The existing mature N-type crystalline silicon battery mainly comprises N-PERT, N-PERL, N-TOPCon, N-IBC and other structural batteries.
The Selective Emitter Structure (SE) realizes the optimization of the Emitter region by carrying out heavy doping in the electrode contact region and light doping between the electrodes, so that the contact resistance between a metal electrode and a silicon wafer can be reduced, the carrier recombination in a diffusion layer region can be reduced, the output voltage and the current of a battery are enhanced, and the efficiency of the battery can be obviously improved.
The SE structure of phosphorus is currently used in industrial production, but the SE structure of boron has not been effectively used. At present, some preparation methods aiming at boron SE structures exist in the industry, and the preparation methods are mainly divided into the following two main types: (1) the boron SE structure is prepared by combining a mask method with a secondary boron diffusion method, a mask layer is grown on a silicon substrate in advance, then a local area is etched to form a window, then primary boron diffusion is carried out to form heavy doping, and secondary boron diffusion is carried out to form light doping after the mask is removed; (2) the laser SE method mainly realizes heavy doping through laser propulsion of a local area after a boron source is deposited or coated, realizes light doping in other laser-free areas, and further realizes an SE structure.
Disclosure of Invention
In order to solve the defects of the prior art, one object of the present invention is to provide a method for preparing a boron-doped selective emitter, which comprises the steps of depositing a BSG layer on the surface of a textured silicon wafer, then partially covering a mask layer on the surface of the BSG layer to make the covering area of the mask layer consistent with the metal electrode printing area on the surface of the silicon wafer, then carrying out high-temperature oxidation promotion on the silicon wafer, and finally removing the BSG layer and the mask layer on the silicon wafer.
Preferably, the step of depositing the BSG layer on the surface of the textured silicon wafer comprises the following steps: and (3) placing the textured silicon wafer in a tubular or chain type boron diffusion furnace for BSG deposition and slight propulsion, so that a layer of BSG layer and a shallow boron junction are obtained on the surface of the silicon wafer.
Preferably, the step of depositing the BSG layer on the surface of the textured silicon wafer comprises the following steps: and placing the textured silicon wafer in equipment capable of realizing BSG deposition, such as CVD, PECVD and the like, for BSG deposition, so that a BSG layer is obtained on the surface of the silicon wafer.
Preferably, the mask layer is a high-temperature-resistant oxidation-resistant film, and can keep good oxygen blocking capacity at the temperature of 800-.
More preferably, the high-temperature-resistant oxidation-resistant film is selected from any one of a silicon nitride layer, a silicon oxynitride layer, a boron nitride layer, a silicon oxide layer, an organic silicon resin layer, and a high-temperature-resistant ceramic layer.
Preferably, the step of locally covering the surface of the BSG layer with a mask layer includes the following steps: and screen printing slurry or laser transfer printing slurry on a local area on the surface of the BSG layer, and forming a mask layer in the local area, wherein the local area is consistent with a metal electrode printing area on the surface of the silicon wafer.
Preferably, the step of locally covering the surface of the BSG layer with a mask layer includes the following steps: and (3) depositing a mask layer on a local area on the surface of the BSG layer by CVD or PECVD and other equipment, covering the surface of the BSG layer by using a template in the deposition process, and directly forming the mask layer on the local area, wherein the local area is consistent with a metal electrode printing area on the surface of the silicon wafer.
Preferably, the step of locally covering the surface of the BSG layer with a mask layer includes the following steps: and depositing a mask layer in the whole area of the surface of the BSG layer by CVD or PECVD equipment capable of depositing the mask layer, and printing the etching slurry by screen printing to etch the mask layer in partial area, wherein the area which is not etched is consistent with the metal electrode printing area on the surface of the silicon chip.
Preferably, a chain type diffusion furnace is adopted to carry out high-temperature oxidation propulsion on the silicon wafer, the chain type diffusion furnace is provided with a constant temperature area, the temperature of the constant temperature area is controlled to be 800-1200 ℃, and the high-temperature oxidation propulsion of the silicon wafer in the constant temperature area is 200-1000 s.
Preferably, a tubular diffusion furnace is adopted to carry out high-temperature oxidation propulsion on the silicon wafer, and nitrogen and oxygen are introduced into the tubular diffusion furnace during the high-temperature oxidation propulsion.
Further preferably, the temperature of the tubular diffusion furnace is controlled at 800-.
Preferably, a RTP furnace is adopted to carry out high-temperature oxidation propulsion on the silicon wafer, and nitrogen and oxygen are introduced into the RTP furnace during the high-temperature oxidation propulsion.
Further preferably, the temperature of the RTP furnace is controlled at 800-.
Preferably, the BSG layer and the mask layer on the silicon wafer are removed by using a cleaning solution containing HF.
The invention also aims to provide a preparation method of the N-type battery, which comprises the preparation method of the boron-doped selective emitter.
The invention has the advantages and beneficial effects that: the preparation method of the boron-doped selective emitter is provided, after the BSG layer is deposited, only a mask layer needs to be covered locally, and the SE structure can be prepared by high-temperature propulsion under the condition that the BSG layer is not removed.
According to the invention, the mask layer is selectively covered on the local area (namely the metal electrode printing area, hereinafter referred to as the electrode area) on the surface of the BSG layer, so that the boron diffusion of the electrode area to the environment atmosphere during the subsequent high-temperature propulsion is inhibited. Specifically, the method comprises the following steps: in the process of high-temperature propulsion, the electrode area is covered with a mask layer which is a high-temperature-resistant oxidation-resistant film and is selected from a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy) layer, a boron nitride layer, a silicon oxide layer, an organic silicon resin layer or a high-temperature-resistant ceramic layer, and boron in the silicon surface and the BSG layer of the electrode area can be inhibited from diffusing and escaping into the ambient atmosphere (air), so that more boron sources in the electrode area can diffuse into the silicon substrate, and the boron concentration obtained in the electrode area is higher and the junction depth is deeper; because the non-electrode area is not covered with the mask layer, a large amount of boron in the silicon surface and the BSG layer of the non-electrode area can diffuse and escape into the environment atmosphere in the high-temperature oxidation propulsion process, and the boron obtained by the non-electrode area has low concentration and shallow junction depth; the difference between the electrode area and the non-electrode area can be used to prepare the selective emitter.
If a tubular diffusion furnace or an RTP furnace is adopted for high-temperature oxidation propulsion, nitrogen and oxygen in a certain proportion can be introduced into the tubular diffusion furnace or the RTP furnace, and boron in the BSG layer of the non-electrode area can be promoted to diffuse into the ambient atmosphere in the oxygen environment.
The invention has the following characteristics:
1. the invention has less process steps and low cost, and the SE structure can be prepared by only covering a mask layer (a silicon nitride layer, a silicon oxynitride layer, a boron nitride layer, a silicon oxide layer or an organic silicon resin layer) on the electrode area after the BSG layer is deposited and advancing at high temperature under the condition of not removing the BSG layer.
2. The invention has high feasibility and can directly utilize the existing industrial equipment.
3. The invention can use chain type propulsion and can increase the productivity compared with a tubular type.
4. The invention has wide application prospect.
Detailed Description
The following further describes embodiments of the present invention with reference to examples. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
Example 1
The embodiment provides a preparation method of a boron-doped selective emitter, which includes depositing a BSG (borosilicate glass) layer on the surface of a textured silicon wafer, covering a mask layer (a silicon nitride layer, a silicon oxynitride layer, a boron nitride layer, a silicon oxide layer, an organic silicon resin layer or a high-temperature-resistant ceramic layer) on a local area (namely a metal electrode printing area, hereinafter referred to as an electrode area) on the surface of the BSG layer, enabling the covering area of the mask layer to be consistent with the metal electrode printing area on the surface of the silicon wafer, then carrying out high-temperature propulsion on the silicon wafer, and then removing the BSG layer and the mask layer on the silicon wafer.
The method comprises the following specific steps:
1) texturing: selecting an N-type silicon wafer to carry out conventional cleaning and texturing;
2) depositing a BSG layer on the surface of the textured silicon wafer: placing the textured silicon wafer in a tubular boron diffusion furnace for tubular deposition and slight propulsion to obtain a BSG layer and a shallow boron junction on the surface of the silicon wafer; after completion of the tube deposition and slight drive-in, the peak concentration of boron doping was 2E20cm-3The depth of the boron junction is 100nm, and the thickness of the BSG layer is20nm, and the sheet resistance is about 200 ohms;
3) the surface of the BSG layer is partially covered with a mask layer, and the mask layer can be any one of a silicon nitride layer, a silicon oxynitride layer, a boron nitride layer, a silicon oxide layer or an organic silicon resin layer and a high-temperature-resistant ceramic layer: the method comprises the steps of screen printing slurry containing a mask layer component, specifically slurry containing a SiNx component, a SiOxNy component, a boron nitride component, a silicon oxide component, an organic silicon resin component or a high-temperature-resistant ceramic layer component, on a local area on the surface of a BSG layer, forming a mask layer on the local area, wherein the local area is consistent with a metal electrode printing area on the surface of a silicon wafer; the width of the pattern for screen printing is about 100 um;
4) carrying out high-temperature oxidation propulsion on the silicon wafer: the silicon chip is pushed at high temperature by adopting a chain type diffusion furnace, the chain type diffusion furnace is provided with five temperature zones, the speed of a conveyor belt is 100cm/min, the silicon chip sequentially passes through a furnace inlet zone, a temperature rising zone, a constant temperature zone, a cooling zone and a furnace outlet zone, the temperature of the constant temperature zone is controlled to be 800 plus one year, the silicon chip is pushed at high temperature in the constant temperature zone for 200 plus one year for 1000s, the square resistance of the electrode zone is 80-100 ohms after the high-temperature oxidation pushing is finished, and the square resistance of the non-electrode zone is 200 plus one year for 250 ohms;
5) and cleaning and removing the BSG layer and the mask layer on the silicon wafer by adopting a cleaning solution containing HF.
Example 2
The present embodiment provides a method for preparing a boron-doped selective emitter, which is similar to embodiment 1, except that the following steps are performed:
2) depositing a BSG layer on the surface of the textured silicon wafer: placing the textured silicon wafer in equipment capable of realizing BSG deposition, such as CVD, PECVD and the like, for BSG deposition, so that a BSG layer is obtained on the surface of the silicon wafer;
3) a mask layer is partially covered on the surface of the BSG layer, and the mask layer can be any one of a SiNx layer, a SiOxNy layer and a silicon oxide layer: the method comprises the following steps of depositing a mask layer on a local area on the surface of the BSG layer through CVD or PECVD equipment and the like, covering the surface of the BSG layer by using a template in the deposition process, and directly forming the mask layer on the local area, wherein the local area is consistent with a metal electrode printing area on the surface of a silicon wafer;
4) carrying out high-temperature oxidation propulsion on the silicon wafer: high-temperature oxidation is carried out on silicon wafers by adopting RTP furnaceWhen the high-temperature oxidation propulsion is carried out, nitrogen and oxygen are introduced into the RTP furnace, and the gas flow is O2:N2The RTP temperature is controlled at 800-.
Example 3
The present embodiment provides a method for preparing a boron-doped selective emitter, which is similar to embodiment 1, except that the following steps are performed:
3) a mask layer is partially covered on the surface of the BSG layer, and the mask layer can be any one of a SiNx layer, a SiOxNy layer and a silicon oxide layer: depositing a mask layer in the whole area of the surface of the BSG layer by a device which can deposit the mask layer, such as CVD or PECVD and the like, and then screen-printing an etching slurry to etch the mask layer in a partial area, wherein the area which is not etched is consistent with the metal electrode printing area on the surface of the silicon chip; the etching slurry used in this example is an etching slurry containing HF;
4) carrying out high-temperature oxidation propulsion on the silicon wafer: the silicon chip is propelled at high temperature by adopting a tubular diffusion furnace, nitrogen and oxygen are introduced into the tubular diffusion furnace, and the gas flow is O2:N2The temperature of the tubular diffusion furnace is controlled to be 800-.
Example 4
The embodiment provides a method for manufacturing an N-type cell, where the N-type cell is a TOPCon solar cell, and the method specifically includes the following steps:
1) texturing: selecting an N-type silicon wafer to carry out conventional cleaning and texturing;
2) depositing a BSG layer on the surface of the textured silicon wafer:
placing the textured silicon wafer in a tubular boron diffusion furnace for tubular deposition and slight propulsion to obtain a BSG layer and a shallow boron junction on the surface of the silicon wafer; after completion of the tube deposition and slight drive-in, the peak concentration of boron doping was 2E20cm-3The depth of the boron junction is 100nm, the thickness of the BSG layer is 20nm, and the sheet resistance is about 200 ohms;
alternatively, the first and second electrodes may be,
placing the textured silicon wafer in equipment capable of realizing BSG deposition, such as CVD, PECVD and the like, for BSG deposition, so that a BSG layer is obtained on the surface of the silicon wafer;
3) covering a mask layer on the surface of the BSG layer locally, wherein the mask layer is a SiNx layer, a SiOxNy layer, a boron nitride layer, a silicon oxide layer, an organic silicon resin layer or a high-temperature-resistant ceramic layer:
the method comprises the steps of screen printing slurry containing a mask layer component, specifically slurry containing a SiNx component, a SiOxNy component, a boron nitride component, a silicon oxide component, an organic silicon resin component or a high-temperature-resistant ceramic component, on a local area of the surface of a BSG layer, forming the mask layer on the local area, wherein the local area is consistent with a metal electrode printing area on the surface of a silicon wafer; the width of the pattern for screen printing is about 100 um;
alternatively, the first and second electrodes may be,
the method comprises the steps that a mask layer can be deposited on a local area of the surface of a BSG layer through CVD or PECVD and the like, the mask layer is directly formed in the local area by covering the surface of the BSG layer with a template in the deposition process, the mask layer is a SiNx layer, a SiOxNy layer or a silicon oxide layer, and the local area is consistent with a metal electrode printing area on the surface of a silicon wafer;
alternatively, the first and second electrodes may be,
depositing a mask layer in the whole area of the BSG layer surface by CVD or PECVD equipment capable of depositing the mask layer, wherein the mask layer is a SiNx layer, a SiOxNy layer or a silicon oxide layer, and the thickness of the mask layer is 30-200 nm; etching the mask layer of the local area by screen printing of etching slurry, keeping the area which is not etched consistent with the metal electrode printing area on the surface of the silicon wafer, wherein the pattern width of the area which is not etched is 50-100 um; the etching slurry used in this example is an etching slurry containing HF;
4) carrying out high-temperature propulsion on the silicon wafer:
the silicon chip is pushed at high temperature by adopting a chain type diffusion furnace, the chain type diffusion furnace is provided with five temperature zones, the speed of a conveyor belt is 100cm/min, the silicon chip sequentially passes through a furnace inlet zone, a temperature rising zone, a constant temperature zone, a cooling zone and a furnace outlet zone, the temperature of the constant temperature zone is controlled to be 800 plus one year, the silicon chip is pushed at high temperature in the constant temperature zone for 200 plus one year for 1000 seconds, the square resistance of the electrode zone is 80-100 ohms after the high temperature pushing is finished, and the square resistance of the non-electrode zone is 200 plus one year for 250 ohms;
alternatively, the first and second electrodes may be,
the silicon chip is propelled at high temperature by adopting a tubular diffusion furnace, nitrogen and oxygen are introduced into the tubular diffusion furnace, and the gas flow is O2:N2The temperature of the tubular diffusion furnace is controlled to be 800-;
alternatively, the first and second electrodes may be,
the silicon chip is propelled at high temperature by an RTP furnace, nitrogen and oxygen are introduced into the RTP furnace, and the gas flow is O2:N2The RTP temperature is controlled to be 800-;
5) back BSG removal and back base polishing:
placing the silicon wafer in HF solution with the concentration of 0.5-10% to remove BSG on the back of the silicon wafer in a mode of water floating or front water film covering; then the silicon wafer is put into a sodium hydroxide solution or a potassium hydroxide solution containing polishing additive components to realize the back polishing of the silicon wafer;
6) removing the front mask layer and the BSG:
simultaneously cleaning the front mask layer and the BSG by adopting an HF solution with the concentration of 0.5-20%;
7) forming a back tunneling passivation structure:
depositing a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the back of the silicon wafer, and annealing the silicon wafer;
8) removing the coil plating: removing the film layer wound to the front side in the deposition and annealing processes of the phosphorus-doped polysilicon on the back side so as to avoid influencing the electrical property and appearance of the front side and simultaneously etching edge damage generated by laser slicing;
8) depositing a front and back passivation layer and an antireflection layer;
9) and printing and sintering.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the technical principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (15)
1. A preparation method of a boron-doped selective emitter is characterized in that a BSG layer is deposited on the surface of a textured silicon wafer, a mask layer is partially covered on the surface of the BSG layer, the covering area of the mask layer is enabled to be consistent with the metal electrode printing area on the surface of the silicon wafer, then high-temperature oxidation propulsion is carried out on the silicon wafer, and finally the BSG layer and the mask layer on the silicon wafer are removed.
2. The method for preparing the boron-doped selective emitter according to claim 1, wherein the step of depositing the BSG layer on the surface of the textured silicon wafer comprises the following steps: and (3) placing the textured silicon wafer in a tubular or chain type boron diffusion furnace for BSG deposition and slight propulsion, so that a layer of BSG layer and a shallow boron junction are obtained on the surface of the silicon wafer.
3. The method for preparing the boron-doped selective emitter according to claim 1, wherein the step of depositing the BSG layer on the surface of the textured silicon wafer comprises the following steps: and placing the textured silicon wafer in equipment capable of realizing BSG deposition, such as CVD, PECVD and the like, for BSG deposition, so that a BSG layer is obtained on the surface of the silicon wafer.
4. The method as claimed in claim 1, wherein the mask layer is a high temperature resistant oxidation resistant film capable of maintaining good oxygen blocking capability at 800-.
5. The method of claim 4, wherein the high temperature resistant oxidation resistant film is selected from any one of a silicon nitride layer, a silicon oxynitride layer, a boron nitride layer, a silicon oxide layer, a silicone resin layer, and a high temperature resistant ceramic layer.
6. The method for preparing the boron-doped selective emitter according to claim 1, wherein the step of partially covering a mask layer on the surface of the BSG layer comprises the following steps: and screen printing slurry or laser transfer printing slurry on a local area on the surface of the BSG layer, and forming a mask layer in the local area, wherein the local area is consistent with a metal electrode printing area on the surface of the silicon wafer.
7. The method for preparing the boron-doped selective emitter according to claim 1, wherein the step of partially covering a mask layer on the surface of the BSG layer comprises the following steps: and (3) depositing a mask layer on a local area on the surface of the BSG layer by CVD or PECVD and other equipment, covering the surface of the BSG layer by using a template in the deposition process, and directly forming the mask layer on the local area, wherein the local area is consistent with a metal electrode printing area on the surface of the silicon wafer.
8. The method for preparing the boron-doped selective emitter according to claim 1, wherein the step of partially covering a mask layer on the surface of the BSG layer comprises the following steps: and depositing a mask layer in the whole area of the surface of the BSG layer by CVD or PECVD equipment capable of depositing the mask layer, and printing the etching slurry by screen printing to etch the mask layer in partial area, wherein the area which is not etched is consistent with the metal electrode printing area on the surface of the silicon chip.
9. The method as claimed in claim 1, wherein the silicon wafer is advanced by high temperature oxidation in a chain type diffusion furnace, the chain type diffusion furnace is provided with a constant temperature region, the temperature of the constant temperature region is controlled to be 1200 ℃ at 800-.
10. The method for preparing the boron-doped selective emitter according to claim 1, wherein a tubular diffusion furnace is used for carrying out high-temperature oxidation propulsion on the silicon wafer, and nitrogen and oxygen are introduced into the tubular diffusion furnace during the high-temperature oxidation propulsion.
11. The method as claimed in claim 10, wherein the temperature of the tubular diffusion furnace is controlled at 1200 ℃ and the time of the high temperature oxidation is controlled at 3000s and 200 s.
12. The method for preparing the boron-doped selective emitter according to claim 1, wherein a RTP furnace is used for carrying out high-temperature oxidation propulsion on the silicon wafer, and nitrogen and oxygen are introduced into the RTP furnace during the high-temperature oxidation propulsion.
13. The method as claimed in claim 12, wherein the temperature of the RTP furnace is controlled at 800-1200 ℃ and the time for the high temperature oxidation is 200-1000 s.
14. The method of claim 1, wherein the BSG layer and the mask layer are removed from the silicon wafer using a cleaning solution containing HF.
15. A method of manufacturing an N-type cell, comprising the method of manufacturing a boron doped selective emitter according to any one of claims 1 to 14.
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CN114479658B (en) * | 2022-01-01 | 2023-02-03 | 常州时创能源股份有限公司 | Mask adhesive for SE doping and preparation method and application thereof |
CN114464700A (en) * | 2022-01-17 | 2022-05-10 | 常州时创能源股份有限公司 | Selective boron doping method of N-type crystalline silicon battery and application thereof |
CN115020536A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of IBC battery graphical P region |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010186900A (en) * | 2009-02-13 | 2010-08-26 | Shin-Etsu Chemical Co Ltd | Solar cell and method of manufacturing the same |
CN103151428A (en) * | 2013-03-26 | 2013-06-12 | 浙江晶科能源有限公司 | Method for realizing selective emitter of crystalline silicon solar cell |
CN109671807A (en) * | 2018-12-26 | 2019-04-23 | 浙江晶科能源有限公司 | A kind of preparation method of solar battery |
CN111739982A (en) * | 2020-06-30 | 2020-10-02 | 浙江晶科能源有限公司 | Preparation method of selective emitter and solar cell |
CN112490304A (en) * | 2020-12-04 | 2021-03-12 | 东方日升(常州)新能源有限公司 | Preparation method of high-efficiency solar cell |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2959351B1 (en) * | 2010-04-26 | 2013-11-08 | Photowatt Int | PROCESS FOR PREPARING AN N + PP + TYPE OR P + NN + TYPE STRUCTURE ON SILICON PLATES |
CN102437238A (en) * | 2011-11-30 | 2012-05-02 | 晶澳(扬州)太阳能科技有限公司 | Method for boron doping of crystalline silicon solar battery |
CN105576083A (en) * | 2016-03-11 | 2016-05-11 | 泰州中来光电科技有限公司 | N-type double-side solar cell based on APCVD technology and preparation method thereof |
CN111628047B (en) * | 2020-06-01 | 2023-02-28 | 常州顺风太阳能科技有限公司 | Manufacturing method of N-type TOPCon solar cell |
CN113363334A (en) * | 2021-06-01 | 2021-09-07 | 常州时创能源股份有限公司 | Preparation method of boron-doped selective emitter |
-
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2022
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010186900A (en) * | 2009-02-13 | 2010-08-26 | Shin-Etsu Chemical Co Ltd | Solar cell and method of manufacturing the same |
CN103151428A (en) * | 2013-03-26 | 2013-06-12 | 浙江晶科能源有限公司 | Method for realizing selective emitter of crystalline silicon solar cell |
CN109671807A (en) * | 2018-12-26 | 2019-04-23 | 浙江晶科能源有限公司 | A kind of preparation method of solar battery |
CN111739982A (en) * | 2020-06-30 | 2020-10-02 | 浙江晶科能源有限公司 | Preparation method of selective emitter and solar cell |
CN112490304A (en) * | 2020-12-04 | 2021-03-12 | 东方日升(常州)新能源有限公司 | Preparation method of high-efficiency solar cell |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023124254A1 (en) * | 2021-06-01 | 2023-07-06 | 常州时创能源股份有限公司 | Preparation method for and use of boron-doped selective emitter |
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