CN110838536A - Back contact solar cell with various tunnel junction structures and preparation method thereof - Google Patents

Back contact solar cell with various tunnel junction structures and preparation method thereof Download PDF

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CN110838536A
CN110838536A CN201911186619.5A CN201911186619A CN110838536A CN 110838536 A CN110838536 A CN 110838536A CN 201911186619 A CN201911186619 A CN 201911186619A CN 110838536 A CN110838536 A CN 110838536A
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layer
sio
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包杰
陈程
陈嘉
赵影文
林建伟
刘志锋
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Taizhou Zhonglai Optoelectronics Technology Co Ltd
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Abstract

The invention relates to a back contact solar cell with various tunnel junction structures and a preparation method thereof. The solar cell comprises an N-type crystalline silicon substrate, wherein the front surface of the N-type crystalline silicon substrate comprises a lightly doped N + surface field and a passivated antireflection film, and the back surface of the N-type crystalline silicon substrate comprises a P-type emitter region, an N-type back surface field region and a groove structure; the P-type emitter region is positioned in the groove structure, and the N-type back surface field region is positioned on the groove structure; the N-type back surface field region sequentially comprises tunneling SiO from inside to outsideXLayer, n + poly layer, oxide layer, n + poly layer, tunneling SiOXA layer, and a p + poly layer; SiO 2XThe layer and the n + poly layer form a c-Si/SiOXA/n + poly tunnel junction, wherein the Oxide layer and the n + poly layer form a n + poly/Oxide/n + poly tunnel junction for tunneling through the SiOXThe layer and the p + poly layer form n + poly/SiOXA/p + poly tunnel junction; the P-type emitter region sequentially comprises a tunneling SiOx layer, a P + poly layer and SiO from inside to outsideXThe layer and the p + poly layer form c-Si/SiOXA/p + poly tunnel junction; the P-type emitter region is provided with a P-type metal electrode, and the N-type back surface field region is provided with an N-type metal electrode.

Description

Back contact solar cell with various tunnel junction structures and preparation method thereof
Technical Field
The invention relates to the technical field of solar cells, in particular to a back contact solar cell with various tunnel junction structures and a preparation method thereof.
Background
In the crystalline silicon solar cell, the efficiency loss of the cell can be divided into two aspects of electrical loss and optical loss, the important component of the electrical loss is recombination loss and resistance loss caused by metal-semiconductor contact, and the important component of the optical loss is shading of metal grating lines on a light receiving surface.
In the current commercialized crystalline silicon solar cells, such as p-type all-aluminum back surface field cells, p-type PERC cells or n-type PERT cells, the metal shielding area of the light receiving surface is about 5 percent; the dark saturation current density (J0, metal) of the n + emission and metal contact area of the front surface of the p-PERC battery is 800-1000 fA/cm under the condition of ensuring that the contact resistivity is low2(ii) a For an n-type battery, the recombination loss is higher, and the dark saturation current density (J0, metal) of a p + emitter and a metal contact area is 1000-2000 fA/cm2. In order to further improve the efficiency of the crystalline silicon solar cell, it is important to reduce the loss in the following three aspects: 1) optical loss due to metal shadowing of the light-receiving surface, 2) recombination loss of metal-semiconductor contact, 3) resistance loss of metal-semiconductor contact.
Researches find that the tunneling oxide layer passivated metal contact structure has remarkable electrical properties, can simultaneously obtain low contact resistivity and low surface recombination, and consists of an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer. Since the absorption of light by the doped polysilicon layer is a 'parasitic' absorption, i.e. does not contribute to the photocurrent, the tunnel oxide layer passivated metal contact structure is most often used on the back side of the cell. In 2017, Feldmann et al, Fraunhofer solar systems research institute, Germany, promoted the conversion efficiency of solar cells with tunnel oxide passivation metal contact structures to 25.8%, and the grid lines on the front surface of the cell caused an efficiency loss of-0.2%. In 2018, the german ISFH solar research institute introduces a tunnel oxide layer passivated metal contact structure into a back contact (IBC) cell, and the front surface of the cell is not shielded by a metal electrode, so that the conversion efficiency is 26.1%.
Conventional crystalline silicon back contact (IBC) cells: 1) a multi-step mask process is required; 2) the spacing between the back emitter region and the back field region needs to be precisely controlled to prevent leakage; 3) a precise alignment metallization technology is needed to isolate the P-region electrode from the N-region electrode; the above reasons lead to many challenges in the large-scale industrialization of IBC cells, such as: more working procedures, complex process, lower productivity, higher cost and the like. The difficulty of the process is undoubtedly further aggravated by introducing a tunnel oxide layer passivation metal contact structure into the IBC cell and preparing the IBC cell (POLO-IBC) in which the emitter and the Back Surface Field (BSF) are both passivation contact structures. The POLO-IBC cell with 26.1% efficiency of the German ISFH solar institute adopts a photoresist mask technology to complete the doping of a back emitter and a BSF region, and an intrinsic region between the emitter and the BSF is realized by adopting the photoresist mask, so that the electric leakage of the cell is prevented. The metallization mode of the battery is Physical Vapor Deposition (PVD), firstly, a laser film opening mode is used for locally removing an emitter and a passivation film above BSF, metal aluminum with the thickness of 10 mu m is thermally evaporated to be used as an electrode, and then a layer of SiO is depositedXAnd as a mask, opening the film by laser again to remove the metal aluminum electrode in the specific area, and isolating the P area from the metal electrode above the N area to finally finish the metallization of the battery.
In addition, the most common metallization method in the industrialization of the crystalline silicon solar cell is screen printing and sintering, and different from the PVD isothermal metallization method, the screen printing and sintering process can cause the metal to penetrate through the tunneling oxide layer/doped polysilicon and directly contact with the silicon substrate, which leads to the rapid increase of the recombination under the metal region and the deterioration of the contact. For silver-aluminum paste, the penetration of metal through the oxide layer/doped polysilicon is more severe.
The processes such as photoresist masking and PVD metal electrode deposition belong to laboratory technologies, are not suitable for large-scale mass production of enterprises, combine the excellent optical characteristics of the IBC structure with the excellent electrical characteristics of the passivation contact structure in order to improve the conversion efficiency of the solar cell, and have important significance in preparing the passivation contact IBC cell which has less mask processing times, low cell leakage and is suitable for large-scale mass production.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a back contact solar cell with various tunnel junction structures.
The invention relates to a back contact solar cell with various tunnel junction structures, which adopts the technical scheme that: the method comprises the following steps:
(1) growing a tunneling oxide layer on the back surface of the N-type crystal silicon substrate, and depositing an intrinsic polycrystalline silicon layer on the tunneling oxide layer to form c-Si/SiOXA/i-poly tunnel junction; depositing an Oxide layer on the intrinsic polycrystalline silicon layer, and depositing the intrinsic polycrystalline silicon layer on the Oxide layer to form an i-poly/Oxide/i-poly tunnel junction;
(2) depositing a mask on the n + doped region on the front surface, doping phosphorus into the intrinsic polysilicon layer, activating or propelling phosphorus atoms at high temperature to convert the intrinsic polysilicon layer into a phosphorus-doped polysilicon layer to form c-Si/SiOXA/n + poly tunnel junction and an n + poly/Oxide/n + poly tunnel junction, and a phosphorus-containing silicon Oxide layer is formed on the outer phosphorus-doped polycrystalline silicon layer;
(3) removing partial phosphorus-containing silicon oxide layer and c-Si/SiO on the back of the N-type crystal silicon substrateXA/n + poly tunnel junction, and an n + poly/Oxide/n + poly tunnel junction;
(4) putting the N-type crystal silicon substrate into an alkaline solution for isotropic etching, wherein in the etching process, the area covered by the phosphorus-containing silicon oxide layer on the N-type crystal silicon substrate is not etched, and the area uncovered by the phosphorus-containing silicon oxide layer is etched into an invaginated groove structure by an alkaline solution;
(5) placing the N-type crystal silicon substrate into an acid solution, and removing the mask of the N + doped region on the front surface of the N-type crystal silicon substrate and the phosphorus-containing silicon oxide layer on the back surface of the N-type crystal silicon substrate;
(6) growing a tunneling oxide layer on the back of the N-type crystal silicon substrate, and depositing an in-situ boron-doped polycrystalline silicon layer on the tunneling oxide layer to form N + poly/SiO in the region without the groove structure on the back of the N-type crystal silicon substrateXA/p + poly tunnel junction, wherein c-Si/SiO is formed at the bottom of the groove structureXA/p + poly tunnel junction; and annealing treatment is carried out to convert the in-situ boron-doped polycrystalline silicon layer into a boron-doped polycrystalline silicon layer.
The invention provides a preparation method of a back contact solar cell with various tunnel junction structures, which further comprises the following auxiliary technical scheme:
wherein, prior to step (1), the method further comprises:
(1) selecting an N-type crystal silicon substrate, cleaning the surface of the N-type crystal silicon substrate, and manufacturing a textured surface;
(2) performing phosphorus diffusion on the texturing surface of the N-type crystal silicon substrate to form a double-sided N + doped region;
(3) and etching the back surface of the N-type crystal silicon substrate, and polishing to remove the N + doped region on the back surface of the N-type crystal silicon substrate.
Wherein, the method also comprises:
(7) depositing a passivation film on the back surface of the N-type crystalline silicon substrate treated in the step (6), and depositing an anti-reflection film on the front surface of the N-type crystalline silicon substrate;
(8) and forming a metal grid line with an interdigital structure on the N-type back surface field region and the P-type emitter region on the back surface of the N-type crystal silicon substrate.
Wherein, the groove structure is an arc groove structure, the maximum width of the groove structure is 0.9-1.8 mm, and the depth of the groove structure is 3-10 μm.
Wherein, the c-Si/SiOXA/n + poly tunnel junction, and c-Si/SiOXSiO in/p + poly tunnel junctionXIs a tunneling oxide layer with a thickness of 0.5-3.5nm and grown by thermal oxidation and HNO3Oxidation, O3Oxidation, or atomic layer deposition;
the Oxide in the n + poly/Oxide/n + poly tunnel junction is an Oxide layer, the thickness of the Oxide layer is 2.0-15nm, and the growth mode is PECVD or atomic layer deposition.
Wherein the oxide layer comprises silicon oxide, aluminum oxide, or titanium dioxide.
Wherein, the c-Si/SiOXThe n + poly tunnel junction and the n + poly/Oxide/n + poly tunnel junction are phosphorus-doped polycrystalline silicon layers, the thickness of each polycrystalline silicon layer is 50-300nm, and the polycrystalline silicon layers are formed in a deposition mode or a doping mode; wherein the content of the first and second substances,
the deposition mode comprises the steps of carrying out low-pressure chemical deposition on a polycrystalline silicon layer mixed with microcrystalline silicon phase intrinsically, wherein the deposition temperature is 550-650 ℃;
the doping mode comprises ion implantation of phosphorus atoms, phosphorus diffusion or atmospheric pressure chemical vapor deposition of phosphosilicate glass;
if the doping mode is ion implantation of phosphorus atoms or normal-pressure chemical vapor deposition of phosphosilicate glass, after the doping process is finished, annealing treatment is required, the annealing temperature is 800-950 ℃, and the annealing time is 5-60 min; after annealing, the c-Si/SiOXThe overall square resistance values of the/n + poly tunnel junction and the n + poly/Oxide/n + poly tunnel junction are 30-200 Ω/sq.
Wherein, in the n + poly/SiOXIn a/p + poly tunnel junction: the p + poly is a boron-doped polycrystalline silicon layer, the deposition mode is physical vapor deposition of polycrystalline silicon doped with boron atoms in situ, high-temperature annealing treatment is carried out, the annealing temperature is 800-950 ℃, the annealing time is 5-60 min, and the square resistance value after annealing is 30-200 omega/sq.
Wherein, in the n + poly/SiOXIn the/p + poly tunnel junction, the doping concentration of n + poly is 2-6E +20cm-3The doping concentration range of p + poly is 1-4E +20cm-3。
The invention also discloses a back contact solar cell with various tunnel junction structures, which comprises an N-type crystal silicon substrate,
the front surface of the N-type crystal silicon substrate comprises a lightly doped N + surface field and a passivated antireflection film;
the back surface of the N-type crystal silicon substrate comprises a P-type emitter region, an N-type back surface field region and a groove structure; the P-type emitter region is located in the groove structure, and the N-type back surface field region is located above the groove structure;
the N-type back surface field region sequentially comprises tunneling SiO from inside to outsideXLayer, n + poly layer, oxide layer, n + poly layer, tunneling SiOXA layer, and a p + poly layer; wherein the content of the first and second substances,
SiOXthe layer and the N + poly layer form c-Si/SiO in the N-type back surface field areaXa/N + poly tunnel junction is formed in the N-type back surface field region by the Oxide layer and the N + poly layer, and a tunnel junction of N + poly/Oxide/N + poly is formed in the N-type back surface field region by tunneling SiOXThe layer and the p + poly layer form N + poly/SiO in the N-type back surface field regionXA/p + poly tunnel junction;
the P-type emitter region sequentially comprises a tunneling SiOx layer and a P + poly layer from inside to outside; the SiOXThe layer and the P + poly layer form c-Si/SiO in the P-type emitter regionXA/p + poly tunnel junction;
the P-type emitter region is provided with a P-type metal electrode, and the N-type back surface field region is provided with an N-type metal electrode.
The width of the P-type emitter region is 0.9-1.8 mm, and the width of the N-type back surface field region is 0.6-1.4 mm;
the front surface and the back surface of the N-type crystal silicon substrate are both provided with laminated dielectric films; wherein the content of the first and second substances,
the front surface of the N-type crystal silicon substrate is provided with SiO2/SiNXLaminated passivated antireflection film, SiO2The thickness of the layer is 3-15 nm, SiNXThe thickness of the layer is 60-80 nm;
the back surface of the N-type crystal silicon substrate is provided with SiOX、SiNXOr Al2O3Any two of the above layers are used for passivating the antireflection film; or the back surface of the N-type crystal silicon substrate is provided with SiOX、SiNXAnd Al2O3And (5) laminating and passivating the antireflection film.
The implementation of the invention comprises the following technical effects:
the grid lines of the back contact battery are all positioned on the back of the battery, and the front surface is not shielded by metal, so that the optical loss can be obviously reduced; tunneling oxide layerThe passivated metal contact structure has the characteristics of low contact resistivity and low surface recombination, and can obviously reduce recombination loss and resistance loss. Therefore, the combination of the back contact cell structure and the tunnel oxide layer passivation metal contact structure can significantly improve the conversion efficiency of the cell. However, the passivated metal contact cell of the back contact structure reported in the literature has a number of technical difficulties: 1) the preparation process (such as photoetching technology and thermal evaporation electrode technology) belongs to the laboratory technology, and is suitable for small-size cell-4 cm2Large-scale batch production on full-size silicon chips is difficult to realize; 2) a multi-step mask process is required; 3) the spacing between the back emitter and the back field needs to be precisely controlled to prevent leakage; 4) precise alignment metallization techniques are required.
The invention creatively introduces a plurality of tunnel junction structures and arc groove structures into the back contact battery, and can effectively solve the technical difficulties: 1. by utilizing the back contact structure, the front surface is not shielded by grid lines, and the optical loss is obviously reduced; 2. by utilizing various tunnel junction structures, extremely low surface recombination rate and contact resistivity are obtained, and recombination loss and contact loss in electricity are remarkably reduced, so that higher conversion efficiency is obtained, and the mask frequency can be reduced; 3. by adopting the arc-shaped groove structure, the self-mask can be realized, the self-alignment of the emitter and the BSF can be realized, the accurate alignment of the screen printing is convenient, the process steps are obviously reduced, the mask frequency and the process difficulty are reduced, a new realization way is provided for the application of the passivated metal contact structure in the back contact battery, and the method is suitable for large-scale mass production.
Drawings
Fig. 1 is a schematic cross-sectional view of a cell structure after a first step of a method for manufacturing a back contact solar cell having multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a cell structure after a second step of a method for manufacturing a back contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a cell structure after a third step of a method for manufacturing a back contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a cell structure after a fourth step of a method for manufacturing a back contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a cell structure after step five of a method for manufacturing a back contact solar cell having multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a cell structure after sixth step of a method for manufacturing a back contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a cell structure after a seventh step of a method for manufacturing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of a cell structure after step eight of a method for manufacturing a back contact solar cell having multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of a cell structure after ninth step of a method for manufacturing a back contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of a cell structure ten times after the step of a method for manufacturing a back contact solar cell having multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view of a cell structure after eleventh step of a method for manufacturing a back contact solar cell having multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view of a cell structure after twelfth step of a method for manufacturing a back-contact solar cell having multiple tunnel junction structures according to an embodiment of the present invention.
Fig. 13 is a schematic cross-sectional view of a cell structure after thirteen steps of a method for manufacturing a back-contact solar cell having multiple tunnel junction structures, in other words, a structural diagram of a back-contact solar cell having multiple tunnel junction structures according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to examples.
The present invention is not limited to the above-described embodiments, and those skilled in the art can make modifications to the embodiments without any inventive contribution as required after reading the present specification, but only protected within the scope of the appended claims.
The invention provides a preparation method of a back contact solar cell with various tunnel junction structures, which comprises the following steps:
(1) growing a tunneling oxide layer on the back surface of the N-type crystal silicon substrate, and depositing an intrinsic polycrystalline silicon layer on the tunneling oxide layer to form c-Si/SiOXA/i-poly tunnel junction; depositing an Oxide layer on the intrinsic polycrystalline silicon layer, and depositing the intrinsic polycrystalline silicon layer on the Oxide layer to form an i-poly/Oxide/i-poly tunnel junction;
(2) firstly, depositing a mask in the n + doped region on the front surface; then, the intrinsic polycrystalline silicon layer is doped with phosphorus, and phosphorus atoms are activated or pushed at high temperature to convert the intrinsic polycrystalline silicon layer into a phosphorus-doped polycrystalline silicon layer to form c-Si/SiOXA/n + poly tunnel junction and an n + poly/Oxide/n + poly tunnel junction, and a phosphorus-containing silicon Oxide layer is formed on the outer phosphorus-doped polycrystalline silicon layer;
(3) removing partial phosphorus-containing silicon oxide layer and c-Si/SiO on the back of the N-type crystal silicon substrateXA/n + poly tunnel junction, and an n + poly/Oxide/n + poly tunnel junction;
(4) putting the N-type crystal silicon substrate into an alkaline solution for isotropic etching, wherein in the etching process, the area covered by the phosphorus-containing silicon oxide layer on the N-type crystal silicon substrate is not etched, and the area uncovered by the phosphorus-containing silicon oxide layer is etched into an invaginated groove structure by an alkaline solution;
(5) placing the N-type crystal silicon substrate into an acid solution, and removing the mask of the N + doped region on the front surface of the N-type crystal silicon substrate and the phosphorus-containing silicon oxide layer on the back surface of the N-type crystal silicon substrate;
(6) growing a tunneling oxide layer on the back of the N-type crystal silicon substrate, and depositing an in-situ boron-doped polycrystalline silicon layer on the tunneling oxide layer so as not to arrange a layer of boron on the back of the N-type crystal silicon substrateN + poly/SiO is formed in the region with groove structureXA/p + poly tunnel junction, wherein c-Si/SiO is formed at the bottom of the groove structureXA/p + poly tunnel junction; and annealing treatment is carried out to convert the in-situ boron-doped polycrystalline silicon layer into a boron-doped polycrystalline silicon layer.
Preferably, the method further comprises:
(1) selecting an N-type crystal silicon substrate, cleaning the surface of the N-type crystal silicon substrate, and manufacturing a textured surface;
(2) performing phosphorus diffusion on the texturing surface of the N-type crystal silicon substrate to form a double-sided N + doped region;
(3) and etching the back surface of the N-type crystal silicon substrate, and polishing to remove the N + doped region on the back surface of the N-type crystal silicon substrate.
Preferably, the method further comprises:
(7) depositing a passivation film on the back surface of the N-type crystalline silicon substrate treated in the step (6), and depositing an anti-reflection film on the front surface of the N-type crystalline silicon substrate;
(8) and forming a metal grid line with an interdigital structure on the N-type back surface field region and the P-type emitter region on the back surface of the N-type crystal silicon substrate.
Wherein, the groove structure is an arc groove structure, the maximum width of the groove structure is 0.9-1.8 mm, and the depth of the groove structure is 3-10 μm.
Preferably, the c-Si/SiOXA/n + poly tunnel junction, and c-Si/SiOXSiO in/p + poly tunnel junctionXIs a tunneling oxide layer with a thickness of 0.5-3.5nm and grown by thermal oxidation and HNO3Oxidation, O3Oxidation, or atomic layer deposition;
the Oxide in the n + poly/Oxide/n + poly tunnel junction is an Oxide layer, the thickness of the Oxide layer is 2.0-15nm, and the growth mode is PECVD or atomic layer deposition.
Wherein the oxide layer comprises silicon oxide, aluminum oxide, or titanium dioxide.
Preferably, the c-Si/SiOXN + poly tunnel junctions and n + poly/Oxide/n + poly tunnel junctions are phosphorus doped polysilicon layers with a thickness of 50-300nm formed by depositionFormula (II) or doping; wherein the content of the first and second substances,
the deposition mode comprises the steps of carrying out low-pressure chemical deposition on a polycrystalline silicon layer mixed with microcrystalline silicon phase intrinsically, wherein the deposition temperature is 550-650 ℃;
the doping mode comprises ion implantation of phosphorus atoms, phosphorus diffusion or atmospheric pressure chemical vapor deposition of phosphosilicate glass;
if the doping mode is ion implantation of phosphorus atoms or normal-pressure chemical vapor deposition of phosphosilicate glass, after the doping process is finished, annealing treatment is required, the annealing temperature is 800-950 ℃, and the annealing time is 5-60 min; after annealing, the c-Si/SiOXThe overall square resistance values of the/n + poly tunnel junction and the n + poly/Oxide/n + poly tunnel junction are 30-200 Ω/sq.
Preferably, in the n + poly/SiOXIn a/p + poly tunnel junction:
the p + poly is a boron-doped polycrystalline silicon layer, the deposition mode is physical vapor deposition of polycrystalline silicon doped with boron atoms in situ, high-temperature annealing treatment is carried out, the annealing temperature is 800-950 ℃, the annealing time is 5-60 min, and the square resistance value after annealing is 30-200 omega/sq.
Preferably, in the n + poly/SiOXIn the/p + poly tunnel junction,
the doping concentration of n + poly is 2-6E +20cm-3The doping concentration range of p + poly is 1-4E +20cm-3。
The invention also discloses a back contact solar cell with various tunnel junction structures, which comprises an N-type crystal silicon substrate,
the front surface of the N-type crystal silicon substrate comprises a lightly doped N + surface field and a passivated antireflection film;
the back surface of the N-type crystal silicon substrate comprises a P-type emitter region, an N-type back surface field region and a groove structure; the P-type emitter region is located in the groove structure, and the N-type back surface field region is located above the groove structure;
the N-type back surface field region sequentially comprises tunneling SiO from inside to outsideXLayer, n + poly layer, oxide layer, n + poly layer, tunneling SiOXA layer, and a p + poly layer; wherein the content of the first and second substances,
SiOXthe layer and the N + poly layer form c-Si/SiO in the N-type back surface field areaXa/N + poly tunnel junction is formed in the N-type back surface field region by the Oxide layer and the N + poly layer, and a tunnel junction of N + poly/Oxide/N + poly is formed in the N-type back surface field region by tunneling SiOXThe layer and the p + poly layer form N + poly/SiO in the N-type back surface field regionXA/p + poly tunnel junction;
the P-type emitter region sequentially comprises a tunneling SiOx layer and a P + poly layer from inside to outside; the SiOXThe layer and the P + poly layer form c-Si/SiO in the P-type emitter regionXA/p + poly tunnel junction;
the P-type emitter region is provided with a P-type metal electrode, and the N-type back surface field region is provided with an N-type metal electrode.
The width of the P-type emitter region is 0.1-10 mm, and the width of the N-type back surface field region is 0.1-10 mm; preferably, the width of the P-type emitter region is 0.9-1.8 mm, and the width of the N-type back surface field region is 0.6-1.4 mm;
preferably, the front surface and the back surface of the N-type crystal silicon substrate are both provided with laminated dielectric films; wherein the content of the first and second substances,
the front surface of the N-type crystal silicon substrate is provided with SiO2/SiNXLaminated passivated antireflection film, SiO2The thickness of the layer is 3-15 nm, SiNXThe thickness of the layer is 60-80 nm;
the back surface of the N-type crystal silicon substrate is provided with SiOX、SiNXOr Al2O3Any two of the above layers are used for passivating the antireflection film; or the back surface of the N-type crystal silicon substrate is provided with SiOX、SiNXAnd Al2O3And (5) laminating and passivating the antireflection film.
Aiming at the defects of high technical threshold (photoetching technology), multiple mask times, incompatibility with industrialized sintering process and the like of the existing passivated contact cell with the IBC structure, the invention provides a passivated metal contact solar cell with various tunnel junction structures and a preparation method thereof. Wherein the plurality of tunnel junction structures are capable of: 1) regulating and controlling the doping distribution of phosphorus atoms in the monocrystalline silicon substrate to obtain lower surface recombination rate; 2) avoiding the metal electrode from penetrating through the doped polycrystalline silicon layer to directly contact the silicon substrate in the sintering process, greatly reducing the metal contact recombination, and 3) obviously reducing the mask frequency, realizing the preparation of the back structure of the cell through self-masking, and needing no additional mask process on the back.
The arc groove structure can: 1) the phosphorus-doped polycrystalline silicon layer and the boron-doped polycrystalline silicon layer in the back contact battery are isolated in space, so that the self-alignment of an emitter and BSF is realized, and the electric leakage of the battery is remarkably reduced; 2) during screen printing, the height difference that the arc recess arouses can show the contrast of light and shade difference when counterpointing the camera formation of image, the accurate counterpoint of the printing machine of being convenient for.
First tunnel junction c-Si/SiO in multiple tunnel junctionsXN + poly or c-Si/SiOXThe function of the/p + poly is to passivate the contact interface of the n-type crystalline silicon substrate to obtain extremely low surface recombination rate, SiOXThe/n + poly can be obtained in the contact region to be less than 5fA/cm2J0 value of (A), SiOXThe/p + poly can be obtained in the contact region to be less than 10fA/cm2The J0 value of (A) can significantly reduce the recombination loss of the surface.
The second tunnel junction n + poly/Oxide/n + poly in the multiple tunnel junctions has the function of regulating and controlling the doping distribution of phosphorus atoms.
It should be noted that n + poly needs to undergo two annealing processes in the present invention: the first time is to activate phosphorus atoms in n + poly and to completely crystallize into polysilicon, and the second time is to activate boron atoms in p + poly and to completely crystallize p + poly. Therefore, the doping distribution of phosphorus atoms in n + poly and n-type crystalline silicon substrates is regulated and controlled through the n + poly/Oxide/n + poly structure in the two annealing processes, so that the very low surface recombination rate and the very low contact resistivity are particularly important.
The oxide layer material in the present invention, such as silicon oxide, titanium oxide, aluminum oxide, etc., has the following two characteristics: 1) lower diffusion coefficients for dopant atoms (e.g., phosphorus atoms) and 2) more difficult to burn through for metal pastes. By adopting different thicknesses and different types of oxide layer materials to separate the doped polycrystalline silicon layer, when doping atoms are diffused inwards from the surface of the polycrystalline silicon layer, most of the doping atoms can be blocked in the n + poly of the outer layer by the oxide layer (such as silicon oxide, titanium oxide, aluminum oxide and the like) with proper thickness, the excessive doping atoms are prevented from entering the n + poly of the inner layer (the side close to the n-Si) and the n-type crystalline silicon substrate, and the tail of the doping atoms in the silicon substrate is shallow.
The third kind of tunnel junction n + poly/SiO in multiple tunnel junctionsXThe function of the/p + poly is to transport carriers, corresponding to a wire.
In the invention, in order to reduce the mask times and reduce the process steps, an additional mask is not required to be added on n + poly when p + poly is physically deposited by vapor phase deposition. This results in the same material being deposited over n + poly as the emitter, namely: SiO 2XP + poly. In the process of secondary annealing, SiO in the middleXBoron atoms in p + poly are blocked from diffusing into n + poly, so that the transition of doping at the contact interface of n + poly and p + poly becomes very "sharp". The heavily doped n + poly and p + poly are degenerate semiconductors, the Fermi level in the p + poly is below the valence band, the Fermi level in the n + poly is above the conduction band, the valence band of the p + poly has a plurality of empty 'states' not occupied by electrons, the electrons in the conduction band in the n + poly can directly tunnel to the holes of the p + poly, the transmission of carriers is realized, and the function of the p + poly is equivalent to that of a wire.
The inventive method for fabricating a back contact solar cell having various tunnel junction structures will be described in detail with specific examples.
Example 1
(1) Cleaning the front surface and the back surface of the N-type crystal silicon substrate 1 respectively, removing the damaged layer and making a texture as shown in FIG. 1; wherein the N-type silicon substrate has a resistivity of 0.3 to 10 Ω & cm and a thickness of 90 to 300 μm.
(2) Performing double-sided phosphorus diffusion on the textured N-type crystal silicon substrate 1 to form a double-sided N + doped region 2, as shown in FIG. 2; wherein the phosphorus source adopts phosphorus oxychloride, the diffusion temperature is 800-1000 ℃, and the square resistance value of the n + doped region after phosphorus diffusion is 150-400 omega/sq.
(3) Etching and polishing the back surface of the N-type crystalline silicon substrate 1, as shown in fig. 3; and removing and polishing the n + doped region 2 on the back by adopting a heated TMAH or NaOH solution, wherein the weight of the silicon wafer is reduced to 0.1-0.5 g.
(4) Growing an ultrathin tunneling silicon dioxide layer 3 with a thickness of 1.1nm on the polished surface of the silicon wafer by thermal oxidation, and depositing a 50nm intrinsic polysilicon layer 41 (containing microcrystalline silicon phase) in a low-pressure chemical vapor deposition device to form a first c-Si/SiOXA/i-poly tunnel junction; then depositing a 5nm titanium dioxide layer 5 by atomic layer deposition, and then depositing a 150nm intrinsic polysilicon layer 42 (containing microcrystalline silicon phase) by using a low pressure chemical vapor deposition device again to form a second i-poly/Oxide/i-poly, as shown in FIG. 4; wherein the deposition temperature of the intrinsic polysilicon 41 and 42 is 550-650 ℃.
(5) Depositing a layer of SiO on the n + doped region 2 on the front surface by adopting PECVDXThe mask 6, as shown in FIG. 5, is 200nm thick.
(6) Doping the intrinsic polysilicon layer by ion implantation, as shown in fig. 6; the phosphorus source of the ion implanter is phosphine, and the implantation dosage is 6.0E +15cm-2After injecting phosphorus atoms, activating the silicon wafer at high temperature, wherein the annealing temperature is 875 ℃, oxygen is introduced during the annealing process, the annealing time is 60min, the intrinsic polycrystalline silicon layers 41 and 42 containing microcrystalline silicon phases are completely converted into phosphorus-doped polycrystalline silicon layers 71 and 72, and the doping concentration peak value of the intrinsic polycrystalline silicon layers 71 and 72 is 4E +20cm-3To form c-Si/SiOXThe junction structure comprises a/n + poly tunnel junction and an n + poly/Oxide/n + poly tunnel junction, and the overall square resistance value of the tunnel junction is 30-200 omega/sq. And a layer of phosphorus-containing silicon oxide layer 8 with the thickness of 40nm is formed on the surface after annealing due to the introduction of oxygen in the high-temperature process.
(7) Locally removing the phosphorus-containing silicon oxide layer, the polysilicon layers 71 and 72, the titanium dioxide layer 5 and the silicon dioxide layer 3 to the N-type silicon substrate 1 by using a picosecond laser with the laser wavelength of 532nm, wherein the laser energy density is set to be 1J-cm-2As shown in fig. 7; the film opening mode of the laser is equal-spacing array film opening, the width of the laser film opening is 1.2mm, and the laser spacing is 1.6 mm.
(8) Immersing the silicon chip into alkali liquor with high selective reaction ratio (Si: phosphorus-containing silicon oxide layer >100:1) for isotropic etching, protecting the area covered by the phosphorus-containing silicon oxide layer, and etching the area with the phosphorus-containing silicon oxide layer removed by laser by the alkali liquor to form an inward-concave arc-shaped groove structure 9 as shown in figure 8; the depth of the arc-shaped groove structure 9 is 4 μm, and the diameter of the inwardly recessed arc-shaped side wall is 4 μm.
(9) And removing the mask 6 of the n + doped region on the front surface and the phosphorus-containing silicon oxide layer 8 on the back surface by using an HF solution, wherein the volume fraction ratio of the HF solution is 5-20%, as shown in FIG. 9.
(10) Growing an ultrathin tunneling silicon dioxide layer 3 with the thickness range of 1.7nm on the back surface of the silicon wafer, then depositing an in-situ boron-doped polycrystalline silicon layer 10 with the thickness of 200nm by adopting a physical vapor deposition method, and forming a third tunnel junction n + poly/SiO in a region without laser film openingXA/p + poly, c-Si/SiO is formed at the bottom region of the arc-shaped groove structure 9XThe/p + poly tunnel junction, passivates the metal contacts, as shown in FIG. 10.
(11) Annealing the silicon wafer as shown in FIG. 11; the annealing temperature is 915 ℃, the annealing time is 5min, in the annealing process, boron atoms in the in-situ boron-doped polycrystalline silicon layer 10 can be completely activated to become a boron-doped polycrystalline silicon layer 11, the square resistance value after annealing is 90 omega/sq, and the doping concentration peak value of the boron-doped polycrystalline silicon layer 11 is 2E +20cm-3The transition of the doping atoms at the contact interface of the phosphorus-doped polysilicon layer 72 and the boron-doped polysilicon layer 11 is very sharp.
(12) Deposition of three layers of SiO on the back surface2/Al2O3/SiNXThe film 12 is used for surface passivation, as shown in FIG. 12, where the underlying SiO is2Layer thickness 1nm, intermediate Al2O3Thickness of 3nm, top layer SiNXThe layer thickness is 65nm, the refractive index is 2.2; then depositing SiO on the front surface2/SiNXThe laminated film 13 is used for antireflection and passivation, in which SiO2Layer thickness 5nm, SiNXThe layer thickness was 60nm and the refractive index 2.05.
(13) Forming metal grid lines 14 and 15 having an interdigital structure on the N-type back surface field region and the P-type emitter region of the back surface of the cell by means of screen printing and sintering, as shown in fig. 13; the width of the metal grid lines 14 is 150 μm, the number of the metal grid lines is 98, the width of the metal grid lines 15 is 90 μm, the number of the metal grid lines is 98, and the height of the metal grid lines is 10 μm.
Example 2
(1) Cleaning the front surface and the back surface of the N-type crystal silicon substrate 1 respectively, removing the damaged layer and making a texture as shown in FIG. 1; wherein the N-type silicon substrate has a resistivity of 0.3 to 10 Ω & cm and a thickness of 90 to 300 μm.
(2) Performing double-sided phosphorus diffusion on the textured N-type crystal silicon substrate 1 to form a double-sided N + doped region 2, as shown in FIG. 2; wherein the phosphorus source adopts phosphorus oxychloride, the diffusion temperature is 800-1000 ℃, and the square resistance value of the n + doped region after phosphorus diffusion is 150-400 omega/sq.
(3) Etching and polishing the back surface of the N-type crystalline silicon substrate 1, as shown in fig. 3; and removing and polishing the n + doped region 2 on the back by adopting a heated TMAH or NaOH solution, wherein the weight of the silicon wafer is reduced to 0.1-0.5 g.
(4) Growing an ultrathin tunneling silicon dioxide layer 3 with a thickness of 1.7nm on the polished surface of the silicon wafer by thermal oxidation, and depositing a 50nm intrinsic polysilicon layer 41 (containing microcrystalline silicon phase) in a low-pressure chemical vapor deposition device to form a first c-Si/SiOXA/i-poly tunnel junction; then, using PECVD technology to deposit a 5nm alumina layer 5, and then using low pressure chemical vapor deposition equipment to deposit a 150nm intrinsic polysilicon layer 42 (containing microcrystalline silicon phase) again to form a second i-poly/Oxide/i-poly, as shown in FIG. 4; wherein the deposition temperature of the intrinsic polysilicon 41 and 42 is 550-650 ℃.
(5) Depositing a layer of SiO on the n + doped region 2 on the front surface by adopting PECVDXThe mask 6, as shown in FIG. 5, has a thickness of 200 nm.
(6) Doping the intrinsic polysilicon layer by ion implantation, as shown in fig. 6; the phosphorus source of the ion implanter is phosphine, and the implantation dosage is 6.0E +15cm-2After injecting phosphorus atoms, activating the silicon wafer at high temperature, wherein the annealing temperature is 875 ℃, oxygen is introduced during the annealing process, the annealing time is 60min, and the intrinsic polycrystalline silicon layers 41 and 42 containing microcrystalline silicon phases are completely converted into phosphorus-doped polycrystalline silicon layers 71 and phosphorus-doped polycrystalline silicon layers72, 71 and 72 have a peak doping concentration of 4E +20cm-3To form c-Si/SiOXThe junction structure comprises a/n + poly tunnel junction and an n + poly/Oxide/n + poly tunnel junction, and the overall square resistance value of the tunnel junction is 30-200 omega/sq. And a layer of phosphorus-containing silicon oxide layer 8 with the thickness of 40nm is formed on the surface after annealing due to the introduction of oxygen in the high-temperature process.
(7) Locally removing the phosphorus-containing silicon oxide layer 8, the polysilicon layers 71 and 72, the aluminum oxide layer 5 and the silicon dioxide layer 3 to the N-type silicon substrate 1 by using a picosecond laser with a laser wavelength of 532nm, wherein the laser energy density is set to 1J-cm-2As shown in fig. 7; the film opening mode of the laser is equal-spacing array film opening, the width of the laser film opening is 1.2mm, and the laser spacing is 1.6 mm.
(8) Immersing the silicon chip into alkali liquor with high selective reaction ratio (Si: phosphorus-containing silicon oxide layer >100:1) for isotropic etching, protecting the area covered by the phosphorus-containing silicon oxide layer, and etching the area with the phosphorus-containing silicon oxide layer removed by laser by the alkali liquor to form an inward-concave arc-shaped groove structure 9 as shown in figure 8; the depth of the arc-shaped groove structure 9 is 4 μm, and the diameter of the inwardly recessed arc-shaped side wall is 4 μm.
(9) And removing the mask 6 of the n + doped region on the front surface and the phosphorus-containing silicon oxide layer 8 on the back surface by using an HF solution, wherein the volume fraction ratio of the HF solution is 8-16%, as shown in FIG. 9.
(10) Growing an ultrathin tunneling silicon dioxide layer 3 with the thickness of 1.7nm on the back surface of the silicon wafer, then depositing an in-situ boron-doped polycrystalline silicon layer 10 with the thickness of 200nm by adopting a physical vapor deposition method, and forming a third tunnel junction n + poly/SiO in a region without laser film openingXA/p + poly, c-Si/SiO is formed at the bottom region of the arc-shaped groove structure 9XThe/p + poly tunnel junction, passivates the metal contacts, as shown in FIG. 10.
(11) Annealing the silicon wafer as shown in FIG. 11; the annealing temperature is 915 ℃, the annealing time is 5min, in the annealing process, boron atoms in the in-situ boron-doped polycrystalline silicon layer 10 can be completely activated to become a boron-doped polycrystalline silicon layer 11, the square resistance value after annealing is 90 omega/sq, and the doping concentration peak value of the boron-doped polycrystalline silicon layer 11 is 2E +20cm-3Doping atoms in the phosphorus doped polysilicon layer 72 and the boron doped polysilicon layerThe transition at the contact interface of the layer 11 is very sharp.
(12) Deposition of three layers of SiO on the back surface2/Al2O3The film 12 is used for surface passivation, as shown in FIG. 12, where the underlying SiO is2Layer thickness of 5nm, intermediate Al2O3Thickness of 60nm, refractive index of 2.2; then depositing SiO on the front surface2/SiNXThe laminated film 13 is used for antireflection and passivation, in which SiO2Layer thickness 10nm, SiNXThe layer thickness was 80nm and the refractive index 2.05.
(13) Forming metal grid lines 14 and 15 having an interdigital structure on the N-type back surface field region and the P-type emitter region of the back surface of the cell by means of screen printing and sintering, as shown in fig. 13; the width of the metal grid lines 14 is 150 μm, the number of the metal grid lines is 98, the width of the metal grid lines 15 is 90 μm, the number of the metal grid lines is 98, and the height of the metal grid lines is 30 μm.
Example 3
(1) Cleaning the front surface and the back surface of the N-type crystal silicon substrate 1 respectively, removing the damaged layer and making a texture as shown in FIG. 1; wherein the N-type silicon substrate has a resistivity of 0.3 to 10 Ω & cm and a thickness of 90 to 300 μm.
(2) Performing double-sided phosphorus diffusion on the textured N-type crystal silicon substrate 1 to form a double-sided N + doped region 2, as shown in FIG. 2; wherein the phosphorus source adopts phosphorus oxychloride, the diffusion temperature is 800-1000 ℃, and the square resistance value of the n + doped region after phosphorus diffusion is 150-400 omega/sq.
(3) Etching and polishing the back surface of the N-type crystalline silicon substrate 1, as shown in fig. 3; and removing and polishing the n + doped region 2 on the back by adopting a heated TMAH or NaOH solution, wherein the weight of the silicon wafer is reduced to 0.1-0.5 g.
(4) Growing an ultrathin tunneling silicon dioxide layer 3 with a thickness of 1.4nm on the polished surface of the silicon wafer by thermal oxidation, and depositing a 50nm intrinsic polysilicon layer 41 (containing microcrystalline silicon phase) in a low-pressure chemical vapor deposition device to form a first c-Si/SiOXA/i-poly tunnel junction; then depositing a 5nm alumina layer 5 by atomic layer deposition, and then depositing a 150nm intrinsic polysilicon layer 42 (containing microcrystalline silicon phase) by low pressure chemical vapor depositionA second i-poly/Oxide/i-poly, as shown in FIG. 4; wherein the deposition temperature of the intrinsic polysilicon 41 and 42 is 550-650 ℃.
(5) Depositing a layer of SiO on the n + doped region 2 on the front surface by adopting PECVDXThe mask 6, as shown in FIG. 5, is 200nm thick.
(6) Doping the intrinsic polysilicon layer by ion implantation, as shown in fig. 6; the phosphorus source of the ion implanter is phosphine, and the implantation dosage is 6.0E +15cm-2After injecting phosphorus atoms, activating the silicon wafer at high temperature, wherein the annealing temperature is 875 ℃, oxygen is introduced during the annealing process, the annealing time is 60min, the intrinsic polycrystalline silicon layers 41 and 42 containing microcrystalline silicon phases are completely converted into phosphorus-doped polycrystalline silicon layers 71 and 72, and the doping concentration peak value of the intrinsic polycrystalline silicon layers 71 and 72 is 4E +20cm-3To form c-Si/SiOXThe junction structure comprises a/n + poly tunnel junction and an n + poly/Oxide/n + poly tunnel junction, and the overall square resistance value of the tunnel junction is 30-200 omega/sq. And a layer of phosphorus-containing silicon oxide layer 8 with the thickness of 40nm is formed on the surface after annealing due to the introduction of oxygen in the high-temperature process.
(7) Locally removing the phosphorus-containing silicon oxide layer, the polysilicon layers 71 and 72, the alumina 5 and the silicon dioxide layer 3 to the N-type silicon substrate 1 by using a picosecond laser with a laser wavelength of 532nm, wherein the laser energy density is set to 1J-cm-2As shown in fig. 7; the film opening mode of the laser is equal-spacing array film opening, the width of the laser film opening is 1.2mm, and the laser spacing is 1.6 mm.
(8) Immersing the silicon chip into alkali liquor with high selective reaction ratio (Si: phosphorus-containing silicon oxide layer >100:1) for isotropic etching, protecting the area covered by the phosphorus-containing silicon oxide layer, and etching the area with the phosphorus-containing silicon oxide layer removed by laser by the alkali liquor to form an inward-concave arc-shaped groove structure 9 as shown in figure 8; the depth of the arc-shaped groove structure 9 is 4 μm, and the diameter of the inwardly recessed arc-shaped side wall is 4 μm.
(9) The mask 6 of the n + doped region on the front surface and the phosphorus-containing silicon oxide layer 8 on the back surface were removed by using an HF solution, as shown in fig. 9, the volume fraction ratio of the HF solution was 15%.
(10) Growing an ultrathin tunneling silicon dioxide layer 3 with the thickness of 1.7nm on the back surface of the silicon wafer, and then adoptingDepositing an in-situ boron-doped polycrystalline silicon layer 10 by physical vapor deposition, wherein the thickness is 200nm, and forming a third tunnel junction n + poly/SiO in a region without laser film openingXA/p + poly, c-Si/SiO is formed at the bottom region of the arc-shaped groove structure 9XThe/p + poly tunnel junction, passivates the metal contacts, as shown in FIG. 10.
(11) Annealing the silicon wafer as shown in FIG. 11; the annealing temperature is 915 ℃, the annealing time is 5min, in the annealing process, boron atoms in the in-situ boron-doped polycrystalline silicon layer 10 can be completely activated to become a boron-doped polycrystalline silicon layer 11, the square resistance value after annealing is 90 omega/sq, and the doping concentration peak value of the boron-doped polycrystalline silicon layer 11 is 2E +20cm-3The transition of the doping atoms at the contact interface of the phosphorus-doped polysilicon layer 72 and the boron-doped polysilicon layer 11 is very sharp.
(12) Depositing two layers of Al on the back surface2O3/SiNXThe film 12 is used for surface passivation, as shown in FIG. 12, where the bottom layer is Al2O3Thickness of 6nm, top layer SiNXThe layer thickness is 45nm, the refractive index is 2.2; then depositing SiO on the front surface2/SiNXThe laminated film 13 is used for antireflection and passivation, in which SiO2Layer thickness of 8nm, SiNXThe layer thickness was 70nm and the refractive index 2.05.
(13) Forming metal grid lines 14 and 15 having an interdigital structure on the N-type back surface field region and the P-type emitter region of the back surface of the cell by means of screen printing and sintering, as shown in fig. 13; the width of the metal grid lines 14 is 150 μm, the number of the metal grid lines is 98, the width of the metal grid lines 15 is 90 μm, the number of the metal grid lines is 98, and the height of the metal grid lines is 20 μm.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims (13)

1. A preparation method of a back contact solar cell with various tunnel junction structures is characterized by comprising the following steps: the method comprises the following steps:
(1) growing a tunneling oxide layer on the back surface of the N-type crystal silicon substrate, and depositing an intrinsic polycrystalline silicon layer on the tunneling oxide layer to form c-Si/SiOXA/i-poly tunnel junction; depositing an Oxide layer on the intrinsic polycrystalline silicon layer, and depositing the intrinsic polycrystalline silicon layer on the Oxide layer to form an i-poly/Oxide/i-poly tunnel junction;
(2) after a mask is deposited in the n + doped region on the front surface, phosphorus doping is carried out on the intrinsic polycrystalline silicon layer, and phosphorus atoms are activated or pushed at high temperature to convert the intrinsic polycrystalline silicon layer into a phosphorus-doped polycrystalline silicon layer to form a c-Si/SiOXA/n + poly tunnel junction and an n + poly/Oxide/n + poly tunnel junction, and a phosphorus-containing silicon Oxide layer is formed on the outer phosphorus-doped polycrystalline silicon layer;
(3) removing partial phosphorus-containing silicon oxide layer and c-Si/SiO on the back of the N-type crystal silicon substrateXA/n + poly tunnel junction, and an n + poly/Oxide/n + poly tunnel junction;
(4) putting the N-type crystal silicon substrate into an alkaline solution for isotropic etching, wherein in the etching process, the area covered by the phosphorus-containing silicon oxide layer on the N-type crystal silicon substrate is not etched, and the area uncovered by the phosphorus-containing silicon oxide layer is etched into an invaginated groove structure by an alkaline solution;
(5) placing the N-type crystal silicon substrate into an acid solution, and removing the mask of the N + doped region on the front surface of the N-type crystal silicon substrate and the phosphorus-containing silicon oxide layer on the back surface of the N-type crystal silicon substrate;
(6) growing a tunneling oxide layer on the back of the N-type crystal silicon substrate, and depositing an in-situ boron-doped polycrystalline silicon layer on the tunneling oxide layer to form N + poly/SiO in the region without the groove structure on the back of the N-type crystal silicon substrateXA/p + poly tunnel junction, wherein c-Si/SiO is formed at the bottom of the groove structureXA/p + poly tunnel junction; and annealing treatment is carried out to convert the in-situ boron-doped polycrystalline silicon layer into a boron-doped polycrystalline silicon layer.
2. The method of claim 1, wherein prior to step (1), the method further comprises:
(1) selecting an N-type crystal silicon substrate, cleaning the surface of the N-type crystal silicon substrate, and manufacturing a textured surface;
(2) performing phosphorus diffusion on the texturing surface of the N-type crystal silicon substrate to form a double-sided N + doped region;
(3) and etching the back surface of the N-type crystal silicon substrate, and polishing to remove the N + doped region on the back surface of the N-type crystal silicon substrate.
3. The method of manufacturing according to claim 2, further comprising:
(7) depositing a passivation film on the back surface of the N-type crystalline silicon substrate treated in the step (6), and depositing an anti-reflection film on the front surface of the N-type crystalline silicon substrate;
(8) and forming a metal grid line with an interdigital structure on the N-type back surface field region and the P-type emitter region on the back surface of the N-type crystal silicon substrate.
4. The production method according to any one of claims 1 to 3, wherein the groove structure is an arc-shaped groove structure having a maximum width of 0.9 to 1.8mm and a depth of 3 to 10 μm.
5. The production method according to claim 4,
the c-Si/SiOXA/n + poly tunnel junction, and c-Si/SiOXSiO in/p + poly tunnel junctionXIs a tunneling oxide layer with a thickness of 0.5-3.5nm and grown by thermal oxidation and HNO3Oxidation, O3Oxidation, or atomic layer deposition;
the Oxide in the n + poly/Oxide/n + poly tunnel junction is an Oxide layer, the thickness of the Oxide layer is 2.0-15nm, and the growth mode is PECVD or atomic layer deposition.
6. The production method according to claim 5, wherein the oxide layer comprises silicon oxide, aluminum oxide, or titanium oxide.
7. The method of claim 4Characterized in that the c-Si/SiOXThe n + poly tunnel junction and the n + poly/Oxide/n + poly tunnel junction are phosphorus-doped polycrystalline silicon layers, the thickness of each polycrystalline silicon layer is 50-300nm, and the polycrystalline silicon layers are formed in a deposition mode or a doping mode; wherein the content of the first and second substances,
the deposition mode comprises the steps of carrying out low-pressure chemical deposition on a polycrystalline silicon layer mixed with microcrystalline silicon phase intrinsically, wherein the deposition temperature is 550-650 ℃;
the doping method comprises ion implantation of phosphorus atoms, phosphorus diffusion or atmospheric pressure chemical vapor deposition of phosphosilicate glass.
8. The preparation method according to claim 7, wherein the doping method is ion implantation of phosphorus atoms or atmospheric pressure chemical vapor deposition of phosphosilicate glass, and after the doping process is completed, annealing treatment is required, wherein the annealing temperature is 800-950 ℃, and the annealing time is 5-60 min; after annealing, the c-Si/SiOXThe overall square resistance values of the/n + poly tunnel junction and the n + poly/Oxide/n + poly tunnel junction are 30-200 Ω/sq.
9. The method of claim 4, wherein n + poly/SiOXIn a/p + poly tunnel junction: the p + poly is a boron-doped polycrystalline silicon layer, the deposition mode is physical vapor deposition of polycrystalline silicon doped with boron atoms in situ, high-temperature annealing treatment is carried out, the annealing temperature is 800-950 ℃, the annealing time is 5-60 min, and the square resistance value after annealing is 30-200 omega/sq.
10. The method of claim 9, wherein n + poly/SiO is present in the compositionXIn the/p + poly tunnel junction, the doping concentration of n + poly is 2-6E +20cm-3The doping concentration range of p + poly is 1-4E +20cm-3。
11. A back contact solar cell having multiple tunnel junction structures, comprising an N-type crystalline silicon substrate, characterized in that:
the front surface of the N-type crystal silicon substrate comprises a lightly doped N + surface field and a passivated antireflection film;
the back surface of the N-type crystal silicon substrate comprises a P-type emitter region, an N-type back surface field region and a groove structure; the P-type emitter region is located in the groove structure, and the N-type back surface field region is located above the groove structure;
the N-type back surface field region sequentially comprises tunneling SiO from inside to outsideXLayer, n + poly layer, oxide layer, n + poly layer, tunneling SiOXA layer, and a p + poly layer; wherein the content of the first and second substances,
the SiOXThe layer and the N + poly layer form c-Si/SiO in the N-type back surface field areaXa/N + poly tunnel junction is formed in the N-type back surface field region by the Oxide layer and the N + poly layer, and a tunnel junction of N + poly/Oxide/N + poly is formed in the N-type back surface field region by tunneling SiOXThe layer and the p + poly layer form N + poly/SiO in the N-type back surface field regionXA/p + poly tunnel junction;
the P-type emitter region sequentially comprises a tunneling SiOx layer and a P + poly layer from inside to outside; the SiOXThe layer and the P + poly layer form c-Si/SiO in the P-type emitter regionXA/p + poly tunnel junction;
the P-type emitter region is provided with a P-type metal electrode, and the N-type back surface field region is provided with an N-type metal electrode.
12. The back contact solar cell of claim 11, wherein the width of the P-type emitter region is 0.9-1.8 mm, and the width of the N-type back surface field region is 0.6-1.4 mm.
13. The back contact solar cell of claim 11, wherein both the front surface and the back surface of the N-type crystalline silicon substrate are provided with a laminated dielectric film; wherein the content of the first and second substances,
the front surface of the N-type crystal silicon substrate is provided with SiO2/SiNXLaminated passivated antireflection film, SiO2The thickness of the layer is 3-15 nm, SiNXThe thickness of the layer is 60-80 nm;
the back surface of the N-type crystal silicon substrate is provided with SiOX、SiNXOr Al2O3Any two of the above layers are used for passivating the antireflection film; or the back surface of the N-type crystal silicon substrate is provided with SiOX、SiNXAnd Al2O3Three stacks passivate the antireflection film.
CN201911186619.5A 2019-11-28 2019-11-28 Back contact solar cell with various tunnel junction structures and preparation method thereof Pending CN110838536A (en)

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