CN112701174A - Back emitter passivation contact battery and preparation method, assembly and system thereof - Google Patents
Back emitter passivation contact battery and preparation method, assembly and system thereof Download PDFInfo
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
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Abstract
The invention relates to a back emitter passivated contact cell and a preparation method, a component and a system thereof. Wherein the structure of the battery is as follows: the front surface of the silicon substrate is sequentially provided with a local heavily doped layer, a passivation layer and a front surface metal grid line from inside to outside, wherein the front surface metal grid line is printed on the local heavily doped layer, the local heavily doped layer is positioned in a metal contact area on the front surface of the battery and is consistent with the doping type of the silicon substrate, and the nonmetal contact area on the front surface of the battery is not doped or is only partially doped; the back of the silicon substrate is sequentially provided with a doped polycrystalline silicon layer, a passivation layer and a back metal grid line from inside to outside, and the doping types of the doped polycrystalline silicon layer and the silicon substrate are opposite. The invention can greatly reduce the recombination rate of the front side of the battery under the same passivation condition, has better passivation effect, and simultaneously can solve the problem of rapid reduction of the filling factor caused by difficult transmission of majority carriers due to over-high sheet resistance of the front side.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a back emitter passivation contact cell and a preparation method, a component and a system thereof.
Background
In the field of solar cell technology, surface recombination in solar cells causes loss of photogenerated carriers, resulting in a decrease in the photoelectric conversion efficiency of the solar cell. In the solar cell, the recombination is divided into three types, namely radiation recombination, auger recombination and SRH recombination, the surface recombination of the solar cell mainly comprises auger recombination and SRH recombination, and if the surface recombination is to be reduced, the auger recombination and the SRH recombination are to be reduced. According to Shockley-Read-Hall theory, the surface recombination rate formula is US ≡ S · Δ ns, where Δ ns is the excess carrier concentration at the surface, so there are two different techniques to reduce the recombination rate at the surface of the solar cell.
First, surface state characteristics are optimized, and surface state density is reduced by depositing or growing a suitable passivation film. For example, patent documents CN201010141267.4 and CN201510143161.0 disclose back-emitter (also called back junction, which means PN junction is located on the back surface of the cell) contact cells, and improve photoelectric conversion efficiency by providing a passivation layer on the back surface of a silicon wafer (also called silicon substrate or semiconductor substrate).
The second is to reduce the surface concentration of electrons and holes to achieve a reduced surface recombination rate. Experiments and simulations have found that the higher the sheet resistance of the doped layer, the lower the surface doping concentration, and the lower the surface recombination under the same passivation conditions, so it can be concluded that the surface recombination should be the lowest when the sheet resistance of the doped layer tends to infinity, according to this trend. However, when the sheet resistance of the doped layer tends to be infinite, for a general positive junction (PN junction is located on the front surface of the solar cell), the lateral transport of majority carriers on the front surface of the solar cell is seriously affected, so that the fill factor of the solar cell is seriously affected, and the photoelectric conversion efficiency of the solar cell is sharply reduced.
Patent document CN201910507835.9 discloses a positive junction cell, in which a local heavily doped P + + region is formed in a gate line pattern region (also called a metal contact region) on the back surface of a silicon substrate, and a lightly doped P + region is formed in a non-gate line pattern region (also called a non-metal contact region), so as to reduce the surface recombination loss, improve the fill factor, and achieve the purpose of improving the photoelectric conversion efficiency.
Therefore, in order to solve the above problems, a new solar cell structure and a method for manufacturing the same are needed to be developed.
Disclosure of Invention
The invention aims to reduce the recombination rate of the surface of the cell, solve the problem of reduction of the filling factor caused by over-high sheet resistance and realize the improvement of the photoelectric conversion efficiency of the solar cell.
Therefore, the non-front field back emitter passivated contact battery is provided, and the structure is as follows:
the front surface of a silicon substrate in the cell is sequentially provided with a local heavily doped layer, a passivation layer and a front surface metal grid line from inside to outside, the local heavily doped layer is positioned in a metal contact area on the front surface of the cell and is consistent with the doping type of a silicon substrate, the nonmetal contact area on the front surface of the cell is not doped or is only partially doped, and the front surface metal grid line is printed on the local heavily doped layer;
the back surface of the silicon substrate is sequentially provided with a doped polycrystalline silicon layer, a passivation layer and a back metal grid line from inside to outside, and the doping types of the doped polycrystalline silicon layer and the silicon substrate are opposite.
Furthermore, a tunneling oxide layer is arranged between the back surface of the silicon substrate and the doped polycrystalline silicon layer.
Further, the passivation layer on the front surface and/or the back surface of the silicon substrate has the antireflection effect.
Further, the passivation layer is a passivation antireflection film deposited on the surface of the silicon substrate.
Further, the silicon substrate is an N-type silicon substrate, the local heavily doped layer is an N + + heavily doped region on the front surface of the silicon substrate, and the doped polycrystalline silicon layer is a boron-doped amorphous silicon layer; or
The silicon substrate is a P-type silicon substrate, the local heavily doped layer is a P + + heavily doped region on the front surface of the silicon substrate, and the doped polycrystalline silicon layer is a phosphorus-doped amorphous silicon layer.
Also provided is a method for preparing a back emitter passivated contact cell, comprising the steps of:
s1, determining a silicon substrate of a battery;
s2, forming a local heavily doped region consistent with the doping type of the silicon substrate in the metal contact region on the front surface of the silicon substrate, and performing no or only partial doping in the non-metal contact region on the front surface of the silicon substrate;
s3, forming a doped amorphous silicon layer with the doping type opposite to that of the silicon substrate on the back of the silicon substrate;
and S4, carrying out post-treatment on the silicon substrate to complete the preparation of the battery.
Further, in step S2, the method for forming the locally heavily doped region includes one of a1 to A3:
A1. forming an opening by adopting a silicon dioxide mask and laser grooving or etching slurry, and injecting or diffusing phosphorus/boron ions at the opening;
A2. firstly preparing a passivation anti-reflection film on the front surface, and then slotting and printing an aluminum grid line by using laser or etching slurry;
A3. and the local injection of phosphorus/boron ions is realized by adopting a graphite mask plate.
Further, the preparation method of the doped amorphous silicon layer is one of B1-B3:
B1. depositing an amorphous silicon layer by adopting a PVD method and doping phosphorus/boron ions in situ at the same time;
B2. depositing an amorphous silicon layer by adopting a CVD method, and then doping the amorphous silicon layer, wherein the doping mode comprises ion implantation and high-temperature diffusion;
B3. and depositing an amorphous silicon layer by adopting a PECVD method, and then doping the amorphous silicon layer.
Further, in step S3, a tunneling oxide layer is formed between the back surface of the silicon substrate and the doped amorphous silicon layer.
Further, the step S4 further includes:
s41, depositing a passivation antireflection film on the front surface and/or the back surface of the silicon substrate;
and S42, printing metal grid lines on the front side and the back side of the silicon substrate, wherein the metal grid lines on the front side are printed on the local heavily doped region.
The back emitter passivation contact battery assembly comprises a front layer material, a packaging material, a back emitter passivation contact battery, a packaging material and a back layer material which are sequentially arranged from top to bottom, wherein the back emitter passivation contact battery is the back emitter passivation contact battery.
Also provided is a back emitter passivated contact cell system comprising at least one back emitter passivated contact cell assembly in series, said back emitter passivated contact cell assembly being the back emitter passivated contact cell assembly described above.
The implementation of the invention comprises the following technical effects:
(1) by adopting a front-field-free structure, the doping concentration of the front-side non-metal contact area is lower, namely the doping concentration of the silicon substrate, so that the recombination rate of the front side can be greatly reduced under the same passivation condition, the passivation effect is better, and the photoelectric conversion efficiency of the solar cell can be theoretically greatly improved;
(2) the back emitter structure is adopted, and the local heavily doped layer with the doping type consistent with that of the silicon substrate is arranged on the front surface of the cell in a matching manner, so that the influence on the transverse transmission of majority carriers is avoided, and the problem of rapid reduction of filling factors caused by difficulty in transmission of majority carriers due to over-high sheet resistance on the front surface is solved.
Drawings
Fig. 1-1 is a schematic view of example 1 of the present invention after completion of step 1.
Fig. 1-2 are schematic diagrams of preparation of a front locally heavily doped N + + region in example 1 of the present invention.
Fig. 1-3 are schematic diagrams of preparation of a front locally heavily doped N + + region in example 1 of the present invention.
Fig. 1-4 are schematic diagrams of the preparation of the back side passivated contact structure of example 1 of the present invention.
Fig. 1 to 5 are schematic diagrams of front and back passivation antireflection films prepared in example 1 of the present invention.
FIGS. 1-6 are schematic diagrams of the metallization completion of example 1 of the present invention.
Fig. 2-1 is a schematic diagram of example 2 of the present invention after completion of step 1.
Fig. 2-2 is a schematic diagram of a structure for preparing a back side passivation contact in embodiment 2 of the present invention.
Fig. 2-3 are schematic diagrams of front and back passivation antireflection films prepared in example 2 of the present invention.
Fig. 2-4 are schematic diagrams of preparation of a front locally P + + heavily doped region in embodiment 2 of the present invention.
Fig. 2 to 5 are schematic diagrams of preparing a back metal gate line in embodiment 2 of the present invention.
FIG. 3-1 is a schematic diagram of example 3 of the present invention after completion of step 1.
Fig. 3-2 is a schematic diagram of preparing a front locally P + + heavily doped region in embodiment 3 of the present invention.
Fig. 3-3 are schematic views of the structure for preparing a back side passivation contact in embodiment 3 of the present invention.
Fig. 3-4 are schematic diagrams of front and back passivation antireflection films prepared in example 3 of the present invention.
FIGS. 3-5 are schematic diagrams of the metallization completion of example 3 of the present invention.
Reference numerals: 1-1 parts of an N-type silicon substrate, 1-2 parts of a mask, 1-3 parts of an opening, 1-4 parts of phosphorosilicate glass, 1-5 parts of a heavily doped phosphorus doped region, 1-6 parts of a silicon dioxide tunneling oxide layer, 1-7 parts of a boron doped polycrystalline silicon layer, 1-8 parts of an aluminum oxide passivation film, 1-9 parts of a silicon nitride film, 1-10 parts of a front side auxiliary grid and 1-11 parts of a back side auxiliary grid line; 2-1 parts of a P-type silicon substrate, 2-2 parts of a tunneling oxide layer, 2-3 parts of a doped polycrystalline silicon layer, 2-4 parts of a polycrystalline silicon layer, 2-5 parts of an aluminum oxide passivation film, 2-6 parts of a silicon nitride film and 2-7 parts of a heavily doped P + + region; 3-1 parts of a P-type silicon substrate, 3-2 parts of a P + + region, 3-3 parts of a silicon dioxide tunneling oxide layer, 3-4 parts of a phosphorus-doped polycrystalline silicon layer, 3-5 parts of an aluminum oxide passivation film, 3-6 parts of a silicon nitride film, 3-7 parts of a front side auxiliary grid and 3-8 parts of a back side auxiliary grid line.
Detailed Description
The back emitter passivation contact cell without the front field has the structure that: the front surface of the silicon substrate is sequentially provided with a local heavily doped layer, a passivation layer and a front surface metal grid line from inside to outside, wherein the front surface metal grid line is printed on the local heavily doped layer, the local heavily doped layer is positioned in a metal contact area on the front surface of the battery and is consistent with the doping type of the silicon substrate, and the nonmetal contact area on the front surface of the battery is not doped, so that a front field-free structure can be formed, the doping concentration of the nonmetal contact area on the front surface of the battery is lower, namely the doping concentration of the silicon substrate, therefore, under the same passivation condition, the recombination rate of the front surface of the battery can be greatly reduced, the passivation effect is better, and the photoelectric conversion efficiency of the solar; and for the back side of the silicon substrate, a doped polycrystalline silicon layer, a passivation layer and a back metal grid line are sequentially arranged from inside to outside, wherein the doping type of the doped polycrystalline silicon layer is opposite to that of the silicon substrate, so that a PN junction is positioned on the back side of the battery to form a back emitter structure, the back emitter structure is matched with a local heavily doped layer arranged on the front side of the battery, the influence on the transverse transmission of majority carriers can be avoided, and the problem of rapid reduction of filling factors caused by difficulty in transmission of majority carriers due to overhigh square resistance on the front side is solved.
Specifically, in the front-field-free back emitter passivation contact cell, when the silicon substrate is an N-type silicon substrate, the local heavily doped layer is an N + + heavily doped region on the front surface of the silicon substrate, and the doped polycrystalline silicon layer is a boron-doped amorphous silicon layer; when the silicon substrate is a P-type silicon substrate, the local heavily doped layer becomes a P + + heavily doped region on the front surface of the silicon substrate and keeps consistent with the doping type of the silicon substrate, and the doped polycrystalline silicon layer becomes a phosphorus-doped amorphous silicon layer and keeps opposite to the doping type of the silicon substrate.
Further, a tunneling oxide layer is disposed between the back surface of the silicon substrate and the doped polysilicon layer to suppress short channel effects.
Further, in order to achieve a better passivation effect, passivation layers on the front and back surfaces of the substrate can be provided with a reflection reducing effect, and specifically, the passivation layers on the front and back surfaces of the silicon substrate can be passivation reflection reducing films, wherein the passivation reflection reducing films are an aluminum oxide passivation film and a silicon nitride film which are sequentially arranged from inside to outside.
It should be noted that, in the above-mentioned battery, the non-metal contact region on the front surface of the battery is not doped, so that a front field is not present, and an optimal effect of reducing the doping concentration is achieved, but the invention is not achieved by completely not doping, and the non-metal contact region is partially doped, so that an effect of reducing the doping concentration is also achieved, and the efficiency is improved.
In this embodiment, a method for manufacturing the front field-free back emitter passivated contact cell is further provided, which includes the following steps:
s1, selecting a silicon substrate, and performing texturing treatment on the silicon substrate to form a textured structure;
s2, forming a local heavily doped region consistent with the doping type of the silicon substrate in a metal contact region on the front surface of the silicon substrate, wherein the pattern of the heavily doped region is consistent with the pattern of the front surface metallization, and other regions are not doped;
s3, forming a passivation contact structure with the doping type opposite to that of the silicon substrate on the back of the silicon substrate;
and S4, carrying out post-treatment on the silicon substrate to finish the preparation of the solar cell.
Wherein the content of the first and second substances,
step S1, the method for texturing the silicon substrate comprises wet texturing and dry texturing;
in step S2, the method for forming the front-side local heavily doped region includes implanting phosphorus/boron locally by using a graphite mask, or forming an opening by using a silicon dioxide mask and a laser grooving or etching slurry to achieve local phosphorus/boron ion implantation or local phosphorus/boron diffusion, or preparing a passivation anti-reflection film on the front side and then performing groove printing on an aluminum gate line by using laser or etching slurry;
step S3, etching the back surface of the silicon substrate to form a relatively smooth surface, preparing a tunneling oxide layer on the relatively smooth surface, depositing an amorphous silicon layer on the tunneling oxide layer, doping the amorphous silicon layer, and activating by annealing; the tunneling oxide layer comprises silicon oxide, silicon nitride, titanium oxide, hafnium oxide or aluminum oxide, the thickness of the tunneling oxide layer is 1-10 nm, and the preparation method comprises a nitric acid oxidation method, an ozone method, a thermal oxidation method or an atomic layer deposition method; depositing the amorphous silicon layer comprises depositing the amorphous silicon layer by adopting a CVD method, and then doping the amorphous silicon layer, wherein the doping mode comprises ion implantation and high-temperature diffusion, or depositing the amorphous silicon layer by adopting a PVD method and simultaneously doping phosphorus/boron ions in situ, or depositing the amorphous silicon layer by adopting a PECVD method, and then doping the amorphous silicon layer; in the method, the thickness of the amorphous silicon layer is 30-300 nm, the annealing temperature is 880-1000 ℃, and the annealing time is 10-50 min;
step S4 includes substeps S41 and S42, in which step S41 is performed to deposit a passivation anti-reflective film on the front and back surfaces of the silicon substrate, the passivation anti-reflective film includes SiNx, SiOx, or AlOx, and the passivation anti-reflective film is prepared by a PECVD method or an atomic layer deposition method, where the PECVD method includes tubular PECVD and plate PECVD, and the passivation anti-reflective film has a thickness of 70nm to 100 nm; step S42 is to print metal gate lines on the front and back sides of the silicon substrate, wherein the front metal gate lines have a pattern corresponding to the front locally heavily doped region.
And drying and sintering after printing to finish the preparation of the passive contact battery without the front field and the back emitter.
The embodiment also provides a front field-free back emitter passivation contact battery assembly which comprises a front layer material, a packaging material, a front field-free back emitter passivation contact battery, a packaging material and a back layer material which are connected from top to bottom, wherein the front field-free back emitter passivation contact battery is the front field-free back emitter passivation contact battery. The structure and the working principle of the front field free back emitter passivated contact battery component of the embodiment use the technology known in the art, and the component improvement provided by the invention only relates to the front field free back emitter passivated contact battery, and the other parts are not modified. Therefore, the description only details the front field-free back emitter passivation contact battery and the preparation method thereof, and other parts and working principles of the front field-free back emitter passivation contact battery assembly are not repeated herein. Based on the content described in the present specification, a person skilled in the art can implement the front field-free back emitter passivated contact cell assembly of the present invention.
The embodiment also provides a front field free back emitter passivated contact battery system, which comprises one or more front field free back emitter passivated contact battery assemblies connected in series, wherein the front field free back emitter passivated contact battery assembly is the front field free back emitter passivated contact battery assembly. The structure and the working principle of the no-front-field back emitter passivated contact battery system of the embodiment use the technology known in the field, and the improvement of the no-front-field back emitter passivated contact battery system provided by the invention only relates to the no-front-field back emitter passivated contact battery, and other parts are not modified. Therefore, the description only details the contact battery without front field back emitter passivation and the preparation method thereof, and other parts and working principles of the contact battery system without front field back emitter passivation are not described herein again. The person skilled in the art can realize the field-free back emitter passivation contact battery system of the invention on the basis of the content described in the specification.
The present invention will be described in detail with reference to specific examples. The present invention is not limited to the above-described embodiments, and those skilled in the art can make modifications to the embodiments without any inventive contribution as required after reading the present specification, but only protected within the scope of the appended claims.
Example 1
Selecting an N-type silicon substrate 1-1, and performing texturing treatment on the N-type silicon substrate 1-1 to form a surface textured structure, as shown in figure 1-1.
A layer of mask 1-2 is deposited on the front surface of a silicon substrate in a PECVD mode, the mask is made of silicon dioxide, a laser is used for opening a film, the laser can be a nanosecond laser or a picosecond laser, the power of the laser is 10-35W, an opening 1-3 is formed in the mask, the width of the opening is 30-100 mu m, and the opening pattern is consistent with the front surface metallization pattern, as shown in the figure 1-2.
Preparing an N + + heavily doped region on the front surface of a silicon substrate by adopting a phosphorus diffusion mode, specifically, depositing phosphorosilicate glass 1-4 on a mask and an opening, wherein the region with the mask is not doped, forming a heavily doped phosphorus doped region 1-5 at the opening 1-3 of the mask, and simultaneously forming the phosphorosilicate glass 1-4 on the back surface of the silicon substrate, wherein the phosphorus diffusion temperature is 830-900 ℃, and the diffusion time is 40-180 min, as shown in figure 1-3.
And etching the silicon substrate 1-1 to remove the phosphorosilicate glass 1-4 on the back side, and simultaneously removing the phosphorosilicate glass 1-4 and the mask 1-2 on the front side to form a gentle back side structure. On the gentle back structure, a layer of silicon dioxide tunneling oxide layer 1-6 is prepared by a nitric acid oxidation method, and the specific method is that a nitric acid solution with the mass fraction of 60-68% is adopted to react for 4-10 min at the reaction temperature of 80-100 ℃, so that the tunneling oxide layer 1-6 is prepared, and the thickness is 1-10 nm. Depositing a boron-doped amorphous silicon layer on the tunneling oxide layer by adopting a PVD method, wherein the thickness of the amorphous silicon layer is 30-300 nm, and then performing tubular high-temperature annealing to activate the boron-doped amorphous silicon layer to form a boron-doped polycrystalline silicon layer 1-7, wherein the annealing temperature is 850-950 ℃, as shown in figures 1-4.
Depositing an aluminum oxide passivation film 1-8 on the front surface and the back surface of the silicon substrate by adopting an atomic layer deposition method, and depositing a silicon nitride film 1-9 on the aluminum oxide passivation film by adopting a plate-type PECVD method, wherein the thickness of the silicon nitride film 1-9 is 60-95 nm, as shown in a figure 1-5.
Printing metal silver grid lines on the front surface of a silicon substrate, wherein the silver grid lines in a local N + + heavily doped region are front side auxiliary grid lines 1-10, the line widths of the front side auxiliary grid lines are 30-90 um and are arranged in parallel, the back surface of the silicon substrate is printed with metal silver aluminum paste grid lines, the widths of the back side auxiliary grid lines 1-11 are 45-90 um and are arranged in parallel, drying and sintering are carried out after printing is finished, and thus the preparation of the front field-free back emitter passivation contact double-sided battery is finished, as shown in figures 1-6.
Example 2
Selecting a P-type silicon substrate 2-1, and performing texturing treatment on the P-type silicon substrate 2-1 to form a surface textured structure, as shown in figure 2-1.
And selecting any surface of the silicon substrate as a back surface to be etched to form a gentle surface, and preparing a passivation contact structure on the gentle back surface by adopting an LPCVD method. Specifically, a tunneling oxide layer 2-2 is deposited on the back side, the tunneling oxide layer is 2nm thick, then an intrinsic amorphous silicon layer is deposited on the tunneling oxide layer, the intrinsic amorphous silicon layer is 100nm thick, then the intrinsic amorphous silicon layer is doped in a phosphorus diffusion mode, so that the intrinsic amorphous silicon layer is crystallized to form a doped polycrystalline silicon layer 2-3, and meanwhile, a doped polycrystalline silicon layer 2-4 is formed on the front side of a silicon substrate and is plated in a winding mode, as shown in fig. 2-2.
Cleaning a silicon substrate, removing oxide layers on the front side and the back side by using a hydrofluoric acid solution with the volume ratio concentration of 1% -5%, placing a silicon wafer with the oxide layers removed in a mixed solution of 0.05% -1% by mass of alkali and 2% -10% by volume of a single crystal additive to remove a polysilicon layer on the front side of the silicon wafer for 2-4 times of winding plating, then depositing an aluminum oxide passivation film 2-5 on the front side and the back side of the silicon substrate by using an atomic layer deposition method, depositing a silicon nitride film 2-6 on the aluminum oxide passivation film by using a plate-type PECVD method, wherein the thickness of the silicon nitride film 2-6 is 60-95 nm, as shown in a graph 2-3.
On the front surface of a silicon substrate, a film is opened by adopting laser, the laser can be a nanosecond laser or a picosecond laser, the power of the laser is 10-35W, an opening is formed on a front surface passivation antireflection film, the width of the opening is 30-50 um, the opening pattern is consistent with a front surface metallization pattern, a metal aluminum grid line is printed on the opening to form a heavily doped P + + region 2-7, and the metal aluminum grid line is a front surface metal contact grid line, as shown in fig. 2-4.
And printing metal silver grid lines on the back of the silicon substrate, wherein the line width of the back auxiliary grid lines is 30-90 um, the back auxiliary grid lines are arranged in parallel, drying and sintering are carried out after printing is finished, and thus the preparation of the front field-free back emitter passivation contact double-sided battery is finished, as shown in fig. 2-5.
Example 3
Selecting a P-type silicon substrate 3-1, and performing texturing treatment on the P-type silicon substrate 3-1 to form a surface textured structure, as shown in figure 3-1.
Boron is locally implanted into the front surface of the silicon substrate by adopting graphite mask plate ions, a locally heavily doped P + + region 3-2 is formed in the opening region of the mask, and the opening pattern of the mask plate is consistent with the front surface metallization pattern, as shown in figure 3-2.
Etching the back surface of the silicon substrate 3-1 to form a gentle back surface structure, and preparing a silicon dioxide tunneling oxide layer 3-3 on the gentle back surface structure by adopting a nitric acid oxidation method. Specifically, 60-68% by mass of nitric acid solution is adopted to react for 4-10 min at a reaction temperature of 80-100 ℃, the thickness of the tunneling oxide layer 3-3 is 1-10 nm, an intrinsic amorphous silicon layer is deposited on the tunneling oxide layer by a PECVD method, the thickness of the amorphous silicon layer is 30-300 nm, phosphorus ion implantation is carried out on the intrinsic amorphous silicon layer, then tubular high-temperature annealing is carried out, boron atoms on the front side and phosphorus atoms on the back side are activated, the intrinsic amorphous silicon layer on the back side is crystallized to form a phosphorus-doped polycrystalline silicon layer 3-4, and the annealing temperature is 900-1000 ℃, as shown in figure 3-3.
Depositing an aluminum oxide passivation film 3-5 on the front surface and the back surface of the silicon substrate by adopting an atomic layer deposition method, and depositing a silicon nitride film 3-6 on the aluminum oxide passivation film by adopting a plate-type PECVD method, wherein the thickness of the silicon nitride film 3-6 is 60-95 nm, as shown in a figure 3-4.
Printing metal silver aluminum paste grid lines on the front surface of a silicon substrate, wherein the grid lines of a local P + + heavily doped region are front side auxiliary grids 3-7, the line widths of the front side auxiliary grids are 30-90 um and are arranged in parallel, the metal silver grid lines are printed on the back surface of the silicon substrate, the widths of the back side auxiliary grid lines 3-8 are 45-90 um and are arranged in parallel, drying and sintering are carried out after printing is finished, and thus the preparation of the front field-free back emitter passivation contact double-sided battery is completed, as shown in the figure 3-5.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (10)
1. A back emitter passivated contact cell, characterized by:
the front surface of a silicon substrate in the cell is sequentially provided with a local heavily doped layer, a passivation layer and a front surface metal grid line from inside to outside, the local heavily doped layer is positioned in a metal contact area on the front surface of the cell and is consistent with the doping type of a silicon substrate, the nonmetal contact area on the front surface of the cell is not doped or is only partially doped, and the front surface metal grid line is printed on the local heavily doped layer;
the back surface of the silicon substrate is sequentially provided with a doped polycrystalline silicon layer, a passivation layer and a back metal grid line from inside to outside, and the doping types of the doped polycrystalline silicon layer and the silicon substrate are opposite.
2. The back emitter passivated contact cell of claim 1, wherein: and a tunneling oxide layer is also arranged between the back surface of the silicon substrate and the doped polycrystalline silicon layer.
3. The back emitter passivated contact cell of claim 1, wherein: the passivation layer on the front surface and/or the back surface of the silicon substrate has the antireflection effect.
4. The back emitter passivated contact cell of claim 3, wherein: the passivation layer is a passivation anti-reflection film deposited on the surface of the silicon substrate.
5. The back emitter passivated contact cell according to any of claims 1 to 4, wherein:
the silicon substrate is an N-type silicon substrate, the local heavily doped layer is an N + + heavily doped region on the front surface of the silicon substrate, and the doped polycrystalline silicon layer is a boron-doped amorphous silicon layer; or
The silicon substrate is a P-type silicon substrate, the local heavily doped layer is a P + + heavily doped region on the front surface of the silicon substrate, and the doped polycrystalline silicon layer is a phosphorus-doped amorphous silicon layer.
6. A method for preparing a back emitter passivated contact cell is characterized by comprising the following steps:
s1, determining a silicon substrate of a battery;
s2, forming a local heavily doped region consistent with the doping type of the silicon substrate in the metal contact region on the front surface of the silicon substrate, and performing no or only partial doping in the non-metal contact region on the front surface of the silicon substrate;
s3, forming a doped amorphous silicon layer with the doping type opposite to that of the silicon substrate on the back of the silicon substrate;
and S4, carrying out post-treatment on the silicon substrate to complete the preparation of the battery.
7. The method of claim 6, wherein in step S2, the method of forming the locally heavily doped region comprises one of A1-A3:
A1. forming an opening by adopting a silicon dioxide mask and laser grooving or etching slurry, and injecting or diffusing phosphorus/boron ions at the opening;
A2. firstly preparing a passivation anti-reflection film on the front surface, and then slotting and printing an aluminum grid line by using laser or etching slurry;
A3. and the local injection of phosphorus/boron ions is realized by adopting a graphite mask plate.
8. The method according to claim 6, wherein the doped amorphous silicon layer is prepared by one of the following methods from B1 to B3:
B1. depositing an amorphous silicon layer by adopting a PVD method and doping phosphorus/boron ions in situ at the same time;
B2. depositing an amorphous silicon layer by adopting a CVD method, and then doping the amorphous silicon layer, wherein the doping mode comprises ion implantation and high-temperature diffusion;
B3. and depositing an amorphous silicon layer by adopting a PECVD method, and then doping the amorphous silicon layer.
9. A back emitter passivation contact battery component comprises a front layer material, a packaging material, a back emitter passivation contact battery, a packaging material and a back layer material which are sequentially arranged from top to bottom; the method is characterized in that: the back emitter passivated contact cell is the back emitter passivated contact cell of any one of claims 1-4.
10. A back emitter passivated contact cell system comprising at least one back emitter passivated contact cell assembly in series; the method is characterized in that: the back emitter passivated contact cell assembly is the back emitter passivated contact cell assembly of claim 9.
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