CN116110978B - Solar cell, preparation method thereof and photovoltaic module - Google Patents
Solar cell, preparation method thereof and photovoltaic module Download PDFInfo
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- CN116110978B CN116110978B CN202310155830.0A CN202310155830A CN116110978B CN 116110978 B CN116110978 B CN 116110978B CN 202310155830 A CN202310155830 A CN 202310155830A CN 116110978 B CN116110978 B CN 116110978B
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- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02162—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors
- H01L31/02164—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors for shielding light, e.g. light blocking layers, cold shields for infrared detectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
- H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Chemical & Material Sciences (AREA)
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- Inorganic Chemistry (AREA)
- Photovoltaic Devices (AREA)
Abstract
The application provides a solar cell, a preparation method thereof and a photovoltaic module, wherein the solar cell comprises: a semiconductor substrate; a tunneling layer located at a rear surface of the semiconductor substrate; a doped barrier layer located on at least a portion of a surface of the tunneling layer; the doped conductive layer is positioned on the surface of the doped barrier layer and comprises lightly doped conductive areas and heavily doped conductive areas which are alternately arranged, wherein the lightly doped conductive areas comprise N layers of polysilicon layers which are arranged in a layer-by-layer mode, and a nano silicon oxide layer is arranged between at least two layers of polysilicon layers, and N is more than or equal to 3; the first passivation layer is positioned on the surface of the lightly doped conductive area; and a first electrode in one-to-one correspondence with and in contact with the heavily doped conductive region. The solar cell provided by the application can improve the filling factor efficiency of the cell.
Description
Technical Field
The application relates to the technical field of photovoltaic cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module.
Background
The TOPCon (tunnel oxide passivation contact) battery is called tunneling oxidation passivation contact battery, and is characterized in that the core is an ultrathin tunneling oxide layer and a heavily doped polysilicon layer, the ultrathin oxide layer can enable electrons to tunnel into the polysilicon layer, meanwhile, the transport of holes is blocked, the recombination rate is reduced, and the passivation effect and conversion efficiency of the battery are improved. The heavily doped polysilicon has certain parasitic light absorption, and the thicker polysilicon layer on the back side leads to the reduction of the short-circuit current of the battery.
High temperature sintering of the metallization paste in the screen printing mode commonly used at present results in silver attack of polysilicon to a depth of about 30 nm. However, thicker overall polysilicon layers or highly doped polysilicon result in parasitic light absorption. In addition, the high temperature firing step used in the screen printing metallization process can reduce passivation quality of the phosphorus doped polysilicon structure in the passivation and contact areas, thereby reducing passivation effect, further resulting in reduced fill factor of the solar cell and reduced photoelectric conversion efficiency.
Disclosure of Invention
In view of the above, the application provides a solar cell and a photovoltaic module, which can improve the filling factor of the solar cell and the photoelectric conversion efficiency.
In a first aspect, the present application provides a solar cell comprising:
A semiconductor substrate;
a tunneling layer located at a rear surface of the semiconductor substrate;
A doped barrier layer located on at least a portion of a surface of the tunneling layer;
the doped conductive layer is positioned on the surface of the doped barrier layer and comprises lightly doped conductive areas and heavily doped conductive areas which are alternately arranged, wherein the lightly doped conductive areas comprise N layers of polysilicon layers which are arranged in a layer-by-layer mode, and a nano silicon oxide layer is arranged between at least two layers of polysilicon layers, and N is more than or equal to 3;
The first passivation layer is positioned on the surface of the lightly doped conductive area; and
And the first electrodes are in one-to-one correspondence with and contact with the heavily doped conductive regions.
With reference to the first aspect, in some embodiments, a width of the heavily doped conductive region is greater than or equal to a width of the first electrode.
With reference to the first aspect, in some embodiments, the doped barrier layer is disposed on an entire surface of the tunneling layer remote from the semiconductor substrate.
With reference to the first aspect, in some embodiments, the doped barrier layer is disposed at a portion of a surface of the tunneling layer, and is located between the tunneling layer and the heavily doped conductive region.
With reference to the first aspect, in some embodiments, the lightly doped conductive region has a thickness of H1 nm, 40.ltoreq.H2.ltoreq.100.
In combination with the first aspect, in some embodiments, the heavily doped conductive region has a thickness of H2 nm, 60.ltoreq.H2.ltoreq.130.
With reference to the first aspect, in some embodiments, the thickness of the heavily doped conductive region is H2 nm, and the thickness of the lightly doped conductive region is H1 nm, 20.ltoreq.H2-H1.ltoreq.50.
In combination with the first aspect, in some embodiments, the lightly doped conductive region has a width D1 μm, 200.ltoreq.D1.ltoreq.1500.
With reference to the first aspect, in some embodiments, the heavily doped conductive region has a width D2 μm, 40.ltoreq.D2.ltoreq.90.
With reference to the first aspect, in some embodiments, the lightly doped conductive area includes a first polysilicon layer, a second polysilicon layer, and a third polysilicon layer that are stacked, and a nano silicon oxide layer is disposed between the second polysilicon layer and the third polysilicon layer.
With reference to the first aspect, in some embodiments, a band gap of the third polysilicon layer is greater than a band gap of the nano-silicon oxide layer.
With reference to the first aspect, in some embodiments, the lightly doped conductive region has a doping concentration of 0.8e20 cm -3～4E20 cm-3 and the heavily doped conductive region has a doping concentration of 4E20cm -3～12E20 cm-3.
With reference to the first aspect, in some embodiments, the doped barrier layer includes at least one of a gallium nitride layer, a gallium oxide layer, an aluminum oxide layer, a silicon carbide layer, a silicon nitride layer, and a silicon oxynitride layer; and/or the thickness of the doped barrier layer is 0.4 nm-2.0 nm.
With reference to the first aspect, in some embodiments, the solar cell further includes a second passivation layer and a second electrode located on a front surface of the semiconductor substrate.
With reference to the first aspect, in some embodiments, the thickness of the tunneling layer is 0.8nm to 2.5nm.
With reference to the first aspect, in some embodiments, the first passivation layer includes at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.
With reference to the first aspect, in some embodiments, the second passivation layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
With reference to the first aspect, in some embodiments, the thickness of the first passivation layer and the second passivation layer is 70nm to 120nm.
With reference to the first aspect, in some embodiments, the semiconductor substrate is an N-type monocrystalline silicon substrate, and the doped conductive layer is an N-type doped polysilicon layer or an N-type doped silicon carbide layer.
In a second aspect, the present application also provides a method for preparing a solar cell, the method comprising the steps of:
Performing texturing treatment on the semiconductor substrate;
Forming a tunneling layer on the rear surface of the semiconductor substrate;
depositing a barrier layer on at least part of the surface of the tunneling layer;
forming a mask on the surface of the barrier layer, and removing a part of material from the mask to form exposed first areas which are arranged at intervals;
Forming a first polysilicon region in the first region, wherein the first polysilicon region comprises N polysilicon layers which are arranged in a layer-by-layer manner, and a nano silicon oxide layer is arranged between at least two polysilicon layers, wherein N is more than or equal to 3;
forming a second mask on the surface of the first polysilicon region, depositing polysilicon in an uncovered region of the second mask, and performing in-situ doping treatment to form a second polysilicon region;
performing secondary doping treatment on the first polycrystalline silicon region and the second polycrystalline silicon region to obtain a lightly doped conductive region, a heavily doped conductive region and a doped barrier layer;
forming a first passivation layer on the surface of the lightly doped conductive area; and
And forming a first electrode on the surface of the heavily doped conductive region.
In a third aspect, the present application also provides a photovoltaic module, which includes a plurality of solar cell strings including the solar cells described above.
The technical scheme of the application has at least the following beneficial effects:
According to the application, the efficiency of the battery filling factor can be improved by forming the selective passivation contact structure on the rear surface of the solar battery, the barrier layer is arranged between the tunneling layer and the doped conductive layer, the barrier layer is utilized to prevent excessive phosphorus element in the doped conductive layer from diffusing into the tunneling layer in the crystallization process in the preparation process to damage the tunneling effect, the multi-layer laminated polycrystalline silicon layer is constructed in the lightly doped conductive region, positive charges of the nano silicon oxide layer between the polycrystalline silicon layers have an attraction effect on electron carriers, potential barrier of the doped conductive layer can be improved, infrared reflection loss is reduced, and the open-circuit voltage of the battery is improved, so that the solar battery can improve the efficiency of the filling factor compared with a common TOPCon battery under the synergistic effect of the barrier layer, the selective passivation contact structure and the nano silicon oxide layer, and the solar energy conversion efficiency is improved.
Drawings
For a clearer description of embodiments of the application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application.
Fig. 2 is another schematic structural diagram of a solar cell according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a photovoltaic module according to an embodiment of the present application.
Fig. 4 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a solar cell according to comparative example 3 of the present application.
Detailed Description
For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
The TOPCon (tunnel oxide passivation contact) battery is called tunneling oxidation passivation contact battery, and is characterized in that the core is an ultrathin tunneling oxide layer and a heavily doped polysilicon layer, the ultrathin oxide layer can enable electrons to tunnel into the polysilicon layer, meanwhile, the transport of holes is blocked, the recombination rate is reduced, and the passivation effect and conversion efficiency of the battery are improved. The heavily doped polysilicon has certain parasitic light absorption, and the thicker polysilicon layer on the back side leads to the reduction of the short-circuit current of the battery.
High temperature sintering of the metallization paste in the screen printing mode commonly used at present results in silver attack of polysilicon to a depth of about 30 nm. However, thicker overall polysilicon layers or highly doped polysilicon result in parasitic light absorption. In addition, the high temperature firing step used in the screen printing metallization process can reduce passivation quality of the phosphorus doped polysilicon structure in the passivation and contact areas, thereby reducing passivation effect, further resulting in reduced fill factor of the solar cell and reduced photoelectric conversion efficiency.
Based on this, the present application provides, in a first aspect, a solar cell, as shown in fig. 1, comprising:
A semiconductor substrate 10;
a tunneling layer 20 located at a rear surface of the semiconductor substrate 10;
a doped barrier layer 30 located on at least a portion of the surface of tunneling layer 20;
The doped conductive layer is located on the surface of the doped barrier layer 30, and comprises lightly doped conductive regions 40 and heavily doped conductive regions 50 which are alternately arranged, wherein the lightly doped conductive regions 40 comprise N polysilicon layers 41 which are stacked, and a nano silicon oxide layer 42 is arranged between at least two polysilicon layers 41, and N is more than or equal to 3;
A first passivation layer 60 on the surface of the lightly doped conductive region 40; and
First electrodes 70 in one-to-one correspondence with and in contact with the heavily doped conductive regions 50.
In the scheme, the selective passivation contact structure is formed on the rear surface of the solar cell, so that the cell filling factor efficiency can be improved, a blocking layer is arranged between the tunneling layer and the doped conductive layer, the blocking layer is used for preventing excessive doped elements from diffusing into the tunneling layer to damage the tunneling effect in the preparation process of the doped conductive layer, the multi-layer laminated polycrystalline silicon layer is constructed in the lightly doped conductive region, positive charges of the nano silicon oxide layer between the polycrystalline silicon layers have an attraction effect on electron carriers, potential barriers of the doped conductive layer can be improved, infrared reflection loss is reduced, and the open-circuit voltage of the cell is improved, so that the solar cell can improve the filling factor efficiency compared with an ordinary TOPCon cell under the synergistic effect of the blocking layer, the selective passivation contact structure and the nano silicon oxide layer, and the solar energy conversion efficiency is improved.
The front surface of the semiconductor substrate 10 may refer to a light receiving surface, i.e., a surface (light receiving surface) receiving solar rays, and the rear surface of the semiconductor substrate 10 refers to a surface opposite to the front surface. In some embodiments, the formed solar cell is a single-sided cell, the front surface may refer to a light receiving surface, and the back surface may refer to a backlight surface. In some embodiments, the formed solar cell is a bifacial cell, and both the front and back surfaces may be light receiving surfaces.
As an alternative solution of the present application, the semiconductor substrate 10 is an N-type crystalline silicon substrate (or silicon wafer), and any one or more of high-temperature diffusion, slurry doping or ion implantation may be used to form a P-type doped layer on the front surface of the semiconductor substrate, so as to form a PN junction in the semiconductor substrate 10. In some embodiments, the semiconductor substrate 10 may be one of a monocrystalline silicon substrate, a polycrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate.
In some embodiments, the P-doped layer is a boron doped diffusion layer. The boron-doped diffusion layer is a P-type doped layer (i.e., p+ layer) formed by diffusing boron atoms to a certain depth on the front surface by a diffusion process using a boron source. For example, the boron source may be liquid boron tribromide.
In some embodiments, the front surface of the semiconductor substrate 10 has a textured structure, which may be formed by performing a texturing process on the semiconductor substrate. The manner of the texturing process can be chemical etching, laser etching, mechanical method, plasma etching and the like. The suede structure can be better filled in the suede structure when the electrode is formed by screen printing metal paste, so that more excellent electrode contact is obtained, the series resistance of the battery can be effectively reduced, and the filling factor is improved.
As shown in fig. 1, the tunneling layer 20 is located on the rear surface of the semiconductor substrate 10, and the tunneling layer 20 may be one or more stacked structures of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer. In other embodiments, the tunneling layer 20 may also be a silicon oxynitride layer, a silicon oxycarbide layer, or the like.
The thickness of the tunneling layer 20 is 0.8nm to 2.5nm. Specifically, the thickness of the tunneling layer 20 is 0.8nm, 0.9nm, 1.0nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm, 2.5nm, or the like. The thickness of the tunneling layer 20 refers to the thickness of the tunneling layer relative to the forming surface. The thickness of the tunneling layer 20 is too large to reduce the contact resistance of the tunneling layer. By controlling the thickness of the tunneling layer, a decrease in the fill factor due to contact resistance can be suppressed. When the thickness of the tunneling layer is too large, the tunneling effect of majority carriers is affected, and carriers are difficult to transport through the tunneling layer 20, and the photoelectric conversion efficiency of the battery gradually decreases. When the thickness of the tunneling layer 20 is too small, passivation cannot be performed. Preferably, the tunneling layer 20 is a silicon oxide layer, and the thickness of the tunneling layer 20 is 0.8nm to 1.5nm.
In some embodiments, as shown in fig. 1, a doped barrier layer 30 is disposed on the entire surface of the tunneling layer 20 remote from the semiconductor substrate 10.
In some embodiments, the doped barrier layer 30 is located on at least a portion of the surface of the tunneling layer 20. As shown in fig. 2, the doped blocking layer 30 is disposed on a portion of the surface of the tunneling layer 20 at intervals, and is located between the tunneling layer 20 and the heavily doped conductive region 50. Specifically, the doped barrier layer 30 is disposed in one-to-one correspondence with the heavily doped conductive regions 50 in the doped conductive layer.
In some embodiments, the material of the doped barrier layer 30 is a material with a melting point higher than 1700K. That is, the dielectric constant of the doped barrier layer 30 is higher than that of the tunneling layer made of silicon oxide, the melting point of the dielectric layer is higher than that of the tunneling layer, and the doped barrier layer 30 has a certain fixed interface positive charge density.
Specifically, the doped barrier layer 30 includes at least one of a gallium nitride layer, a gallium oxide layer, an aluminum oxide layer, a silicon carbide layer, and a silicon nitride layer. The arrangement of the doped barrier layer 30 can avoid that excessive N-type doping elements such as phosphorus diffuse into the tunneling layer 20 in the preparation process of the heavily doped conductive region 50 to damage the tunneling effect, i.e. the doping elements in the doped barrier layer 30 are mainly N-type doping elements such as phosphorus diffuse into the barrier layer when the heavily doped conductive region 50 is doped.
The thickness of the doped barrier layer 30 is 0.4nm to 2.0nm. Specifically, the thickness of the doping blocking layer 30 is 0.4nm, 0.5nm, 0.6nm, 0.7nm, 1.0nm, 1.2nm, 1.5nm, 1.8nm, or 2.0nm, etc., but other values within the above range are also possible. The doped barrier layer 30 with a suitable thickness can prevent the heavily doped conductive region 50 from damaging the tunneling effect due to the excessive N-type doping elements such as phosphorus diffusing into the tunneling layer 20 during the preparation process.
In some embodiments, the doped conductive layer is located on a surface of the doped barrier layer 30 remote from the semiconductor substrate 10. The doped conductive layer includes lightly doped conductive regions 40 and heavily doped conductive regions 50 alternately arranged, and the selectively passivated contact structure formed by the lightly doped conductive regions 40 and the heavily doped conductive regions 50 can improve the efficiency of the battery filling factor.
The doped conductive layer has a doping element of the same conductivity type as the semiconductor substrate 10. When the semiconductor substrate 10 is an N-type monocrystalline silicon substrate, the doped conductive layer is an N-type doped polysilicon layer or an N-type doped silicon carbide layer, and the doping element may be an N-type doping element such as phosphorus.
Further, the lightly doped conductive region 40 includes N polysilicon layers 41 stacked on each other, and a nano silicon oxide layer 42 is disposed between at least two polysilicon layers 41, where N is greater than or equal to 3, and N is a natural number.
As shown in fig. 1, the lightly doped conductive region 40 has a doping concentration of 0.8e20 cm -3～4E20cm-3, specifically 0.8E20 cm-3、1.0E20 cm-3、1.2E20 cm-3、1.5E20 cm-3、1.8E20 cm-3、2.0E20 cm-3、2.5E20 cm-3、3.0E20 cm-3, 3.9e20 cm -3, or the like, but may have other values within the above range.
The thickness of the lightly doped conductive area 40 is H1 nm, H1 is more than or equal to 40 and less than or equal to 100; the value of H1 may be specifically 40, 50, 55, 60, 65, 70, 80, 90, 100, or the like, and may be any other value within the above range.
The width of the lightly doped conductive region 40 is D1 μm, and D1 is 200-1500, and the value of D1 may be 200, 300, 500, 600, 700, 800, 900, 1000, 1200 or 1500, or other values within the above range.
In some embodiments, as shown in fig. 1, the lightly doped conductive region 40 includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer stacked, and a nano silicon oxide layer 42 is disposed between the second polysilicon layer and the third polysilicon layer.
The nano silicon oxide layer 42 is made of a wide-gap nc-SiOx H material, the band gap of which is in the range of 1.4-1.8eV, and the hydrogen content of the nano silicon oxide layer is 8% -15%. The positive charges of the nano silicon oxide layer 42 between the polysilicon layers have an attraction effect on electron carriers, so that the potential barrier of the doped conductive layer can be raised, the infrared reflection loss is reduced, and the open-circuit voltage of the battery is raised.
In some embodiments, the third polysilicon layer has a band gap greater than that of the nano-silicon oxide layer, such that short wave light absorption may be increased. Specifically, the band gap of the third polysilicon layer is in the range of 1.8 to 2.2 eV.
In some embodiments, the heavily doped conductive region 50 has a doping concentration of 4E20 cm -3～12E20 cm-3, which may be 4E20 cm-3、5E20 cm-3、6E20 cm-3、7E20 cm-3、8E20cm-3、9E20 cm-3、10E20 cm-3、11E20 cm-3 or 12E20 cm -3, or the like, although other values within the above range are also possible.
As shown in FIG. 1, the heavily doped conductive region 50 has a thickness H2 nm, 60.ltoreq.H2.ltoreq.130; the value of H2 may be specifically 60, 65, 70, 80, 90, 100, 110, 120, 130, or the like, but may be any other value within the above range.
In some embodiments, the thickness of the heavily doped conductive region 50 is greater than the thickness of the lightly doped conductive region 40, which satisfies 20.ltoreq.H2—H2.ltoreq.50, and the heavily doped conductive region is higher than the lightly doped conductive region, and the height difference between the two can reduce the influence of the breakdown effect of the battery in the electrode slurry sintering process, which is beneficial to improving the conversion efficiency of the battery.
The width of the heavily doped conductive region 50 is D2 μm, D2 is 40-90, and the value of D2 may be 40, 50, 55, 60, 65, 70, 80 or 90, or any other value within the above range.
Further, the first electrodes are in one-to-one correspondence and contact connection with the heavily doped conductive regions 50.
In some embodiments, the width of the heavily doped conductive region 50 is greater than or equal to the width of the first electrode 70. By the arrangement, the influence on the lightly doped conductive area during sintering of the metal conductive paste can be avoided during metallization treatment, and the contact resistivity can be effectively reduced.
Further, a first passivation layer 60 is located on the surface of the lightly doped conductive region 40, and the first passivation layer 60 includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
In some embodiments, when the first passivation layer 60 is a stacked silicon nitride layer and silicon oxide layer or a stacked silicon nitride layer and silicon oxynitride layer, the silicon nitride layer is located on the surface of the lightly doped conductive region, and the silicon oxide layer or the silicon oxynitride layer is located on the surface of the silicon nitride layer.
With continued reference to fig. 1, the solar cell 100 further includes a second passivation layer 80 and a second electrode 90 on the front surface of the semiconductor substrate 10.
In some embodiments, the second passivation layer 80 and the second electrode 90 are alternately disposed on the front surface of the semiconductor substrate 10. The second passivation layer 80 includes a stacked structure of at least one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.
In some embodiments, the thickness of the second passivation layer 80 ranges from 10nm to 120nm, specifically, may be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or 120nm, or the like, but may be other values within the above range, which is not limited herein.
In some embodiments, the second passivation layer 80 is a stacked passivation structure of an aluminum oxide layer and a silicon nitride layer. The aluminum oxide layer is disposed on the front surface of the semiconductor substrate 10, and the silicon nitride layer is disposed on the surface of the aluminum oxide layer.
Wherein the second electrode 90 forms an ohmic contact with a P-type doped layer (e.g., boron doped diffusion layer) of the front surface of the semiconductor substrate 10 and the first electrode 70 forms an ohmic contact with the heavily doped conductive region 50. The first electrode 70 and the second electrode 90 may be formed by sintering a metal conductive paste applied on the surfaces of the first passivation layer and the second passivation layer. In some embodiments, the material of the first electrode 70 or the second electrode 90 includes a metallic material such as silver, aluminum, copper, nickel, etc.
In a second aspect, embodiments of the present application provide a photovoltaic module including a plurality of solar cell strings.
As shown in fig. 3, the photovoltaic module includes a first cover plate 1, a first encapsulation adhesive layer 2, a solar cell string 3, a second encapsulation adhesive layer 4, and a second cover plate 5.
The solar cell string 3 includes a plurality of solar cells (such as the solar cells shown in fig. 1), and the solar cells are connected by a conductive tape (not shown). The solar cells may be partially stacked or spliced.
The first cover plate 1, the second cover plate 5 may be a transparent or opaque cover plate, such as a glass cover plate, a plastic cover plate.
The two sides of the first packaging adhesive layer 2 are respectively contacted and attached with the first cover plate 1 and the solar cell string 3, and the two sides of the second packaging adhesive layer 4 are respectively contacted and attached with the second cover plate 5 and the solar cell string 3. The first packaging adhesive layer 2 and the second packaging adhesive layer 4 can be respectively ethylene-vinyl acetate copolymer (EVA) adhesive films, polyethylene octene co-elastomer (POE) adhesive films or polyethylene terephthalate (PET) adhesive films.
The photovoltaic module can also adopt side full-surrounding type packaging, namely the side of the photovoltaic module is completely encapsulated by adopting the packaging adhesive tape, so that the phenomenon of lamination offset of the photovoltaic module in the lamination process is prevented.
Further, the photovoltaic module further comprises a sealing component, and the sealing component is fixedly packaged on part of the edge of the photovoltaic module. The edge sealing component can fixedly encapsulate edges of the photovoltaic module near corners. The edge sealing member may be a high temperature resistant tape. The high-temperature-resistant adhesive tape has excellent high-temperature resistance, can not be decomposed or fall off in the lamination process, and can ensure reliable encapsulation of the photovoltaic module. Wherein, the both ends of high temperature resistant sticky tape are fixed in second apron 5 and first apron 1 respectively. The two ends of the high-temperature-resistant adhesive tape can be respectively adhered to the second cover plate 5 and the first cover plate 1, and the middle part of the high-temperature-resistant adhesive tape can limit the side edges of the photovoltaic module, so that the photovoltaic module is prevented from generating lamination offset in the lamination process.
In a third aspect, the present application further provides a method for preparing a solar cell, for preparing the solar cell, as shown in fig. 4, where the preparation method includes the following steps:
Step S10, performing texturing treatment on the semiconductor substrate;
step S20, forming a tunneling layer on the rear surface of the semiconductor substrate;
Step S30, a barrier layer is deposited and formed on at least part of the surface of the tunneling layer;
Step S40, forming a mask on the surface of the barrier layer, and removing a part of material from the mask to form exposed first areas which are arranged at intervals;
s50, forming a first polycrystalline silicon region in the first region, wherein the first polycrystalline silicon region comprises N layers of polycrystalline silicon layers which are arranged in a layer-by-layer mode, and a nano silicon oxide layer is arranged between at least two layers of polycrystalline silicon layers, and N is more than or equal to 3;
step S60, forming a second mask on the surface of the first polysilicon region, depositing polysilicon in the uncovered region of the second mask, and performing in-situ doping treatment to form a second polysilicon region;
Step S70, carrying out secondary doping treatment on the first polysilicon region and the second polysilicon region to obtain a lightly doped conductive region, a heavily doped conductive region and a doped barrier layer;
step S80, forming a first passivation layer on the surface of the lightly doped conductive area; and
Step S90, forming a first electrode on the surface of the heavily doped conductive region.
The scheme is specifically described as follows:
and step S10, performing texturing treatment on the semiconductor substrate.
The semiconductor substrate may be a crystalline silicon substrate (silicon substrate), for example, one of a polycrystalline silicon substrate, a single crystal silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the specific type of the semiconductor substrate is not limited in the embodiments of the present application. In some embodiments, the semiconductor substrate is an N-type crystalline silicon substrate (or silicon wafer), and the thickness of the semiconductor substrate is 60 μm to 240 μm, specifically 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, 240 μm, or the like, which is not limited herein. The doping element of the semiconductor substrate may be phosphorus, nitrogen, or the like.
It should be noted that the present application is not limited to a specific manner of operation of the texturing. For example, the N-type substrate may be selectively textured by a wet texturing process, and when the N-type semiconductor substrate is an N-type single crystal silicon substrate, the texturing may be performed using an alkaline solution such as a potassium hydroxide solution.
The manner of the texturing process can be chemical etching, laser etching, mechanical method, plasma etching and the like. The suede structure can be better filled in the suede structure when the electrode is formed by screen printing metal paste, so that more excellent electrode contact is obtained, the series resistance of the battery can be effectively reduced, and the filling factor is improved.
Prior to step S20, the method further comprises:
and doping the front surface of the semiconductor substrate after texturing to form a doped layer.
In a specific embodiment, when the semiconductor substrate 10 is an N-type substrate, a P-type doped layer may be formed on the front surface of the semiconductor substrate using any one or more of high temperature diffusion, slurry doping, or ion implantation, so as to form a PN junction in the semiconductor substrate 10.
In some embodiments, the P-doped layer is a boron doped diffusion layer. The boron-doped diffusion layer is a P-type doped layer (i.e., p+ layer) formed by diffusing boron atoms to a certain depth on the front surface by a diffusion process using a boron source. For example, the boron source may be liquid boron tribromide. The microcrystalline silicon phase of the boron diffusion treated substrate is converted to a polycrystalline silicon phase. Borosilicate glass layers (BSG) are typically formed due to the relatively high concentration of boron on the surface of the semiconductor substrate.
And step S20, forming a tunneling layer on the rear surface of the semiconductor substrate.
In some possible embodiments, the tunneling layer 20 may be formed by performing a rear surface etching process on the semiconductor substrate using an ozone oxidation process, a high temperature thermal oxidation process, a nitric acid oxidation process, a chemical vapor deposition process, or a low pressure chemical vapor deposition process.
In some embodiments, the tunneling layer 20 is deposited on the back surface of the semiconductor substrate using a temperature swing process as well as chemical vapor deposition. In the deposition process, the heating rate is controlled to be 0.5-3 ℃ per minute, the deposition temperature is 560-620 ℃ and the deposition time is 3-10 min.
Specifically, in the deposition process, the deposition temperature may be 560 ℃, 570 ℃, 580 ℃, 590 ℃, 600 ℃, 610 ℃, 615 ℃, 620 ℃ or the like, the deposition time may be 3min, 4min, 5min, 6min, 7min, 8min, 9min, 10min or the like, and the heating rate may be 0.5 ℃/min, 0.8 ℃/min, 1.0 ℃/min, 1.2 ℃/min, 1.5 ℃/min, 2.0 ℃/min, 2.5 ℃/min, 3 ℃/min or the like, although other values within the above range are also possible, and the present invention is not limited thereto.
Preferably, the tunneling layer 20 is formed on the rear surface of the semiconductor substrate by low-pressure chemical vapor deposition, so that the influence of too high local doping concentration of the thinner tunneling layer 20 in the subsequent high-temperature doping treatment can be reduced, the fluctuation of open-circuit voltage is reduced, and the tunneling layer 20 is formed by temperature-changing technology and low-pressure chemical vapor deposition.
The tunneling layer 20 may be one or more of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, a hafnium oxide layer. In other embodiments, the tunneling layer 20 may also be a silicon oxynitride layer, a silicon oxycarbide layer, or the like. The thickness of the tunneling layer 20 is 0.8nm to 2.5nm.
And step S30, depositing a barrier layer on at least part of the surface of the tunneling layer.
Specifically, a barrier layer is deposited on the surface of the tunneling layer 20, and the material of the barrier layer is a material with a melting point higher than 1700K. Specifically, the barrier layer comprises at least one of a gallium nitride layer, a gallium oxide layer, an aluminum oxide layer, a silicon carbide layer, a silicon nitride layer and a silicon oxynitride layer. The provision of the barrier layer can prevent the heavily doped conductive region 50 from damaging the tunneling effect by diffusing excessive N-type doping elements such as phosphorus into the tunneling layer 20 during the preparation process. In this case, no or only a very small amount of doping element is present in the barrier layer.
In this embodiment, when the barrier layer is disposed on the entire surface of the tunneling layer 20 away from the semiconductor substrate 10, the deposition process may be directly performed on the entire surface of the tunneling layer.
When the material of the barrier layer is silicon carbide, the mixed gas of carbon dioxide and silane can be used as a gas source for plasma enhanced chemical vapor deposition, and the deposition temperature is controlled to be 450-600 ℃.
When the material of the barrier layer is silicon nitride, the mixed gas of ammonia and silane can be used as a gas source for plasma enhanced chemical vapor deposition, and the deposition temperature is controlled to be 450-600 ℃.
When the material of the barrier layer is silicon oxynitride, the mixed gas of ammonia, nitrogen dioxide and silane can be used as a gas source for plasma enhanced chemical vapor deposition, and the deposition temperature is controlled to be 450-600 ℃.
When the material of the blocking layer is alumina, the alumina can be used as a deposition source for atomic layer deposition, and the deposition temperature is controlled to be 200-350 ℃.
When the barrier layer is made of gallium oxide or gallium nitride, the barrier layer can be deposited by a metal organic chemical vapor deposition process (MOVPE) or a hydride vapor phase epitaxy process (HVPE).
And S40, forming a mask on the surface of the barrier layer, and removing a part of material from the mask to form exposed first areas which are arranged at intervals.
And S50, forming a first polycrystalline silicon region in the first region, wherein the first polycrystalline silicon region comprises N layers of polycrystalline silicon layers which are arranged in a layer-by-layer mode, and a nano silicon oxide layer is arranged between at least two layers of polycrystalline silicon layers, and N is more than or equal to 3.
In some embodiments, the multi-layered polysilicon layer is deposited in the first region of the barrier layer surface using any one of physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition. The chemical vapor deposition method may be a low pressure chemical vapor deposition method or an atmospheric pressure chemical vapor deposition method.
In some embodiments, a first polysilicon layer and a second polysilicon layer are deposited, then a nano silicon oxide layer is deposited on the surface of the second polysilicon layer, and finally a third polysilicon layer is deposited.
The nano silicon oxide layer 42 is made of a wide-gap nc-SiOx H material, the band gap of which is in the range of 1.4-1.8eV, and the hydrogen content of the nano silicon oxide layer is 8% -15%. The positive charges of the nano silicon oxide layer 42 between the polysilicon layers have an attraction effect on electron carriers, so that the potential barrier of the doped conductive layer can be raised, the infrared reflection loss is reduced, and the open-circuit voltage of the battery is raised.
In some embodiments, the third polysilicon layer has a band gap greater than that of the nano-silicon oxide layer, such that short wave light absorption may be increased. Specifically, the band gap of the third polysilicon layer is in the range of 1.8 to 2.2 eV.
And step S60, forming a second mask on the surface of the first polysilicon region, depositing and forming polysilicon in the uncovered region of the second mask, and performing in-situ doping treatment to form a second polysilicon region.
In some embodiments, the polysilicon layer is deposited in the area of the barrier layer surface not covered by the second mask using any one of physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition.
In particular embodiments, the deposition of the tunneling layer and the polysilicon layer and the in-situ doping of the polysilicon layer are all formed in a low pressure chemical vapor deposition apparatus.
And step S70, performing secondary doping treatment on the first polysilicon region and the second polysilicon region to obtain a lightly doped conductive region, a heavily doped conductive region and a doped barrier layer.
It will be appreciated that the first polysilicon region is doped to form a lightly doped conductive region, and the second polysilicon region is secondarily doped to form a heavily doped conductive region, and the heavily doped conductive region and a portion of the doping element of the lightly doped conductive region diffuse into the barrier layer to form a doped barrier layer.
After step S70, and before step S80, the method further includes:
the secondary doping is followed by a high temperature annealing treatment and a cleaning treatment.
The specific operation modes of the high-temperature annealing treatment and the cleaning treatment are not limited in the embodiment of the application. Illustratively, the high temperature annealing treatment is performed on the deposited polysilicon layer to enable better crystallization of the polysilicon layer, and the annealing temperature can range from 700 ℃ to 1000 ℃.
And (3) forming a doped polysilicon layer by diffusing pentavalent phosphorus atoms through high-temperature annealing treatment, wherein after the annealing treatment, the silicon phase of the crystalline silicon is converted into the polysilicon phase, and phosphorus is deposited on the surface of the semiconductor substrate to form phosphosilicate glass (PSG).
The cleaning process is to remove a phosphosilicate glass layer (PSG) formed during the doping process. It will be appreciated that during phosphorus diffusion, due to the higher concentration of phosphorus on the surface of the semiconductor substrate, a phosphosilicate glass (PSG) layer is typically formed, which has a metal gettering effect and affects the normal operation of the solar cell, requiring removal.
The phosphosilicate glass layer can be removed by acid washing. After pickling, water washing is needed, the water washing time is 10-20 s, and the water washing temperature can be 15-25 ℃; of course, the semiconductor substrate may also be subjected to a baking treatment after the washing with water.
And S80, forming a first passivation layer on the surface of the lightly doped conductive area.
After step S80, before step S90, the method further includes: a second passivation layer is formed on a front surface of the semiconductor substrate.
In some embodiments, the first passivation layer and the second passivation layer may be deposited using a plasma enhanced chemical vapor deposition method, although other methods, such as an organic chemical vapor deposition method, may also be used. The embodiment of the application is not limited to the specific implementation manners of the first passivation layer and the second passivation layer. The passivation layer can generate good passivation effect on the semiconductor substrate, and is beneficial to improving the conversion efficiency of the battery.
And step S90, forming a first electrode on the surface of the heavily doped conductive region, and forming a second electrode on the front surface of the semiconductor substrate.
In some embodiments, the second electrode forms an ohmic contact with a P-type doped layer (e.g., boron doped diffusion layer) of the front surface of the semiconductor substrate, and the first electrode 70 forms an ohmic contact with the heavily doped conductive region 50. The first electrode 70 and the second electrode 90 may be formed by sintering a metal conductive paste applied on the surfaces of the first passivation layer and the second passivation layer. In some embodiments, the material of the first electrode 70 or the second electrode 90 includes a metallic material such as silver, aluminum, copper, nickel, etc.
As shown in fig. 2, in the solar cell to be fabricated, the doped barrier layers 30 are disposed on a part of the surface of the tunneling layer 20 at intervals, and the doped barrier layers 30 are disposed in one-to-one correspondence with the heavily doped conductive regions 50 in the doped conductive layers, and the fabrication process is different from the above steps in that:
Step S10, performing texturing treatment on the semiconductor substrate;
step S20, forming a tunneling layer on the rear surface of the semiconductor substrate;
step S30, forming a mask on the surface of the tunneling layer, and removing a part of material from the mask to form exposed first areas which are arranged at intervals;
Step S40, forming a first polysilicon region in the first region, wherein the first polysilicon region comprises N polysilicon layers which are arranged in a layer-by-layer manner, and a nano silicon oxide layer is arranged between at least two polysilicon layers, wherein N is more than or equal to 3;
step S50, forming a second mask on the surface of the first polysilicon region, and depositing a barrier layer on the uncovered region of the second mask;
Step S60, depositing and forming polysilicon on the surface of the barrier layer and simultaneously carrying out in-situ doping treatment to form a second polysilicon region;
Step S70, carrying out secondary doping treatment on the first polysilicon region and the second polysilicon region to obtain a lightly doped conductive region, a heavily doped conductive region and a doped barrier layer;
step S80, forming a first passivation layer on the surface of the lightly doped conductive area; and
Step S90, forming a first electrode on the surface of the heavily doped conductive region.
The preparation process mainly comprises slightly different deposition timings of the barrier layers, and the description is omitted here.
The dimensions of the silicon wafer substrate were selected to be M10, the side length was generally 182-182.3mm, and solar cell examples 1 to 7 were prepared according to the above method, and the parameters of the solar cell structure portion are shown in Table 1.
Wherein, the lightly doped conductive region in embodiments 1 to 7 includes a first polysilicon layer, a second polysilicon layer, a nano silicon oxide layer and a third polysilicon layer which are stacked.
The back surface of the solar cell of comparative example 1 was laminated with a tunneling layer, and a selective contact structure, a first passivation layer and a first electrode on the surface of the tunneling layer in this order, wherein the selective contact structure comprises a heavily doped conductive region and a lightly doped conductive region.
The rear surface of the solar cell in comparative example 2 was sequentially laminated with a tunneling layer, a doped blocking layer, and a selective contact structure comprising a heavily doped conductive region and a lightly doped conductive region, a first passivation layer, and a first electrode on the surface of the doped blocking layer; the lightly doped conductive region comprises a first layer of polysilicon layer, a second layer of polysilicon layer and a third layer of polysilicon layer which are stacked. "
The solar cell of comparative example 3 is a conventional TOPCon having a structure as shown in fig. 5, in which the tunneling layer 20 has a doped conductive layer 40' on its surface, and the doping concentration is the same as that of the lightly doped conductive region of example 1.
Table 1 parameters of solar cells
The test results of the obtained solar cells are shown in table 2:
TABLE 2 test results of solar cells
| Sample of | Open circuit voltage (mV) | Short-circuit current (A) | Fill factor% | Photoelectric conversion efficiency (%) |
| Example 1 | 723 | 13.78 | 83.64 | 25.28 |
| Example 2 | 724 | 13.82 | 83.62 | 25.32 |
| Example 3 | 725 | 13.78 | 83.65 | 25.29 |
| Example 4 | 726 | 13.75 | 83.8 | 25.33 |
| Example 5 | 728 | 13.75 | 84.0 | 25.46 |
| Example 6 | 726 | 13.75 | 84.0 | 25.39 |
| Example 7 | 727 | 13.75 | 84.0 | 25.42 |
| Comparative example 1 | 722 | 13.74 | 83.58 | 25.26 |
| Comparative example 2 | 722 | 13.75 | 83.58 | 25.26 |
| Comparative example 3 | 721 | 13.73 | 83.6 | 25.01 |
According to the test results of examples 1 to 7, the TOPCon solar cell can improve the filling factor efficiency and the solar conversion efficiency compared with the common TOPCon cell under the synergistic effect of the barrier layer, the selective passivation contact structure and the nano silicon oxide layer. And a blocking layer is arranged between the tunneling layer and the doped conductive layer, the blocking layer is used for preventing excessive N-type doped elements such as phosphorus and the like in the doped conductive layer from diffusing into the tunneling layer to damage the tunneling effect in the preparation process, a plurality of stacked polysilicon layers are constructed in the lightly doped conductive region, positive charges of the nano silicon oxide layers between the polysilicon layers have an attraction effect on electron carriers, potential barriers of the doped conductive layer can be improved, infrared reflection loss is reduced, and open-circuit voltage of the battery is improved.
The solar cell prepared in comparative example 1 was not provided with a blocking layer, and the tunneling effect of the tunneling layer was slightly affected, and the open circuit voltage, the fill factor and the solar conversion efficiency of the solar cell were all affected.
The solar cell prepared in comparative example 2, in which the lightly doped conductive region was not provided with the nano silicon oxide layer, increased infrared reflection loss, and had an influence on the open circuit voltage, the fill factor, and the solar conversion efficiency of the solar cell.
Comparative example 3 is a conventional TOPCon cell and the solar cell has overall performance inferior to that of examples 1 to 7.
While the application has been described in terms of the preferred embodiment, it is not intended to limit the scope of the claims, and any person skilled in the art can make many variations and modifications without departing from the spirit of the application, so that the scope of the application shall be defined by the claims.
Claims (13)
1. A solar cell, the solar cell comprising:
A semiconductor substrate;
a tunneling layer located at a rear surface of the semiconductor substrate;
A doped barrier layer located on at least a portion of a surface of the tunneling layer;
the doped conductive layer is positioned on the surface of the doped barrier layer and comprises lightly doped conductive areas and heavily doped conductive areas which are alternately arranged, wherein the lightly doped conductive areas comprise N layers of polysilicon layers which are arranged in a layer-by-layer mode, and a nano silicon oxide layer is arranged between at least two layers of polysilicon layers, and N is more than or equal to 3;
The first passivation layer is positioned on the surface of the lightly doped conductive area; and
And the first electrodes are in one-to-one correspondence with and contact with the heavily doped conductive regions.
2. The solar cell of claim 1, wherein the width of the heavily doped conductive region is greater than or equal to the width of the first electrode.
3. The solar cell of claim 1, wherein the doped barrier layer is disposed on an entire surface of the tunneling layer remote from the semiconductor substrate.
4. The solar cell of claim 1, wherein the doped barrier layer is disposed between a portion of a surface of the tunneling layer and between the tunneling layer and the heavily doped conductive region.
5. Solar cell according to claim 3 or 4, characterized in that it fulfils at least one of the following characteristics:
(1) The thickness of the lightly doped conductive area is H1 nm, H1 is more than or equal to 40 and less than or equal to 100;
(2) The thickness of the heavily doped conductive region is H2 nm, H2 is more than or equal to 60 and less than or equal to 130;
(3) The thickness of the heavily doped conductive region is H2 nm, and the thickness of the lightly doped conductive region is H1 nm, H2-H1 is more than or equal to 20 and less than or equal to 50;
(4) The width of the lightly doped conductive area is D1 mu m, and D1 is more than or equal to 200 and less than or equal to 1500;
(5) The width of the heavily doped conductive region is D2 mu m, and D2 is more than or equal to 40 and less than or equal to 90.
6. The solar cell of claim 1, wherein the lightly doped conductive region comprises a first polysilicon layer, a second polysilicon layer, and a third polysilicon layer stacked together, and a nano silicon oxide layer is disposed between the second polysilicon layer and the third polysilicon layer.
7. The solar cell of claim 6, wherein the third polysilicon layer has a band gap greater than the band gap of the nano-silicon oxide layer.
8. The solar cell of claim 1, wherein the lightly doped conductive region has a phosphorus doping concentration of 0.8e20 cm -3～4E20 cm-3 and the heavily doped conductive region has a doping concentration of 4E20 cm -3～12E20 cm-3.
9. The solar cell of claim 1, wherein the doped barrier layer comprises at least one of a gallium nitride layer, a gallium oxide layer, an aluminum oxide layer, a silicon carbide layer, a silicon nitride layer, and a silicon oxynitride layer; and/or the thickness of the doped barrier layer is 0.4 nm-2.0 nm.
10. The solar cell of claim 1, further comprising a second passivation layer and a second electrode on a front surface of the semiconductor substrate.
11. The solar cell according to claim 10, characterized in that it satisfies at least one of the following characteristics:
(1) The thickness of the tunneling layer is 0.8 nm-2.5 nm;
(2) The first passivation layer comprises at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer and a silicon oxynitride layer;
(3) The second passivation layer comprises at least one of a silicon nitride layer, a silicon oxide layer and a silicon oxynitride layer;
(4) The thickness of the first passivation layer and the second passivation layer is 70nm-120nm;
(5) The semiconductor substrate is an N-type monocrystalline silicon substrate, and the doped conductive layer is an N-type doped polycrystalline silicon layer or an N-type doped silicon carbide layer.
12. A method of manufacturing a solar cell according to any one of claims 1 to 11, comprising the steps of:
Performing texturing treatment on the semiconductor substrate;
Forming a tunneling layer on the rear surface of the semiconductor substrate;
depositing a barrier layer on at least part of the surface of the tunneling layer;
forming a mask on the surface of the barrier layer, and removing a part of material from the mask to form exposed first areas which are arranged at intervals;
Forming a first polysilicon region in the first region, wherein the first polysilicon region comprises N polysilicon layers which are arranged in a layer-by-layer manner, and a nano silicon oxide layer is arranged between at least two polysilicon layers, wherein N is more than or equal to 3;
forming a second mask on the surface of the first polysilicon region, depositing polysilicon in an uncovered region of the second mask, and performing in-situ doping treatment to form a second polysilicon region;
performing secondary doping treatment on the first polycrystalline silicon region and the second polycrystalline silicon region to obtain a lightly doped conductive region, a heavily doped conductive region and a doped barrier layer;
forming a first passivation layer on the surface of the lightly doped conductive area; and
And forming a first electrode on the surface of the heavily doped conductive region.
13. A photovoltaic module comprising a plurality of solar cell strings comprising the solar cell of any one of claims 1-11.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016068711A2 (en) * | 2014-10-31 | 2016-05-06 | Technische Universiteit Delft | Back side contacted wafer-based solar cells with in-situ doped crystallized silicon oxide regions |
| CN108447918A (en) * | 2018-03-29 | 2018-08-24 | 晶澳（扬州）太阳能科技有限公司 | A kind of doped structure and preparation method thereof of passivation contact polysilicon membrane |
| CN108701727A (en) * | 2015-09-30 | 2018-10-23 | 泰姆普雷斯艾普公司 | Manufacture the method for solar cell and thus obtained solar cell |
| CN110838536A (en) * | 2019-11-28 | 2020-02-25 | 泰州中来光电科技有限公司 | Back contact solar cell with various tunnel junction structures and preparation method thereof |
| JP2020077851A (en) * | 2018-09-24 | 2020-05-21 | フラウンホーファー−ゲゼルシャフト ツール フエルデルング デア アンゲヴァンテン フォルシュング エー．ファオ． | Process for producing photovoltaic solar cell having heterojunction and diffused-in emitter region |
| CN112466960A (en) * | 2020-11-10 | 2021-03-09 | 浙江晶科能源有限公司 | Solar cell structure and preparation method thereof |
| CN112736159A (en) * | 2020-12-31 | 2021-04-30 | 三江学院 | Preparation method of selective polycrystalline silicon thickness and doping concentration battery structure |
| WO2023284771A1 (en) * | 2021-07-14 | 2023-01-19 | 天合光能股份有限公司 | Selective passivated contact cell and preparation method therefor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160084261A (en) * | 2015-01-05 | 2016-07-13 | 엘지전자 주식회사 | Solar cell and manufacturing method thereof |
-
2023
- 2023-02-08 CN CN202310155830.0A patent/CN116110978B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016068711A2 (en) * | 2014-10-31 | 2016-05-06 | Technische Universiteit Delft | Back side contacted wafer-based solar cells with in-situ doped crystallized silicon oxide regions |
| CN108701727A (en) * | 2015-09-30 | 2018-10-23 | 泰姆普雷斯艾普公司 | Manufacture the method for solar cell and thus obtained solar cell |
| CN108447918A (en) * | 2018-03-29 | 2018-08-24 | 晶澳（扬州）太阳能科技有限公司 | A kind of doped structure and preparation method thereof of passivation contact polysilicon membrane |
| JP2020077851A (en) * | 2018-09-24 | 2020-05-21 | フラウンホーファー−ゲゼルシャフト ツール フエルデルング デア アンゲヴァンテン フォルシュング エー．ファオ． | Process for producing photovoltaic solar cell having heterojunction and diffused-in emitter region |
| CN110838536A (en) * | 2019-11-28 | 2020-02-25 | 泰州中来光电科技有限公司 | Back contact solar cell with various tunnel junction structures and preparation method thereof |
| CN112466960A (en) * | 2020-11-10 | 2021-03-09 | 浙江晶科能源有限公司 | Solar cell structure and preparation method thereof |
| CN112736159A (en) * | 2020-12-31 | 2021-04-30 | 三江学院 | Preparation method of selective polycrystalline silicon thickness and doping concentration battery structure |
| WO2023284771A1 (en) * | 2021-07-14 | 2023-01-19 | 天合光能股份有限公司 | Selective passivated contact cell and preparation method therefor |
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