CN114256361B - Solar cell and photovoltaic module - Google Patents

Solar cell and photovoltaic module Download PDF

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Publication number
CN114256361B
CN114256361B CN202111464295.4A CN202111464295A CN114256361B CN 114256361 B CN114256361 B CN 114256361B CN 202111464295 A CN202111464295 A CN 202111464295A CN 114256361 B CN114256361 B CN 114256361B
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layer
oxide layer
oxide
amorphous silicon
semiconductor substrate
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CN114256361A (en
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杨楠楠
金井升
张昕宇
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Zhejiang Jinko Solar Co Ltd
Jinko Solar Co Ltd
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Zhejiang Jinko Solar Co Ltd
Jinko Solar Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Abstract

The application relates to a solar cell and a photovoltaic module, wherein the solar cell comprises a semiconductor substrate, and the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged; the emitter and the front passivation layer are sequentially positioned on the front of the semiconductor substrate; the back passivation layer comprises a doped amorphous silicon layer, a first oxide layer, a second oxide layer and a conductive layer, wherein the doped amorphous silicon layer, the first oxide layer, the second oxide layer and the conductive layer are sequentially arranged on the back of the semiconductor substrate; wherein the doping element in the doped amorphous silicon layer has the same conductivity type as the doping element in the semiconductor substrate; and a front electrode in contact with the emitter electrode. The solar cell can ensure good contact of the back surface of the semiconductor substrate, reduce the light absorption effect of the back surface of the semiconductor substrate and improve the conversion efficiency of the solar cell.

Description

Solar cell and photovoltaic module
Technical Field
The application relates to the technical field of photovoltaic cells, in particular to a solar cell and a photovoltaic module.
Background
With the development of the photovoltaic industry, in the production of the battery sheet, the improvement of the photoelectric conversion efficiency and the reduction of the manufacturing cost of the battery have become the fundamental factors of the development of the whole photovoltaic industry. Based on the characteristics, the main research directions at present are HIT batteries, N-type double-sided batteries, back passivation batteries and the like, wherein the back passivation batteries are simple in preparation process and low in cost, but the photoelectric conversion efficiency of the back passivation batteries is limited, the photoelectric conversion efficiency of the HIT batteries is high, but the preparation cost of the back passivation batteries is high, so that the solar batteries capable of improving the efficiency of the solar batteries and reducing the production cost are urgently needed at present.
Disclosure of Invention
In view of the above, the application provides a solar cell, a preparation method thereof and a photovoltaic module, which can ensure good contact of the back surface of a semiconductor substrate, reduce the light absorption effect of the back surface of the semiconductor substrate, and further improve the conversion efficiency of the solar cell.
In a first aspect, embodiments of the present application provide a solar cell, including:
a semiconductor substrate including a front surface and a back surface disposed opposite to each other;
the emitter, the front passivation layer and/or the antireflection layer are/is sequentially positioned on the front of the semiconductor substrate;
the back passivation layer comprises a doped amorphous silicon layer, a first oxide layer, a second oxide layer and a conductive layer, wherein the doped amorphous silicon layer, the first oxide layer, the second oxide layer and the conductive layer are sequentially arranged on the back of the semiconductor substrate, the second oxide layer and the conductive layer are arranged on the surface of the first oxide layer at intervals, and the doped elements in the doped amorphous silicon layer have the same conductivity type as the doped elements in the semiconductor substrate;
a front electrode in contact with the emitter electrode and a back electrode in contact with the conductive layer. In a second aspect, embodiments of the present application provide a photovoltaic module comprising a plurality of solar cell strings, each of the solar cell strings being formed by electrically connecting solar cells of the first aspect.
The technical scheme of the application has the following beneficial effects: according to the solar cell, the passivation performance and contact can be improved by sequentially forming the laminated passivation contact structure of the doped amorphous silicon layer, the first oxide layer, the second oxide layer and the conductive layer on the back surface of the semiconductor substrate; in addition, the second oxide layer and the conductive layer are arranged on the surface of the first oxide layer at intervals, so that the light absorption effect of the back surface of the semiconductor substrate is reduced while the back surface of the semiconductor substrate is well contacted, the short-circuit current of the battery can be effectively improved, and the conversion efficiency of the solar battery is further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
For a clearer description of embodiments of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some embodiments of the present application, and that other drawings may be obtained from these drawings by a person of ordinary skill in the art without inventive effort.
FIG. 1 is a flow chart of the preparation of a solar cell of the present application;
FIG. 2 is a schematic diagram of the front structure of the battery of the present application;
FIG. 3 is a schematic view of a structure of a stacked backside passivation layer formed in accordance with the present application;
FIG. 4 is a schematic view of the structure of the coating organic slurry layer of the present application;
FIG. 5 is a schematic view of the structure of the present application after removal of the conductive layer without the paste coverage area;
FIG. 6 is a schematic diagram of the structure of the present application after removal of the second oxide layer of the non-slurry covered region;
FIG. 7 is a schematic view of the structure of the present application after removal of the slurry layer;
fig. 8 is a schematic structural view of the solar cell of the present application.
In the figure: 100-a semiconductor substrate;
200-emitter;
300-an anti-reflection layer;
400-doping an amorphous silicon layer;
500-a first oxide layer;
600-a second oxide layer;
700-a conductive layer;
800-slurry layer;
801-slurry layer coverage area;
802-non-slurry layer coverage area;
900—a front side passivation layer;
110-a backside passivation layer;
120-front electrode;
130-back electrode.
Detailed Description
For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the existing solar cell, the relatively efficient cell is a passivation contact cell, in the TOPCO cell, the back of the cell is composed of a layer of ultrathin silicon oxide and a layer of phosphorus doped polysilicon film, the two layers together form a passivation contact structure, so that surface recombination and metal contact recombination can be effectively reduced, however, the TOPCO cell only forms a passivation structure on the back of the cell, and the photoelectric conversion efficiency of the TOPCO cell is limited. In a Heterojunction (HIT) cell, the performance of the PN junction can be improved by depositing a layer of undoped (intrinsic) hydrogenated amorphous silicon film and a layer of doped hydrogenated amorphous silicon film of the opposite doping type to crystalline silicon on a crystalline silicon wafer, but the fabrication cost of the heterojunction cell is high, and the heterojunction structure on the back side has a serious light absorption effect.
Therefore, in order to overcome the defect of the prior art, the technical scheme of the embodiment of the invention provides a solar cell and a photovoltaic module, wherein the back of the cell is provided with an amorphous silicon doped layer, a first oxide layer, a second oxide layer arranged on the surface of the first oxide layer at intervals and a conductive layer arranged on the surface of the second oxide layer.
An embodiment of the present application provides a method for preparing a solar cell, as shown in fig. 1, which is a preparation flow chart of the solar cell, and includes the following steps:
step S100, forming an emitter 200 on the surface of the semiconductor substrate 100 after the flocking;
step S200, forming a front passivation layer 900 on the surface of the emitter 200;
step S300, forming a back passivation layer 110 on the back surface of the semiconductor substrate 100, wherein the back passivation layer 110 includes a doped amorphous silicon layer 400, a first oxide layer 500, a second oxide layer 600 arranged on the surface of the first oxide layer 500 at intervals, and a conductive layer 700 on the surface of the second oxide layer 600, which are sequentially arranged on the back surface of the semiconductor substrate 100;
step S400, forming a slurry layer 800 on the surface of the conductive layer 700, removing the conductive layer 700 in the non-slurry layer area 802, removing the second oxide layer 600 in the non-slurry layer area 802, and finally removing the slurry layer 800.
Step S500, forming the back electrode 130 on the surface of the back passivation layer 110.
In step S600, the front electrode 120 is formed on the surface of the front passivation layer 900.
Hereinafter, a method for manufacturing a solar cell of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present invention, and the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
And step S100, forming an emitter 200 on the surface of the semiconductor substrate 100 after texturing.
In some embodiments, the semiconductor substrate 100 is an N-type substrate, and the N-type substrate may be a crystalline silicon substrate (silicon substrate), such as a polysilicon substrate, a monocrystalline silicon substrate, or a monocrystalline-like silicon substrate, which is not limited by the specific type of the semiconductor substrate 100 in the embodiments of the present invention.
In some embodiments, emitter 200 is a P-type emitter.
In this embodiment, boron diffusion is performed on the surface of the semiconductor substrate 100 to form a boron diffusion layer, thereby obtaining a P-type emitter. Boron diffusion is a process of forming a boron diffusion layer by diffusing boron atoms through a boron source, such as boron tribromide.
In some embodiments, the emitter 200 may be formed on the surface of the semiconductor substrate 100 using any one or more of high temperature diffusion, slurry doping, or ion implantation.
In some embodiments, the front and back sides of the N-type semiconductor substrate 100 may be textured prior to forming the emitter 200 to form a textured or surface texture (e.g., pyramidal structures). The manner of the texturing process may be chemical etching, laser etching, mechanical method, plasma etching, etc., and is not limited herein. Illustratively, the front and back surfaces of the N-type semiconductor substrate 100 may be textured with NaOH solution, and pyramid-structured texturing may be prepared due to anisotropy of the NaOH solution.
In this embodiment, the surface of the N-type semiconductor substrate 100 is textured to generate a light trapping effect, so as to increase the light absorption quantity of the solar cell, thereby improving the conversion efficiency of the solar cell.
In some embodiments, a step of cleaning the semiconductor substrate 100 to remove surface metal and organic contaminants may also be included prior to the texturing process.
In some embodiments, the front side of the semiconductor substrate 100 is the sun-facing surface (i.e., the light-receiving surface), and the back side of the silicon substrate is the sun-facing surface (i.e., the back surface).
After step S100, the method further includes removing a borosilicate glass layer (BSG) formed during the boron diffusion process on the back surface of the semiconductor substrate 100, where it is understood that the borosilicate glass layer has a metal gettering effect, which affects the normal operation of the solar cell and needs to be removed.
In a specific embodiment, the back side of the semiconductor substrate 100 may be placed downward in a chain type acid washing apparatus (the belt speed of the chain type apparatus is 1.0 m/min-2.0 m/min, the semiconductor substrate 100 enters an acid tank, and a borosilicate glass layer (BSG) formed by back side boron diffusion is etched away).
After pickling, washing operation is needed, the washing time is 10-20 s, and the washing temperature is 15-25 ℃; of course, the semiconductor substrate 100 may be subjected to a drying process after the washing with water.
Step S200, a front passivation layer 900 is formed on the surface of the emitter 200.
In some embodiments, passivation is performed on the front surface of the semiconductor substrate 100 to form the front passivation layer 900 and/or the anti-reflection layer 300 (also referred to as "anti-reflection layer") on the upper surface of the emitter 200, for example, the front passivation layer 900 may be formed, or the anti-reflection layer 300 may be formed, or the front passivation layer 900 and the anti-reflection layer 300 may be formed, as shown in fig. 2, which is a schematic structural diagram of forming the front passivation layer 900 and the anti-reflection layer 300.
In some embodiments, the specific materials of the front passivation layer 900 and/or the anti-reflection layer 300 are not limited in the examples. For example, an aluminum oxide/silicon nitride stacked structure may be used as the front passivation layer 900, and at the same time, the stacked structure may be the anti-reflection layer 300, or silicon oxynitride may be used as the front passivation layer 900 and the anti-reflection layer 300, but not limited thereto, for example, the front passivation layer 900 may be a stacked structure formed of one or more of silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, silicon nitride layer, silicon oxide, silicon nitride, or gallium oxide, the anti-reflection layer 300 is a silicon nitride layer, and the like.
In this embodiment, the stacked layer formed by the front passivation layer 900 and the anti-reflection layer 300 has a good passivation effect, and can improve the photoelectric conversion efficiency of the solar cell. In addition, the anti-reflection layer 300 is provided to reduce reflection of light, increase the amount of light absorbed by the solar cell, and perform passivation effect to improve photoelectric conversion efficiency of the solar cell.
In some embodiments, the front passivation layer 900 is prepared by any one of Atomic Layer Deposition (ALD) and Plasma Enhanced Chemical Vapor Deposition (PECVD), and the preparation method of the front passivation layer 900 is not limited in the present invention. Accordingly, the apparatus used for deposition may be an ALD apparatus, a PECVD apparatus, or the like.
It should be noted that, in the embodiment of the present application, the thicknesses of the front passivation layer 900 and the anti-reflection layer 300 are not limited, and may be adjusted by those skilled in the art according to the actual situation. The front passivation layer 900 may have a thickness of 50nm to 120nm, for example, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, etc., and the anti-reflection layer 300 may have a thickness of 40nm to 80nm, for example, 40nm, 50nm, 60nm, 70nm, 80nm, etc.
In step S300, a back passivation layer 110 is formed on the back surface of the semiconductor substrate 100, where the back passivation layer 110 includes a doped amorphous silicon layer 400, a first oxide layer 500, a second oxide layer 600, and a conductive layer 700 sequentially disposed on the back surface of the semiconductor substrate 100, and the resulting structure is shown in fig. 3.
Specifically, step S300 includes:
step S301 forms a doped amorphous silicon layer 400 on the back surface of the semiconductor substrate 100.
In some embodiments, an amorphous silicon layer may be formed on the back surface of the semiconductor substrate 100, and then doped to form the doped amorphous silicon layer 400; deposition and doping may also be performed simultaneously on the back side of the semiconductor substrate 100 to form the doped amorphous silicon layer 400.
In some embodiments, the amorphous silicon layer is deposited at a low temperature, and in particular, the amorphous silicon layer may be prepared by any one or more of Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD), and the preparation method of the doped amorphous silicon layer 400 is not limited in the present invention. Accordingly, the apparatus used for deposition may be a CVD apparatus, a PVD apparatus, an ALD apparatus, or the like.
In some embodiments, the low-temperature deposition temperature is 100-300 ℃, the low-temperature deposition temperature can be specifically 100 ℃, 110 ℃, 120 ℃, 150 ℃, 170 ℃, 200 ℃, 220 ℃, 250 ℃ and 300 ℃, and the like, and the low-temperature deposition temperature is limited in the range, so that the amorphous silicon film layer can be formed, the local amorphous silicon can be crystallized, and the photoelectric performance of the battery is further improved.
In some embodiments, the doping element conductivity type of the doped amorphous silicon layer 400 is the same as the doping element conductivity type of the semiconductor substrate 100. For example, the semiconductor substrate 100 is an N-type substrate, and the doped element is an N-type doped element, such as a phosphorus element or an arsenic element, and the formed doped amorphous silicon layer 400 may be a phosphorus doped amorphous silicon layer or an arsenic doped amorphous silicon layer.
In some embodiments, the thickness of the doped amorphous silicon layer 400 is 10nm to 100nm, and the thickness of the doped amorphous silicon layer 400 may be specifically 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc., and the thickness of the doped amorphous silicon layer 400 greater than 100nm may affect the carrier transport, resulting in poor conductivity of the battery; the thickness of the doped amorphous silicon layer 400 is less than 10nm, and thus the desired passivation effect is not achieved.
In step S302, a first oxide layer 500 is formed on the surface of the doped amorphous silicon layer 400.
In some embodiments, the first oxide layer 500 is formed by oxidation or deposition, specifically, the first oxide layer 500 is deposited by at least one of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD), and the first oxide layer 500 is oxidized by at least one of ozone oxidation, thermal oxidation and nitric acid oxidation, which are not limited in the method for forming the first oxide layer 500. The material of the first oxide layer 500 includes silicon oxide, and the material of the first oxide layer may be at least one of silicon oxynitride and aluminum oxide. The first oxide layer 500 blocks minority carrier hole recombination while tunneling the minority carrier into the doped amorphous silicon layer 400, so that electrons are laterally transported in the doped amorphous silicon layer 400 and collected by metal, and the metal contact recombination current is greatly reduced.
Step S303, forming a second oxide layer 600 on the surface of the first oxide layer 500.
In some embodiments, the second oxide layer 600 is formed by deposition, and in particular, the first oxide layer 500 is deposited by at least one of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD). The second oxide layer 600 may also be formed by oxidation, and specifically, the oxidation of the second oxide layer 600 includes at least one of ozone oxidation, high temperature thermal oxidation, and nitric acid oxidation, which is not limited in the method for forming the second oxide layer 600.
In some embodiments, the material of the second oxide layer 600 includes molybdenum oxide, where molybdenum oxide is used as a non-toxic, high work function and high conductivity N-type semiconductor material, and the molybdenum oxide is disposed on the back surface of the solar cell, so that intrinsic electron loss between electron donors and acceptors of back electrons and holes on the interface layer can be effectively reduced, contact type recombination of back electrons and holes is reduced, electron transfer from the electron acceptor fullerene is blocked, and hole transfer rate is improved.
Step S304, a conductive layer 700 is formed on the surface of the second oxide layer 600.
In some embodiments, the conductive layer 700 may be a transparent conductive layer (TCO). The conductive layer 700 is prepared by any one of a Plasma Enhanced Chemical Vapor Deposition (PECVD), a Low Pressure Chemical Vapor Deposition (LPCVD), a Hot Wire Chemical Vapor Deposition (HWCVD) and an Atomic Layer Deposition (ALD), and the preparation method of the conductive layer 700 is not limited in this application, but of course, the preparation of the conductive layer 700 may be performed by using a silicon target, a silicon oxide target, a silicon carbide target in combination with a magnetron sputtering apparatus.
In some embodiments, the material of the conductive layer 700 may be at least one of oxide, nitride, doped oxide and mixed oxide, and In particular, the oxide may be In 2 O 3 、SnO 2 ZnO, cdO, the nitride can be TiN, and the doped oxide can be In 2 O 3 :Sn、ZnO:In，ZnO:Ga，ZnO:Al，SnO 2 :F，SnO 2 Ta, mixed oxide may be In 2 O 3 -ZnO，CdIn 2 O 4 ，Cd 2 SnO 4 ，Zn 2 SnO 4 The conductive layer 700 serves as a carrier transport layer on the back side of the semiconductor substrate 100, and can raise the open circuit voltage and the fill factor of the battery.
In step S400, as shown in fig. 4, a paste layer 800 with a Selective Electrode (SE) pattern is formed on the surface of the conductive layer 700.
In some embodiments, the slurry layer 800 is formed by coating the surface of the conductive layer 700 with a corrosion resistant material, and the surface of the conductive layer 700 is divided into two areas by the arrangement of the slurry layer 800: a slurry layer coverage area 801 and a non-slurry layer coverage area 802, namely the slurry layer coverage area 801 is provided with a slurry layer 800, the slurry layer coverage area 801 is a metal electrode contact area, and the slurry layer 800 corresponds to the position of a preset electrode; the non-paste layer coverage area 802 is the other area of the conductive layer surface than the paste layer coverage area. The purpose of the present application is to form a selective passivation structure in the slurry layer covered region by providing a slurry layer of Selective Electrode (SE) pattern for the purpose of subsequently forming a passivation layer in the non-slurry covered region 802.
In step S500, the conductive layer 700 of the non-slurry layer coverage area 802 is removed, the removed structure is shown in fig. 5, the second oxide layer 600 of the non-slurry layer coverage area 802 is removed, the obtained structure is shown in fig. 6, and finally, the slurry layer 800 is removed, and the obtained structure is shown in fig. 7.
In some implementationsIn an embodiment, the conductive layer 700 of the non-slurry layer covering region 802 is removed by an etching solution, specifically, the etching solution includes HF, HF/HNO 3 When the etching solution is used for the treatment, since the surface of a part of the conductive layer 700 (the conductive layer of the preset back electrode area) is covered with the slurry layer 800, the exposed conductive layer 700 is removed after being subjected to the acid etching solution, thereby obtaining a partially arranged conductive layer structure.
In some embodiments, an acid or base solution is used to remove the second oxide layer 600 of the non-slurry layer covered region 802. Specifically, the acid solution comprises HF, HF/HNO 3 The alkali solution comprises at least one of NaOH, KOH and tetramethyl ammonium hydroxide TMAH. When the second oxide layer 600 of the non-slurry layer covering region 802 is not covered by the slurry layer, an acid solution may be used alone, an alkali solution may be used alone, both the acid solution and the alkali solution may be used to treat the second oxide layer 600 of the non-slurry layer covering region 802, and when the acid solution and the alkali solution are selected, the acid solution may be used first to treat the second oxide layer 600 and then the alkali solution may be used, and the alkali solution may be used first to treat the second oxide layer 500 and then the acid solution or the alkali solution may be used, which is soluble in the second oxide layer 600 and insoluble in the first oxide layer 500, so that the second oxide layer forms a selective structure.
In some embodiments, the slurry layer is removed with an organic solution, specifically, the organic solution includes at least one of ethanol, isopropanol.
In the steps, the second oxide layer and the conductive layer form a selective structure which is arranged on the surface of the first oxide layer at intervals through chemical treatment, so that the passivation effect of the battery can be improved, the light absorption effect of the back surface of the battery can be reduced, and the conversion efficiency of the battery can be improved.
In step S600, the back electrode 130 is formed on the surface of the back passivation layer 110, and the resulting solar cell structure is shown in fig. 8.
In some embodiments, a metallization process is performed on the lower surface of the semiconductor substrate 100 to form the back electrode 130.
Specifically, the positions of the back electrode 130 and the conductive layer 700 are in one-to-one correspondence, and the back electrode 130 may be prepared by a screen printing method and sintered, so that the back electrode 130 and the conductive layer 700 form ohmic contact.
The specific material of the back electrode 130 is not limited in the embodiment of the present application. Illustratively, when the back electrode 130 forms an ohmic contact with the conductive layer 700, the back electrode 130 is a silver electrode.
In some embodiments, the thickness of the back passivation layer 110 is 60nm to 120nm, which may be, for example, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, and the like.
In step S700, the front electrode 120 is formed on the surface of the front passivation layer 900.
In some embodiments, a metallization process is performed on the surface of the semiconductor substrate 100 to form the front electrode 120. The front electrode 120 may be prepared by a screen printing method and sintered such that the front electrode 120 forms an ohmic contact with the emitter 200 through the front passivation layer 900.
The specific material of the front electrode 120 is not limited in the embodiment of the present application. For example, when the front electrode is in ohmic contact with the emitter electrode 200, the front electrode 120 is a silver electrode or a silver/aluminum electrode, for example, silver paste may be printed or silver paste doped with a small amount of aluminum, that is, silver/aluminum paste, on the upper surface of the front passivation layer 900 corresponding to the emitter electrode 200, and the pastes may be fired through the front passivation layer 900.
It should be noted that, the thickness of the front passivation layer 900 is not limited in the embodiments of the present application, and may be adjusted by those skilled in the art according to practical situations. Illustratively, the front passivation layer 900 may have a thickness of 5nm to 30nm, and the front passivation layer 900 may have a thickness of 5nm, 6nm, 7nm, 8nm, 10nm, 15nm, 18nm, 20nm, 23nm, 26nm, 28nm, 30nm, and the like.
In this application, unless otherwise indicated, the steps may or may not be performed sequentially. The order of steps for preparing the solar cell is not limited in the embodiment of the application, and can be adjusted according to actual production process.
The embodiment of the application also provides a solar cell which can be prepared by adopting the preparation method of the solar cell.
The solar cell and the method for manufacturing the solar cell provided in the embodiments of the present application are based on the same inventive concept, so that the method for manufacturing the solar cell has at least all the features and advantages of the method for manufacturing the solar cell described above, and will not be described in detail herein.
Specifically, the solar cell comprises:
a semiconductor substrate 100, the semiconductor substrate 100 including a front surface and a back surface disposed opposite to each other;
an emitter 200, a front passivation layer 900 and/or an anti-reflection layer 300 located in sequence on the front side of the semiconductor substrate 100;
the back passivation layer 110 is positioned on the back of the semiconductor substrate 100, and the back passivation layer 110 comprises a doped amorphous silicon layer 400, a first oxide layer 500, a second oxide layer 600 and a conductive layer 700, wherein the doped amorphous silicon layer 400, the first oxide layer 500, the second oxide layer 600 and the conductive layer 700 are sequentially arranged on the surface of the first oxide layer 500 at intervals, and the conductive type of the doped element in the doped amorphous silicon layer 400 is the same as the conductive type of the doped element in the semiconductor substrate 100;
a front electrode 120 in contact with the emitter 200, and a back electrode 130 in contact with the conductive layer 700.
In the above technical solution, in the solar cell of the present application, the passivation performance and contact can be improved by sequentially forming the stacked passivation contact structure of the doped amorphous silicon layer 400, the first oxide layer 500, the second oxide layer 600 and the conductive layer 700 on the back surface of the semiconductor substrate 100; in addition, the second oxide layer 600 and the conductive layer 700 are arranged at intervals on the surface of the first oxide layer 500, so that the light absorption effect of the back surface of the semiconductor substrate 100 is reduced while the good contact of the back surface of the semiconductor substrate 100 is ensured, the short-circuit current of the battery can be effectively improved, and the conversion efficiency of the solar battery is further improved.
In some embodiments, the front side of the semiconductor substrate 100 is the sun-facing surface (i.e., the light-receiving surface), and the back side of the silicon substrate is the sun-facing surface (i.e., the back surface).
In some embodiments, the material of the first oxide layer 500 includes at least one of silicon oxide, silicon oxynitride, and aluminum oxide. The first oxide layer 500 can make the electrons tunnel into the doped amorphous silicon layer 400 and block minority hole recombination, so that electrons are laterally transmitted and collected by metal in the doped amorphous silicon layer 400, and the metal contact recombination current is greatly reduced.
In some embodiments, the material of the second oxide layer 600 includes molybdenum oxide, where molybdenum oxide is used as a non-toxic, high work function and high conductivity N-type semiconductor material, and the molybdenum oxide is disposed on the back surface of the solar cell, so that intrinsic electron loss between electron donors and acceptors of back electrons and holes on the interface layer can be effectively reduced, contact type recombination of back electrons and holes is reduced, electron transfer from the electron acceptor fullerene is blocked, and hole transfer rate is improved.
In some embodiments, the distance between adjacent second oxide layers 600 is 1mm to 2mm, and the distance between adjacent second oxide layers 600 is 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm, 1.9mm, 2mm, etc., and the distance between adjacent second oxide layers 600 is set within the above range, which is beneficial to ensuring the transmission of carriers in the metal region, reducing the metal contact and simultaneously ensuring the light absorption in the nonmetal region.
In some embodiments, the contact area between the second oxide layer 600 and the first oxide layer 500 is denoted as S1, the surface area of the first oxide layer 500 contacting the doped amorphous silicon layer 400 is denoted as S2, and s1/s2=0.02 to 0.04, for example, may be 0.02, 0.03, 0.04, etc., which is beneficial to avoiding absorption of light by the non-metal region while guaranteeing contact of the metal region by defining the contact area between the second oxide layer 600 and the first oxide layer 500, thereby reducing energy consumption of the battery.
In some embodiments, as shown in fig. 7, since the first oxide layer 500 entirely covers the semiconductor substrate 100 and the conductive layer 700 partially covers the semiconductor substrate 100, the surface area S2 of the first oxide layer 500 contacting the doped amorphous silicon layer 400 can be determined by calculating the surface area of the semiconductor substrate 100, and the contact area S1 of the second oxide layer 600 and the first oxide layer 500 can be determined by testing the area of the conductive layer 700.
In some embodiments, the thickness of the first oxide layer 500 is 1nm to 5nm, and the thickness of the first oxide layer 500 may specifically be 1nm, 2nm, 3nm, 4nm, 5nm, and the like, which defines the thickness of the first oxide layer 500, so that it is beneficial to ensure that the oxide layer does not obstruct the transmission of carriers while passivating the battery, and the first oxide layer serves as a passivation protection layer, so that the passivation performance of the whole battery can be improved.
In some embodiments, the thickness of the second oxide layer 600 is 1m to 50nm, and the thickness of the second oxide layer 600 may be specifically 1nm, 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, etc., so as to define the thickness of the second oxide layer 600, which is advantageous for obtaining superior passivation and transmission performance, and preferably, the thickness of the second oxide layer 600 is 15nm to 40nm. The second oxide layer 600 serves as a passivation contact structure, which can improve passivation effect and conversion efficiency of the battery.
The thickness ratio of the first oxide layer 500 to the second oxide layer 600 is 1 (1 to 50), and the thickness ratio of the first oxide layer 500 to the second oxide layer 600 may be 1: 1. 1: 5. 1: 10. 1: 20. 1: 30. 1:40 and 1:50, etc., it is understood that the thickness of the first oxide layer 500 may be the same as the thickness of the second oxide layer 600, and the thickness of the first oxide layer 500 may also be different from the thickness of the second oxide layer 600, preferably, the thickness of the second oxide layer 600 is greater than the thickness of the first oxide layer 500, so as to further improve the passivation effect on the back surface of the cell and improve the performance of the solar cell. The ratio of the thicknesses of the first oxide layer 500 and the second oxide layer 600 is less than 1:1, the passivation performance and carrier transport of the battery are deteriorated, if the ratio of the thicknesses of the first oxide layer 500 and the second oxide layer 600 is greater than 1:50, the second oxide layer 600 is too thick, resulting in serious back side absorption and also reduced back side conductivity.
In some embodiments, the back passivation layer 110 has a thickness of 60nm to 120nm, which may be, for example, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, and the like.
In some embodiments, the semiconductor substrate 100 is an N-type substrate.
In some embodiments, the doped amorphous silicon layer 400 includes a phosphorus doped amorphous silicon layer or an arsenic doped amorphous silicon layer.
In some embodiments, the phosphorus doped amorphous silicon layer has a doping concentration of 9E19cm -3 ～1E21cm -3 The doping concentration of the phosphorus doped amorphous silicon layer can be 9E19cm -3 、1E20cm -3 、3E20 cm -3 、5E20cm -3 And 1E21cm -3 Etc. the doping concentration of the arsenic doped amorphous silicon layer is 9E19cm -3 ～1E21cm -3 The doping concentration of the arsenic doped amorphous silicon layer can be 9E19cm -3 、1E20cm -3 、3E20 cm -3 、5E20cm -3 And 1E21cm -3 And the like, the doping concentration of the phosphorus doped amorphous silicon layer or the arsenic doped amorphous silicon layer is controlled within the range, so that the excellent passivation performance of the battery is ensured, and the conductivity is improved.
In some embodiments, the thickness of the doped amorphous silicon layer 400 is 10nm to 100nm, and the thickness of the doped amorphous silicon layer 400 may be specifically 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, and the like, and controlling the thickness of the doped amorphous silicon layer 400 within the above range is beneficial to improving conductivity while ensuring passivation performance of the film.
In some embodiments, the sheet resistance of the doped amorphous silicon layer 400 may be in the range of 30 Ω/sqr to 150 Ω/sqr, specifically 30 Ω/sqr, 40 Ω/sqr, 50 Ω/sqr, 60 Ω/sqr, 70 Ω/sqr, 80 Ω/sqr, 90 Ω/sqr, 100 Ω/sqr, 110 Ω/sqr, 120 Ω/sqr, 130 Ω/sqr, 140 Ω/sqr, 150 Ω/sqr, etc.
The sheet resistance or diffusion concentration of the doped amorphous silicon layer 400 is limited in the above range, which helps to ensure passivation performance and conductivity of the solar cell, thereby improving photoelectric conversion efficiency of the solar cell and improving performance of the solar cell.
In some embodiments, the upper surface of the emitter 200 is provided with a front passivation layer 900 and/or an anti-reflection layer 300 (also referred to as an "anti-reflection layer"), for example, the front passivation layer 900 may be formed, or the anti-reflection layer 300 may be formed, or the front passivation layer 900 and the anti-reflection layer 300 may be formed.
The embodiment of the application also provides a photovoltaic module, which comprises a cover plate, a packaging material layer and a solar cell string which are sequentially stacked, wherein the parts form a stacked structure and the stacked structure is subjected to lamination treatment to obtain the photovoltaic module.
In some embodiments, the solar cell string comprises a plurality of solar cells as described above connected by conductive strips, and the solar cells may be partially stacked or spliced.
In some embodiments, the cover plate may be a transparent or opaque cover plate, such as a glass cover plate, a plastic cover plate. The two sides of the packaging material layer are respectively connected with the cover plate and the battery in series for lamination.
In some embodiments, the material of the packaging material layer may be an ethylene-vinyl acetate (EVA) adhesive film, a polyethylene octene co-elastomer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.
The photovoltaic module can also adopt side full-surrounding type packaging, namely the side of the photovoltaic module is completely encapsulated by adopting the packaging adhesive tape, so that the phenomenon of lamination offset of the photovoltaic module in the lamination process is prevented.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
While the preferred embodiment has been described, it is not intended to limit the scope of the claims, and any person skilled in the art can make several possible variations and modifications without departing from the spirit of the invention, so the scope of the invention shall be defined by the claims.

Claims (10)

1. A solar cell, comprising:
a semiconductor substrate including a front surface and a back surface disposed opposite to each other;
the emitter, the front passivation layer and/or the antireflection layer are/is sequentially positioned on the front of the semiconductor substrate;
the back passivation layer comprises a doped amorphous silicon layer, a first oxide layer, a second oxide layer and a conductive layer, wherein the doped amorphous silicon layer, the first oxide layer, the second oxide layer and the conductive layer are sequentially arranged on the back of the semiconductor substrate, the second oxide layer and the conductive layer are arranged on the surface of the first oxide layer at intervals, and the doped elements in the doped amorphous silicon layer have the same conductivity type as the doped elements in the semiconductor substrate;
a front electrode in contact with the emitter electrode and a back electrode in contact with the conductive layer.
2. The battery of claim 1, wherein the first oxide layer comprises at least one of silicon oxide, silicon oxynitride, and aluminum oxide.
3. The battery of claim 1, wherein the material of the second oxide layer comprises molybdenum oxide.
4. The battery of claim 1, wherein a distance between adjacent second oxide layers is 1mm to 2mm.
5. The battery according to claim 1, wherein a contact area of the second oxide layer and the first oxide layer is denoted as S1, and a surface area of the first oxide layer in contact with the doped amorphous silicon layer is denoted as S2, S1/s2=0.02 to 0.04.
6. The cell of claim 1, wherein the first oxide layer has a thickness of 1nm to 5nm and/or the second oxide layer has a thickness of 1nm to 50nm; and/or the thickness ratio of the first oxide layer to the second oxide layer is 1 (1-50).
7. The cell of claim 1, wherein the semiconductor substrate is an N-type substrate and the doped amorphous silicon layer is a phosphorus doped amorphous silicon layer or an arsenic doped amorphous silicon layer.
8. The cell of claim 7, wherein the phosphorus doped amorphous silicon layer has a doping concentration of 9E19cm -3 ～1E21cm -3 Or the doping concentration of the arsenic doped amorphous silicon layer is 9E19cm -3 ～1E21cm -3 。
9. The cell of claim 1, wherein the doped amorphous silicon layer has a thickness of 10nm to 100nm; and/or the thickness of the back passivation layer is 60 nm-120 nm.
10. A photovoltaic module comprising a plurality of solar cell strings, each of the solar cell strings being formed by electrically connecting the solar cells of any one of claims 1 to 9.
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