CN114256361A - Solar cell and photovoltaic module - Google Patents

Solar cell and photovoltaic module Download PDF

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Publication number
CN114256361A
CN114256361A CN202111464295.4A CN202111464295A CN114256361A CN 114256361 A CN114256361 A CN 114256361A CN 202111464295 A CN202111464295 A CN 202111464295A CN 114256361 A CN114256361 A CN 114256361A
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layer
semiconductor substrate
amorphous silicon
oxide
doped amorphous
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CN202111464295.4A
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CN114256361B (en
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杨楠楠
金井升
张昕宇
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Zhejiang Jinko Solar Co Ltd
Jinko Solar Co Ltd
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Zhejiang Jinko Solar Co Ltd
Jinko Solar Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Abstract

The application relates to a solar cell and a photovoltaic module, wherein the solar cell comprises a semiconductor substrate, the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged; an emitter and a front passivation layer sequentially positioned on the front surface of the semiconductor substrate; the back passivation layer is sequentially positioned on the back surface of the semiconductor substrate and comprises a doped amorphous silicon layer, a first oxidation layer, second oxidation layers and a conducting layer, wherein the doped amorphous silicon layer, the first oxidation layer, the second oxidation layers and the conducting layer are sequentially arranged on the back surface of the semiconductor substrate; wherein the doping element in the doped amorphous silicon layer has the same conductivity type as the doping element in the semiconductor substrate; a front electrode in contact with the emitter. The solar cell can ensure good contact on the back surface of the semiconductor substrate, reduces the light absorption effect on the back surface of the semiconductor substrate, and improves the conversion efficiency of the solar cell.

Description

Solar cell and photovoltaic module
Technical Field
The application relates to the technical field of photovoltaic cells, in particular to a solar cell and a photovoltaic module.
Background
With the development of the photovoltaic industry, in the production of battery pieces, the improvement of the photoelectric conversion efficiency and the reduction of the manufacturing cost of the battery become the root of the development of the whole photovoltaic industry. Based on the characteristics, the main research directions at present are HIT cells, N-type double-sided cells, back-passivated cells and the like, wherein the back-passivated cells are simple in preparation process and low in cost, but the photoelectric conversion efficiency of the back-passivated cells is improved to a limited extent, and the HIT cells are high in photoelectric conversion efficiency and high in preparation cost, so that the solar cells which can improve the efficiency of the solar cells and reduce the production cost are urgently needed.
Disclosure of Invention
In view of this, the present application provides a solar cell, a method for manufacturing the same, and a photovoltaic module, which can ensure good contact on the back surface of a semiconductor substrate and reduce the light absorption effect on the back surface of the semiconductor substrate, thereby improving the conversion efficiency of the solar cell.
In a first aspect, an embodiment of the present application provides a solar cell, including:
the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged;
the emitter, the front passivation layer and/or the antireflection layer are/is sequentially positioned on the front surface of the semiconductor substrate;
the back passivation layer is positioned on the back surface of the semiconductor substrate and comprises a doped amorphous silicon layer, a first oxidation layer, a second oxidation layer and a conducting layer, wherein the doped amorphous silicon layer, the first oxidation layer, the second oxidation layer and the conducting layer are sequentially arranged on the back surface of the semiconductor substrate, the second oxidation layer is arranged on the surface of the first oxidation layer and is arranged at intervals, and the conducting type of a doped element in the doped amorphous silicon layer is the same as that of a doped element in the semiconductor substrate;
a front electrode in contact with the emitter and a back electrode in contact with the conductive layer. In a second aspect, embodiments of the present application provide a photovoltaic module, which includes a plurality of solar cell strings, each of the solar cell strings being formed by electrically connecting the solar cells of the first aspect.
The technical scheme of the application has at least the following beneficial effects: according to the solar cell, the laminated passivation contact structure of the doped amorphous silicon layer, the first oxidation layer, the second oxidation layer and the conducting layer is formed on the back surface of the semiconductor substrate in sequence, so that the passivation performance and contact can be improved; moreover, the second oxide layer and the conducting layer are arranged on the surface of the first oxide layer at intervals, so that the light absorption effect of the back surface of the semiconductor substrate is reduced while good contact of the back surface of the semiconductor substrate is ensured, the short-circuit current of the cell can be effectively improved, and the conversion efficiency of the solar cell is further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of the solar cell fabrication process of the present application;
FIG. 2 is a schematic diagram of the front side of the battery of the present application;
FIG. 3 is a schematic diagram of the present application forming a stacked backside passivation layer;
FIG. 4 is a schematic structural view of the present application covering an organic slurry layer;
FIG. 5 is a schematic diagram of the present application after removing the conductive layer from the non-paste covered region;
FIG. 6 is a schematic diagram of the present application after removing the second oxide layer from the non-slurry covered region;
FIG. 7 is a schematic structural view of the present application after removal of the slurry layer;
fig. 8 is a schematic structural diagram of a solar cell according to the present application.
In the figure: 100-a semiconductor substrate;
200-an emitter;
300-an anti-reflective layer;
400-doped amorphous silicon layer;
500-a first oxide layer;
600-a second oxide layer;
700-a conductive layer;
800-slurry layer;
801-slurry layer coverage area;
802-non-slurry layer coverage area;
900-front passivation layer;
110-back passivation layer;
120-front electrode;
130-back electrode.
Detailed Description
For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the TOPCon cell, the back surface of the cell consists of a layer of ultrathin silicon oxide and a layer of phosphorus-doped polycrystalline silicon film, and the ultrathin silicon oxide and the phosphorus-doped polycrystalline silicon film jointly form a passivation contact structure, so that surface recombination and metal contact recombination can be effectively reduced. In a Heterojunction (HIT) cell, a layer of undoped (intrinsic) hydrogenated amorphous silicon film and a layer of doped hydrogenated amorphous silicon film with the doping type opposite to that of crystalline silicon are deposited on the crystalline silicon wafer, so that the performance of a PN junction can be improved, but the manufacturing cost of the heterojunction cell is high, and a heterojunction structure on the back side of the heterojunction cell has a serious light absorption effect.
Therefore, in order to overcome the defects of the prior art, the technical scheme of the embodiment of the invention provides a solar cell and a photovoltaic module, wherein the back surface of the cell is provided with a doped amorphous silicon layer, a first oxide layer, a second oxide layer arranged on the surface of the first oxide layer at intervals, and a conductive layer on the surface of the second oxide layer, so that the back surface passivation effect of the cell can be improved, the absorption of the back surface of the cell to light can be reduced, the energy consumption can be reduced, and the conversion efficiency of the solar cell can be improved.
An embodiment of the present application provides a method for manufacturing a solar cell, as shown in fig. 1, which is a flowchart for manufacturing a solar cell of the present application, and includes the following steps:
step S100, forming an emitter 200 on the surface of the textured semiconductor substrate 100;
step S200, forming a front passivation layer 900 on the surface of the emitter 200;
step S300, forming a back passivation layer 110 on the back surface of the semiconductor substrate 100, where the back passivation layer 110 includes an amorphous doped silicon layer 400, a first oxide layer 500, second oxide layers 600 arranged on the surface of the first oxide layer 500 at intervals, and a conductive layer 700 on the surface of the second oxide layer 600, which are sequentially disposed on the back surface of the semiconductor substrate 100;
step S400, forming a slurry layer 800 on the surface of the conductive layer 700, removing the conductive layer 700 in the non-slurry layer region 802, removing the second oxide layer 600 in the non-slurry layer region 802, and finally removing the slurry layer 800.
Step S500 is to form the back electrode 130 on the surface of the back passivation layer 110.
Step S600, forming the front electrode 120 on the surface of the front passivation layer 900.
Hereinafter, a method for manufacturing a solar cell according to the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Step S100 is to form emitter 200 on the surface of textured semiconductor substrate 100.
In some embodiments, the semiconductor substrate 100 is an N-type substrate, and the N-type substrate may be a crystalline silicon substrate (silicon substrate), such as a polysilicon substrate, a monocrystalline silicon substrate, or a quasi-monocrystalline silicon substrate, and the specific type of the semiconductor substrate 100 is not limited by the embodiments of the present invention.
In some embodiments, emitter 200 is a P-type emitter.
In this embodiment, boron diffusion is performed on the surface of the semiconductor substrate 100 to form a boron diffusion layer, thereby obtaining a P-type emitter. Boron diffusion is to form a boron diffusion layer by diffusing boron atoms through a boron source, and the boron source may be, for example, boron tribromide.
In some embodiments, the emitter 200 may be formed on the surface of the semiconductor substrate 100 by using any one or more of high temperature diffusion, slurry doping, or ion implantation.
In some embodiments, the front and back surfaces of the N-type semiconductor substrate 100 may be subjected to a texturing process to form a textured or surface-textured structure (e.g., a pyramid structure) before forming the emitter 200. The texturing process may be chemical etching, laser etching, mechanical method, plasma etching, etc., and is not limited herein. Illustratively, the front and back surfaces of the N-type semiconductor substrate 100 may be subjected to a texturing process using NaOH solution, and the etching using NaOH solution is anisotropic, so that a pyramidal textured surface may be prepared.
In this embodiment, the surface of the N-type semiconductor substrate 100 has a textured structure by texturing, so as to generate a light trapping effect, increase the amount of light absorbed by the solar cell, and improve the conversion efficiency of the solar cell.
In some embodiments, before the texturing process, a step of cleaning the semiconductor substrate 100 may be further included to remove metal and organic contaminants from the surface.
In some embodiments, the front surface of the semiconductor substrate 100 is the surface facing the sun (i.e., the light-receiving surface), and the back surface of the silicon substrate is the surface facing away from the sun (i.e., the backlight surface).
After the step S100, the method further includes removing a borosilicate glass layer (BSG) formed in a boron diffusion process on the back surface of the semiconductor substrate 100, and it is understood that the borosilicate glass layer has a metal gettering effect, which may affect the normal operation of the solar cell and needs to be removed.
In a specific embodiment, the semiconductor substrate 100 may be placed in a chain type acid cleaning apparatus with the back surface facing downward (the belt speed of the chain type apparatus is 1.0m/min to 2.0 m/min), the semiconductor substrate 100 enters an acid bath, and a borosilicate glass layer (BSG) formed by boron diffusion on the back surface is etched away, a prepared mixed acid is disposed in the acid bath, the mixed acid includes a hydrofluoric acid solution with a mass concentration of 2% to 10% and a hydrochloric acid solution with a mass concentration of 2% to 10%, the acid cleaning temperature is 15 ℃ to 25 ℃, the acid cleaning time is about 30s to 60s, the front surface of the semiconductor substrate 100 is covered with a water film, and the borosilicate glass layer (BSG) on the front surface of the semiconductor substrate 100 may also be used as a protective layer, so as to prevent the front surface of the semiconductor substrate 100 from reacting with the mixed acid in the process of removing the borosilicate glass layer (BSG).
The method comprises the following steps of (1) carrying out acid washing after acid washing, wherein the time of water washing is 10-20 s, and the temperature of water washing is 15-25 ℃; of course, the semiconductor substrate 100 may be subjected to a baking process after the water washing.
Step S200, a front passivation layer 900 is formed on the surface of the emitter 200.
In some embodiments, a passivation process is performed on the front surface of the semiconductor substrate 100 to form a front passivation layer 900 and/or an anti-reflective layer 300 (also referred to as an "anti-reflective layer") on the upper surface of the emitter 200, for example, the front passivation layer 900 may be formed, the anti-reflective layer 300 may be formed, or both the front passivation layer 900 and the anti-reflective layer 300 may be formed, as shown in fig. 2, which is a schematic structural diagram of forming the front passivation layer 900 and the anti-reflective layer 300.
In some embodiments, the specific material of the front passivation layer 900 and/or the anti-reflective layer 300 is not limited in the examples of the present application. Illustratively, an aluminum oxide/silicon nitride stack structure may be used as the front passivation layer 900, and the stack structure may also be the anti-reflective layer 300, or silicon oxynitride may be used as the front passivation layer 900 and the anti-reflective layer 300, but is not limited thereto, for example, the front passivation layer 900 may also be a stack structure formed by one or more of silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, silicon nitride layer, silicon dioxide, silicon nitride, or gallium oxide, and the anti-reflective layer 300 is a silicon nitride layer, or the like.
In the embodiment, the stack of the front passivation layer 900 and the anti-reflective layer 300 has a good passivation effect, and can improve the photoelectric conversion efficiency of the solar cell. In addition, the antireflection layer 300 is disposed to reduce the reflection of light and increase the amount of light absorbed by the solar cell, and also has a passivation effect, so as to improve the photoelectric conversion efficiency of the solar cell.
In some embodiments, the front passivation layer 900 is formed by any one of Atomic Layer Deposition (ALD) and Plasma Enhanced Chemical Vapor Deposition (PECVD), and the method for forming the front passivation layer 900 is not limited in the present invention. Accordingly, the equipment used for deposition may be ALD equipment, PECVD equipment, etc.
It should be noted that, in the embodiments of the present application, the thicknesses of the front passivation layer 900 and the antireflection layer 300 are not limited, and can be adjusted by those skilled in the art according to actual situations. Illustratively, the thickness of the front passivation layer 900 is 50nm to 120nm, for example, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, etc., and the thickness of the anti-reflective layer 300 is 40nm to 80nm, for example, 40nm, 50nm, 60nm, 70nm, 80nm, etc.
Step S300, forming a back passivation layer 110 on the back surface of the semiconductor substrate 100, where the back passivation layer 110 includes an amorphous-doped silicon layer 400, a first oxide layer 500, a second oxide layer 600, and a conductive layer 700 sequentially disposed on the back surface of the semiconductor substrate 100, and the resulting structure is as shown in fig. 3.
Specifically, step S300 includes:
step S301 is to form a doped amorphous silicon layer 400 on the back surface of the semiconductor substrate 100.
In some embodiments, an amorphous silicon layer may be formed on the back surface of the semiconductor substrate 100, and then the amorphous silicon layer may be doped to form the doped amorphous silicon layer 400; it is also possible to simultaneously perform deposition and doping on the back surface of the semiconductor substrate 100 to form the doped amorphous silicon layer 400.
In some embodiments, the amorphous silicon layer is deposited at a low temperature, and in particular, the amorphous silicon layer may be prepared by any one or more of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD), and the preparation method of the doped amorphous silicon layer 400 is not limited in the present invention. Accordingly, the apparatus used for deposition may be a CVD apparatus, a PVD apparatus, an ALD apparatus, or the like.
In some embodiments, the low-temperature deposition temperature is 100 ℃ to 300 ℃, and the low-temperature deposition temperature may be specifically 100 ℃, 110 ℃, 120 ℃, 150 ℃, 170 ℃, 200 ℃, 220 ℃, 250 ℃, 300 ℃ and the like, and the low-temperature deposition temperature is limited in the above range, so that the amorphous silicon film layer is favorably formed, and the local amorphous silicon can be crystallized, thereby improving the photoelectric property of the battery.
In some embodiments, the dopant element conductivity type of the doped amorphous silicon layer 400 is the same as the dopant element conductivity type of the semiconductor substrate 100. For example, the semiconductor substrate 100 is an N-type substrate, and the doping element is an N-type doping element, such as phosphorus or arsenic, and the formed doped amorphous silicon layer 400 may be a phosphorus-doped amorphous silicon layer or an arsenic-doped amorphous silicon layer.
In some embodiments, the thickness of the doped amorphous silicon layer 400 is 10nm to 100nm, the thickness of the doped amorphous silicon layer 400 may be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc., and the thickness of the doped amorphous silicon layer 400 greater than 100nm may affect carrier transmission, resulting in poor conductivity of the battery; the thickness of the doped amorphous silicon layer 400 is less than 10nm, the desired passivation effect may not be achieved.
In step S302, a first oxide layer 500 is formed on the surface of the doped amorphous silicon layer 400.
In some embodiments, the first oxide layer 500 is formed by oxidation or deposition, specifically, the first oxide layer 500 is deposited by at least one of Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD), and the first oxide layer 500 is oxidized by at least one of ozone oxidation, high temperature thermal oxidation, and nitric acid oxidation, and the method for forming the first oxide layer 500 is not limited in this application. The material of the first oxide layer 500 includes silicon oxide, and the material of the first oxide layer may also be at least one of silicon oxynitride and aluminum oxide. The first oxide layer 500 allows multi-photon electrons to tunnel into the doped amorphous silicon layer 400 and simultaneously blocks minority-electron hole recombination, so that electrons are laterally transmitted in the doped amorphous silicon layer 400 and collected by metal, thereby greatly reducing metal contact recombination current.
Step S303 is to form a second oxide layer 600 on the surface of the first oxide layer 500.
In some embodiments, the second oxide layer 600 is deposited, and in particular, the first oxide layer 500 is deposited by at least one of Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD). The second oxide layer 600 may also be formed by oxidation, specifically, the oxidation manner of the second oxide layer 600 includes at least one of an ozone oxidation method, a high-temperature thermal oxidation method, and a nitric acid oxidation method, and the application is not limited to the formation method of the second oxide layer 600.
In some embodiments, the material of the second oxide layer 600 includes molybdenum oxide, which is a non-toxic, high work function, and high conductivity N-type semiconductor material, and the molybdenum oxide is disposed on the back surface of the solar cell, which can effectively reduce the intrinsic electron loss between the electron donor and the electron acceptor on the interface layer of the back electrons and holes, reduce the contact recombination of the back electrons and holes, and block the electron transfer from the electron acceptor fullerene, and simultaneously improve the hole transfer rate.
Step S304 is to form a conductive layer 700 on the surface of the second oxide layer 600.
In some embodiments, the conductive layer 700 may be a transparent conductive layer (TCO). The conductive layer 700 is prepared by any one of a plasma enhanced chemical vapor deposition method (PECVD), a low pressure chemical vapor deposition method (LPCVD), a hot wire chemical vapor deposition method (HWCVD), and an atomic layer deposition method (ALD), but the method for preparing the conductive layer 700 is not limited in the present application, and of course, the conductive layer 700 may be prepared by using a silicon target, a silicon oxide target, a silicon carbide target in combination with a magnetron sputtering apparatus.
In some embodiments, the material of the conductive layer 700 may be at least one of oxide, nitride, doped oxide and mixed oxide, and specifically, the oxide may be In2O3、SnO2ZnO, CdO, the nitride can be TiN, and the doped oxide can be In2O3:Sn、ZnO:In，ZnO:Ga，ZnO:Al，SnO2:F，SnO2Ta, the mixed oxide may be In2O3-ZnO，CdIn2O4，Cd2SnO4，Zn2SnO4The conductive layer 700 serves as a carrier transport layer on the back surface of the semiconductor substrate 100, and can improve the open circuit voltage and fill factor of the battery.
In step S400, as shown in fig. 4, a slurry layer 800 having a Selective Electrode (SE) pattern is formed on the surface of the conductive layer 700.
In some embodiments, the slurry layer 800 is formed by coating a corrosion-resistant material on the surface of the conductive layer 700, and the surface of the conductive layer 700 is divided into two regions by the slurry layer 800: a slurry layer covering region 801 and a non-slurry layer covering region 802, namely the slurry layer covering region 801 is provided with a slurry layer 800, the slurry layer covering region 801 is a metal electrode contact region, and the slurry layer 800 corresponds to the position of a preset electrode; the non-slurry layer covered region 802 is the other region of the conductive layer surface except the slurry layer covered region. The present application provides for the purpose of forming a selective passivation structure in the slurry layer covered region in order to subsequently form a passivation layer in the non-slurry covered region 802 by providing a slurry layer patterned with Selective Electrodes (SE).
Step S500, removing the conductive layer 700 in the non-slurry layer coverage area 802, the structure after the removal is shown in fig. 5, removing the second oxide layer 600 in the non-slurry layer coverage area 802, the structure obtained is shown in fig. 6, and finally removing the slurry layer 800, the structure obtained is shown in fig. 7.
In some embodiments, the conductive layer 700 in the non-slurry layer covered region 802 is removed by an etching solution, specifically, the etching solution comprises HF, HF/HNO3At least one of them, when the etching solution is used for processing, since the surface of part of the conductive layer 700 (the conductive layer of the preset back electrode area) is covered with the slurry layer 800, the exposed conductive layer 700 is removed after being subjected to the acid etching solution, so as to obtain the partially arranged conductive layer structure.
In some embodiments, an acid or base solution is used to remove the second oxide layer 600 in the non-slurry covered region 802. Specifically, the acid solution comprises HF, HF/HNO3The alkaline solution comprises at least one of NaOH, KOH and tetramethyl ammonium hydroxide (TMAH). When the second oxide layer 600 of the non-slurry-layer covered region 802 is not covered by the slurry layer, an acid solution may be used alone, an alkali solution may be used alone, the second oxide layer 600 of the non-slurry-layer covered region 802 may be treated by both the acid solution and the alkali solution, when the acid solution and the alkali solution are selected, the acid solution may be treated by the acid solution first and then the alkali solution, and when the acid solution and the alkali solution are selected, the acid solution or the alkali solution may be selected to be soluble in the second oxide layer 600 but not in the first oxide layer 500, so that the second oxide layer forms a selective structure.
In some embodiments, the slurry layer is removed with an organic solution, specifically, the organic solution includes at least one of ethanol, isopropanol.
In the steps, the second oxidation layer and the conducting layer form a selective structure arranged on the surface of the first oxidation layer at intervals through chemical treatment, so that the light absorption effect of the back of the battery is reduced while the battery passivation effect is improved, and the conversion efficiency of the battery is improved.
Step S600 is to form a back electrode 130 on the surface of the back passivation layer 110, and the resulting solar cell structure is as shown in fig. 8.
In some embodiments, a metallization process is performed on the lower surface of the semiconductor substrate 100 to form the back electrode 130.
Specifically, the positions of the back electrodes 130 correspond to the positions of the conductive layers 700 one by one, and the back electrodes 130 may be prepared by a screen printing method and sintered to form ohmic contact between the back electrodes 130 and the conductive layers 700.
In the embodiment of the present application, the specific material of the back electrode 130 is not limited. Illustratively, when the back electrode 130 forms ohmic contact with the conductive layer 700, the back electrode 130 is a silver electrode.
In some embodiments, the thickness of the back passivation layer 110 is 60nm to 120nm, and may be, for example, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, and the like.
Step S700 is to form the front electrode 120 on the surface of the front passivation layer 900.
In some embodiments, a metallization process is performed on the surface of the semiconductor substrate 100 to form the front electrode 120. The front electrode 120 may be prepared by a screen printing method and sintered such that the front electrode 120 forms ohmic contact with the emitter electrode 200 through the front passivation layer 900.
In the embodiment of the present application, the specific material of the front electrode 120 is not limited. Illustratively, when the front electrode is in ohmic contact with the emitter 200, the front electrode 120 is a silver electrode or a silver/aluminum electrode, for example, a silver paste or a silver paste doped with a small amount of aluminum, i.e., a silver/aluminum paste, may be printed on the upper surface of the front passivation layer 900 corresponding to the emitter 200, and sintered, so that each paste may be fired through the front passivation layer 900.
It should be noted that the thickness of the front passivation layer 900 is not limited in the embodiments of the present application, and can be adjusted by those skilled in the art according to actual situations. Illustratively, the thickness of the front passivation layer 900 may be 5nm to 30nm, and the thickness of the front passivation layer 900 may be specifically 5nm, 6nm, 7nm, 8nm, 10nm, 15nm, 18nm, 20nm, 23nm, 26nm, 28nm, 30nm, and the like.
In the present application, unless otherwise stated, the individual operation steps may or may not be performed in sequence. The step sequence for preparing the solar cell is not limited in the embodiment of the application, and can be adjusted according to the actual production process.
The embodiment of the application also provides a solar cell which can be prepared by adopting the preparation method of the solar cell.
The solar cell provided in the embodiment of the present application and the method for manufacturing the solar cell are based on the same inventive concept, and therefore, at least all the features and advantages of the method for manufacturing the solar cell described above are provided, and no further description is provided herein.
Specifically, the present application relates to a solar cell comprising:
a semiconductor substrate 100, the semiconductor substrate 100 including a front surface and a back surface oppositely disposed;
an emitter 200, a front passivation layer 900 and/or an anti-reflective layer 300 sequentially positioned on the front surface of the semiconductor substrate 100;
the back passivation layer 110 is located on the back surface of the semiconductor substrate 100, and the back passivation layer 110 includes a doped amorphous silicon layer 400, a first oxide layer 500, a second oxide layer 600 disposed on the surface of the first oxide layer 500 and spaced apart from the first oxide layer, and a conductive layer 700 on the surface of the second oxide layer 600, where the doped element in the doped amorphous silicon layer 400 has the same conductivity type as the doped element in the semiconductor substrate 100;
a front electrode 120 in contact with the emitter 200 and a back electrode 130 in contact with the conductive layer 700.
In the above technical solution, in the solar cell of the present application, the passivation performance and contact can be improved by sequentially forming the stacked passivation contact structure of the doped amorphous silicon layer 400, the first oxide layer 500, the second oxide layer 600 and the conductive layer 700 on the back surface of the semiconductor substrate 100; in addition, the second oxide layer 600 and the conductive layer 700 are arranged on the surface of the first oxide layer 500 at intervals, so that the light absorption effect of the back surface of the semiconductor substrate 100 is reduced while good contact of the back surface of the semiconductor substrate 100 is ensured, the short-circuit current of the cell can be effectively improved, and the conversion efficiency of the solar cell is further improved.
In some embodiments, the front surface of the semiconductor substrate 100 is the surface facing the sun (i.e., the light-receiving surface), and the back surface of the silicon substrate is the surface facing away from the sun (i.e., the backlight surface).
In some embodiments, the material of the first oxide layer 500 includes at least one of silicon oxide, silicon oxynitride, and aluminum oxide. The first oxide layer 500 can prevent minority carriers and holes from being recombined while allowing the majority carriers to tunnel into the doped amorphous silicon layer 400, so that electrons are laterally transported in the doped amorphous silicon layer 400 and collected by metal, thereby greatly reducing metal contact recombination current.
In some embodiments, the material of the second oxide layer 600 includes molybdenum oxide, which is a non-toxic, high work function, and high conductivity N-type semiconductor material, and the molybdenum oxide is disposed on the back surface of the solar cell, which can effectively reduce the intrinsic electron loss between the electron donor and the electron acceptor on the interface layer of the back electrons and holes, reduce the contact recombination of the back electrons and holes, and block the electron transfer from the electron acceptor fullerene, and simultaneously improve the hole transfer rate.
In some embodiments, the distance between adjacent second oxide layers 600 is 1mm to 2mm, the distance between adjacent second oxide layers 600 is 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm, 1.9mm, 2mm, etc., and the distance between adjacent second oxide layers 600 is set within the above range, which is beneficial to ensuring the transmission of carriers in the metal region, and ensuring the light absorption in the non-metal region while reducing the metal contact.
In some embodiments, the contact area of the second oxide layer 600 and the first oxide layer 500 is denoted as S1, the surface area of the first oxide layer 500 in contact with the doped amorphous silicon layer 400 is denoted as S2, and S1/S2 is 0.02 to 0.04, for example, 0.02, 0.03, and 0.04, and the like.
In some embodiments, as shown in fig. 7, since the first oxide layer 500 completely covers the semiconductor substrate 100 and the conductive layer 700 partially covers the semiconductor substrate 100, the surface area S2 of the first oxide layer 500 contacting the doped amorphous silicon layer 400 can be determined by calculating the surface area of the semiconductor substrate 100, and the contact area S1 of the second oxide layer 600 and the first oxide layer 500 can be determined by testing the area of the conductive layer 700.
In some embodiments, the thickness of the first oxide layer 500 is 1nm to 5nm, and the thickness of the first oxide layer 500 may be 1nm, 2nm, 3nm, 4nm, 5nm, and the like, and the thickness of the first oxide layer 500 is limited, so that passivation of the oxide layer on the battery is ensured, and meanwhile, transmission of carriers is not hindered, and the first oxide layer serves as a passivation protection layer, so that passivation performance of the whole battery can be improved.
In some embodiments, the thickness of the second oxide layer 600 is 1nm to 50nm, and the thickness of the second oxide layer 600 may be 1nm, 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, and the like, and the thickness of the second oxide layer 600 is limited to be beneficial for obtaining superior passivation and transmission performance, and preferably, the thickness of the second oxide layer 600 is 15nm to 40 nm. The second oxide layer 600 serves as a passivation contact structure, which can improve a passivation effect and improve the conversion efficiency of the battery.
The thickness ratio of the first oxide layer 500 to the second oxide layer 600 is 1 (1-50), and the thickness ratio of the first oxide layer 500 to the second oxide layer 600 may be, for example, 1: 1. 1: 5. 1: 10. 1: 20. 1: 30. 1: 40 and 1: 50, it can be understood that the thickness of the first oxide layer 500 may be the same as that of the second oxide layer 600, and the thickness of the first oxide layer 500 may also be different from that of the second oxide layer 600, and preferably, the thickness of the second oxide layer 600 is greater than that of the first oxide layer 500, so as to further improve the passivation effect on the back surface of the cell and improve the performance of the solar cell. The ratio of the thicknesses of the first oxide layer 500 and the second oxide layer 600 is less than 1: 1, the passivation performance and carrier transport of the battery are deteriorated, if the ratio of the thicknesses of the first oxide layer 500 and the second oxide layer 600 is greater than 1: 50, the second oxide layer 600 is too thick, resulting in severe light absorption at the back surface and also reduced back surface conductivity.
In some embodiments, the thickness of the back passivation layer 110 is 60nm to 120nm, and the thickness may be, for example, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, and the like.
In some embodiments, the semiconductor substrate 100 is an N-type substrate.
In some embodiments, the doped amorphous silicon layer 400 includes a phosphorus doped amorphous silicon layer or an arsenic doped amorphous silicon layer.
In some embodiments, the phosphorus doped amorphous silicon layer has a doping concentration of 9E19cm-3～1E21cm-3The doping concentration of the phosphorus-doped amorphous silicon layer may be 9E19cm-3、1E20cm-3、3E20 cm-3、5E20cm-3And 1E21cm-3And the doping concentration of the arsenic-doped amorphous silicon layer is 9E19cm-3～1E21cm-3The doping concentration of the As-doped amorphous silicon layer may be 9E19cm-3、1E20cm-3、3E20 cm-3、5E20cm-3And 1E21cm-3And the doping concentration of the phosphorus-doped amorphous silicon layer or the arsenic-doped amorphous silicon layer is controlled within the range, so that the excellent passivation performance of the battery is ensured, and the conductivity is improved.
In some embodiments, the thickness of the doped amorphous silicon layer 400 is 10nm to 100nm, and the thickness of the doped amorphous silicon layer 400 may be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or the like, and the thickness of the doped amorphous silicon layer 400 is controlled within the above range, which is beneficial to improving conductivity while ensuring passivation performance of the film layer.
In some embodiments, the sheet resistance of the doped amorphous silicon layer 400 may be 30 Ω/sqr, 40 Ω/sqr, 50 Ω/sqr, 60 Ω/sqr, 70 Ω/sqr, 80 Ω/sqr, 90 Ω/sqr, 100 Ω/sqr, 110 Ω/sqr, 120 Ω/sqr, 130 Ω/sqr, 140 Ω/sqr, 150 Ω/sqr, etc.
The sheet resistance or diffusion concentration of the doped amorphous silicon layer 400 is limited in the above range, which is helpful for ensuring the passivation performance and conductivity of the cell, thereby improving the photoelectric conversion efficiency of the solar cell and the performance of the solar cell.
In some embodiments, the upper surface of the emitter 200 is provided with a front passivation layer 900 and/or an anti-reflection layer 300 (also referred to as an "anti-reflection layer"), for example, the front passivation layer 900 may be formed, the anti-reflection layer 300 may be formed, or both the front passivation layer 900 and the anti-reflection layer 300 may be formed.
The embodiment of the application further provides a photovoltaic module, which comprises a cover plate, a packaging material layer and a solar cell string which are sequentially stacked, wherein the parts form a stacked structure, and the stacked structure is subjected to lamination processing to obtain the photovoltaic module.
In some embodiments, the solar cell string includes a plurality of solar cells connected by conductive tape, and the connection manner between the solar cells may be partial lamination or splicing.
In some embodiments, the cover plate may be a transparent or opaque cover plate, such as a glass cover plate, a plastic cover plate. The two sides of the packaging material layer are respectively contacted and attached with the cover plate and the battery string.
In some embodiments, the material of the encapsulant layer may be an ethylene-vinyl acetate (EVA) adhesive film, a polyethylene octene co-elastomer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.
The photovoltaic module can also adopt side edge full-surrounding type encapsulation, namely, the side edge of the photovoltaic module is completely encapsulated and encapsulated by the encapsulation adhesive tape so as to prevent the photovoltaic module from generating lamination deviation in the lamination process.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Although the present application has been described with reference to preferred embodiments, it is not intended to limit the scope of the claims, and many possible variations and modifications may be made by one skilled in the art without departing from the spirit of the application.

Claims (10)

1. A solar cell, comprising:
the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged;
the emitter, the front passivation layer and/or the antireflection layer are/is sequentially positioned on the front surface of the semiconductor substrate;
the back passivation layer is positioned on the back surface of the semiconductor substrate and comprises a doped amorphous silicon layer, a first oxidation layer, a second oxidation layer and a conducting layer, wherein the doped amorphous silicon layer, the first oxidation layer, the second oxidation layer and the conducting layer are sequentially arranged on the back surface of the semiconductor substrate, the second oxidation layer is arranged on the surface of the first oxidation layer and is arranged at intervals, and the conducting type of a doped element in the doped amorphous silicon layer is the same as that of a doped element in the semiconductor substrate;
a front electrode in contact with the emitter and a back electrode in contact with the conductive layer.
2. The battery of claim 1, wherein the material of the first oxide layer comprises at least one of silicon oxynitride, aluminum oxide.
3. The battery of claim 1, wherein the material of the second oxide layer comprises molybdenum oxide.
4. The battery according to claim 1, wherein a distance between adjacent second oxide layers is 1mm to 2 mm.
5. The battery of claim 1, wherein the contact area of the second oxide layer and the first oxide layer is represented as S1, the surface area of the first oxide layer in contact with the doped amorphous silicon layer is represented as S2, and S1/S2 is 0.02-0.04.
6. The battery of claim 1, wherein the first oxide layer has a thickness of 1nm to 5nm and/or the second oxide layer has a thickness of 1nm to 50 nm; and/or the thickness ratio of the first oxide layer to the second oxide layer is 1 (1-50).
7. The cell of claim 1, wherein the semiconductor substrate is an N-type substrate and the doped amorphous silicon layer is a phosphorus doped amorphous silicon layer or an arsenic doped amorphous silicon layer.
8. The cell of claim 7, wherein the phosphorus doped amorphous silicon layer has a doping concentration of 9E19cm-3～1E21cm-3Or arsenic doped amorphous silicon layer with a doping concentration of 9E19cm-3～1E21cm-3。
9. The cell of claim 1, wherein the doped amorphous silicon layer has a thickness of 10nm to 100 nm; and/or the thickness of the back passivation layer is 60 nm-120 nm.
10. A photovoltaic module comprising a plurality of strings of solar cells, each string of solar cells being formed by electrically connecting solar cells according to any one of claims 1 to 9.
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