CN115513307A - Back contact solar cell and preparation method thereof - Google Patents
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- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H01L31/02—Details
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- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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Abstract
The invention discloses a back contact solar cell and a preparation method thereof, wherein the back contact solar cell comprises: a semiconductor substrate having opposing first and second surfaces, the first surface comprising a plurality of first regions, second regions, and alternating stacked regions; a tunneling oxide layer and a P-type doped crystalline silicon layer; a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer; an isolation structure including an isolation layer and an isolation trench. According to the hybrid back contact battery technology, the selective passivation contact technology at different temperatures is combined with the IBC structure, so that the problem that the n region is easily damaged due to the narrow process window of the n region of the HBC structure and the problems of high manufacturing process cost and complex preparation process of the traditional HBC battery are solved, and the process difficulty and the manufacturing cost are reduced.
Description
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to a back contact solar cell and a preparation method thereof.
Background
In recent years, with the continuous development of photovoltaic related technologies, the mass production efficiency of crystalline silicon cells of various manufacturers is also continuously improved. The IBC cell technology, as a crystal silicon cell technology with the longest history, is compatible and storable in that it continuously absorbs the process advantages and passivation technologies of other crystal silicon technology routes, in addition to the cell structure with the highest conversion efficiency potential, to continuously improve the conversion efficiency. IBC absorbs the advantages of PERC technology in the development stage, and the conversion efficiency is improved to 24-25%; absorbing TOPCON passivation Contact technology, and transforming into TBC (Tunnel oxide Back Contact) battery, the conversion efficiency can reach 25% -26%; the amorphous silicon passivation technology for absorbing HJT is developed into an HBC (Hetero-Junction Back Contact) battery, the conversion efficiency can reach 26% -27%, but the IBC battery technology is always limited by high volume production cost and is more tortuous in development.
Compared with the IBC battery, the HBC battery adopts a-Si: H as a double-sided passivation layer, has excellent passivation effect and can obtain higher open-circuit voltage. In the process of growing PN junctions, the PN junctions are doped by adopting a region type mask, so that the recombination loss of carriers is reduced. The logic of the evolution of the high-efficiency crystalline silicon battery technology is as follows: and the composition of battery carriers is reduced by using a lower-cost large-scale process means, so that the open-circuit voltage and the conversion efficiency are improved.
According to the traditional HBC cell structure, i/na-Si: H and i/pa-Si: H are respectively adopted for the n area and the p area on the back surface to form an interdigital pattern, damage of laser to the n area and the p area needs to be strictly controlled in the manufacturing process, particularly, the process window of the laser is narrow for the n area, and the process difficulty is increased. HBC cells also suffer from the following drawbacks in terms of manufacturing flow: a great amount of masks and mask removing technologies are used for forming patterning, such as a common photoetching technology in the field of semiconductors, so that the production cost is high, and the difficulty in process control is high; in the intrinsic and doped amorphous silicon coating operation process, the requirement on process cleanliness is extremely high due to the narrow process window; the negative side of the amorphous silicon in the battery can cause serious parasitic absorption, and in addition, the negative textured structure in the process needs smoother pyramids to ensure good amorphous silicon passivation, so that the increase of negative reflectivity is caused to influence the photoelectric conversion efficiency; in the aspect of equipment fixed investment, the CVD equipment for depositing the amorphous silicon film has high cost and low productivity. These aspects restrict the efficiency improvement and cost reduction of the HBC cell, limiting its industrial application.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the present invention is directed to a back contact solar cell and a method for manufacturing the same. According to the hybrid back contact battery technology, the selective passivation contact technology at different temperatures is combined with the IBC structure, so that the problem that the n region is easily damaged due to the narrow process window of the n region of the HBC structure and the problems of high manufacturing process cost and complex preparation process of the traditional HBC battery are solved, and the process difficulty and the manufacturing cost are reduced.
In one aspect of the invention, a back contact solar cell is provided. According to an embodiment of the present invention, the back contact solar cell includes:
a semiconductor substrate including opposing first and second surfaces, the first surface including a first region, a second region, and an interleaved stack region between the first and second regions, a distance between the first region and a centerline of the semiconductor substrate in a width direction being greater than a distance between the second region and the centerline of the semiconductor substrate in the width direction, and a distance between the interleaved stack region and the centerline of the semiconductor substrate in the width direction being equal to a distance between the first region and the centerline of the semiconductor substrate in the width direction;
a first tunneling oxide layer and a first P-type doped crystalline silicon layer, wherein the first tunneling oxide layer is on the first area, and the first P-type doped crystalline silicon layer is on a surface of the first tunneling oxide layer away from the semiconductor substrate;
a first sub intrinsic amorphous silicon layer and a first N type doped amorphous silicon layer, wherein the conductivity type of the first P type doped amorphous silicon layer is opposite to that of the first N type doped amorphous silicon layer, the first sub intrinsic amorphous silicon layer is on the second region, and the first N type doped amorphous silicon layer is on the surface of the first sub intrinsic amorphous silicon layer far away from the semiconductor substrate;
the staggered and superposed layer comprises a second tunneling oxide layer, a second P-type doped crystalline silicon layer, a second sub-intrinsic amorphous silicon layer and a second N-type doped amorphous silicon layer which are sequentially arranged in the staggered and superposed area, and the conductivity types of the second P-type doped crystalline silicon layer and the second N-type doped amorphous silicon layer are opposite;
and the isolation structure comprises an isolation layer and an isolation groove, the isolation layer is arranged between the second sub intrinsic amorphous silicon layer and the second P-type doped crystalline silicon layer, and the isolation groove penetrates through the second N-type doped amorphous silicon layer and the second sub intrinsic amorphous silicon layer.
According to the back contact solar cell provided by the embodiment of the invention, compared with an HBC cell structure in the prior art, the passivation contact of the tunneling oxide layer and the P-poly-Si layer is adopted to replace the passivation of an intrinsic a-Si: H + a-Si: H (P) film layer in the conventional HBC cell structure, and the tunneling oxide layer and the P-poly-Si layer have relatively small sensitivity to laser thermal damage, so that the influence on the passivation effect of a P region can be reduced in the laser film opening process, the process window is further increased, and the process difficulty is reduced. Compared with the TBC cell structure in the prior art, the intrinsic amorphous silicon layer i-a-Si + N-a-Si layer passivation contact is adopted to replace SiOx + N-poly-Si in the existing TBC cell structure, so that the problem of serious concentric circles of silicon wafers caused by high-temperature preparation of p poly and N poly in the TBC cell is solved, the surface passivation effect of an N region is improved, and the electrical property of the solar cell is improved. Therefore, the back contact solar cell not only increases the preparation process window of the back contact solar cell, reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, the open-circuit voltage Uoc, the short-circuit current Isc and the filling factor FF of the solar cell can reach the level equivalent to the structure of the conventional HBC cell. In addition, the BSG (borosilicate glass) layer is adopted to replace the SiNx mask layer, so that the film coating process required by the SiNx mask layer is reduced, and the manufacturing cost of the battery is reduced on the whole.
In addition, the back contact solar cell according to the above embodiment of the present invention may further have the following additional technical features:
in some embodiments of the invention, the second region is a textured structure; and/or the first area is of a suede structure; and/or the second surface is of a textured structure.
In some embodiments of the invention, the back contact solar cell further comprises: the first electrode layer is arranged on one side of the isolation groove, the first electrode layer covers the first N-type doped amorphous silicon layer and part of the second N-type doped amorphous silicon layer, the second electrode layer is arranged on the other side of the isolation groove, and the second electrode layer covers part of the second N-type doped amorphous silicon layer and the first P-type doped crystalline silicon layer.
In some embodiments of the present invention, the first electrode layer and the second electrode layer are transparent conductive layers, and the materials of the first electrode layer and the second electrode layer are each independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide and indium tungsten oxide.
In some embodiments of the present invention, the isolation layer includes a BSG layer between the second sub-intrinsic amorphous silicon layer and the second P-type doped crystalline silicon layer.
In some embodiments of the present invention, the thickness of the BSG layer is 80 to 120nm.
In some embodiments of the present invention, the semiconductor substrate further comprises a passivation layer comprising a third intrinsic amorphous silicon layer on the second surface and a silicon nitride passivation layer on a surface of the third intrinsic amorphous silicon layer remote from the semiconductor substrate.
In some embodiments of the inventionIn an embodiment, the first tunneling oxide layer and the second tunneling oxide layer are both tunneling SiO 2 A layer; and/or the thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are both 1.2-1.8 nm; and/or the thicknesses of the first P-type doped crystalline silicon layer and the second P-type doped crystalline silicon layer are both 80-200 nm; and/or the diffusion sheet resistances of the first P-type doped crystalline silicon layer and the second P-type doped crystalline silicon layer are both 80-120 omega/sq; and/or the thicknesses of the first sub-intrinsic amorphous silicon layer and the second sub-intrinsic amorphous silicon layer are both 5-30 nm; and/or the thicknesses of the first N-type doped amorphous silicon layer and the second N-type doped amorphous silicon layer are both 10-30 nm; and/or the element doping concentration in the first N-type doped amorphous silicon layer and the second N-type doped amorphous silicon layer is 10e20cm -3 ～10e21cm -3 。
In yet another aspect of the invention, a method of fabricating a back contact solar cell is presented. According to an embodiment of the invention, the method comprises:
providing a semiconductor substrate having opposing first and second surfaces, the first surface comprising a first region, a second region, and an interleaved stack region between the first and second regions;
sequentially forming a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer on the first surface;
opening the film of the second area by laser to expose part of the second area;
sequentially forming a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on the surface of the prepared intermediate piece far away from the second surface;
removing the first intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer and the isolation layer corresponding to the surface of the first region;
and etching the staggered and superposed regions to ensure that at least part of the N-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the staggered and superposed regions are etched through to form an isolation groove.
According to the method provided by the embodiment of the invention, compared with the preparation process of the HBC battery in the prior art, the method adopts the passivating contact of the tunneling oxide layer and the P-poly-Si layer to replace the passivation of the intrinsic a-Si: H + a-Si: H (P) film layer in the existing HBC battery structure, and as the tunneling oxide layer and the P-poly-Si layer have relatively low sensitivity to laser thermal damage, the influence on the P region passivation effect can be reduced in the laser film opening process, the process window is further enlarged, and the process difficulty is reduced. Compared with the preparation process of the TBC cell in the prior art, the method adopts the passivation contact of the intrinsic amorphous silicon layer i-a-Si + N-a-Si layer to replace SiOx + N-poly-Si in the existing TBC cell structure, thereby avoiding the serious problem of silicon wafer concentric circles caused by the high-temperature preparation of p poly and N poly in the TBC cell, improving the surface passivation effect of the N region and improving the electrical property of the solar cell. Meanwhile, the method adopts the BSG layer to replace the SiNx mask layer, reduces the film coating process required by the preparation of the SiNx mask layer, has simple process and integrally reduces the manufacturing cost of the battery; compared with the SiNx mask layer, the BSG layer has higher density, is higher in stability during P3 etching, and is not easy to fall off. In addition, the method combines the texturing process with local etching, thereby saving the previous texturing process.
In some embodiments of the invention, the method further comprises: and performing alkali texturing on the semiconductor substrate after the second area is exposed so as to form a pyramid-like textured structure on the second surface and the second area.
In some embodiments of the present invention, after forming the pyramid-like textured structure on the second surface and the second region, a third intrinsic amorphous silicon layer and a silicon nitride passivation layer are sequentially formed on the second surface.
In some embodiments of the present invention, after the etching of the staggered overlapping area, both sides of the isolation trench of the staggered overlapping area are divided into a first staggered overlapping area and a second staggered overlapping area.
In some embodiments of the present invention, a first electrode layer is formed on one side of the isolation trench, and the first electrode layer covers the N-type doped amorphous silicon layer of the second region and the N-type doped amorphous silicon layer of the staggered overlapping region, respectively, and a second electrode layer is formed on the other side of the isolation trench, and the second electrode layer covers the N-type doped amorphous silicon layer of the staggered overlapping region and the P-type doped crystalline silicon layer of the staggered overlapping region.
In some embodiments of the present invention, a first gate line is formed on a portion of a surface of the first electrode layer, and a second gate line is formed on a portion of a surface of the second electrode layer.
In some embodiments of the present invention, LPCVD is used to deposit the tunneling oxide layer and the P-type doped crystalline silicon layer.
In some embodiments of the invention, the isolation layer comprises BSG.
In some embodiments of the present invention, a tunneling oxide layer, a P-type doped crystalline silicon layer, and an isolation layer are sequentially formed on the first surface; the method comprises the following steps:
depositing a polycrystalline silicon layer after the tunneling oxide layer is formed;
performing boron diffusion on the polycrystalline silicon layer at high temperature to convert the polycrystalline silicon layer into the P-type doped crystalline silicon layer;
and prolonging the preset annealing time to form the BSG layer.
In some embodiments of the invention, the temperature for boron diffusion on the polysilicon layer is 980-1050 ℃; and/or
The predetermined annealing time is 40 +/-5 min.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of a back contact solar cell according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an intermediate member in a process of manufacturing a back contact solar cell according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an intermediate member in a process of manufacturing a back contact solar cell according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an intermediate member in a process of manufacturing a back contact solar cell according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an intermediate component in a process for manufacturing a back contact solar cell according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an intermediate member in a process of manufacturing a back contact solar cell according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of an intermediate member in a process of manufacturing a back contact solar cell according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of an intermediate component in a process for manufacturing a back contact solar cell according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an intermediate member in a process of manufacturing a back contact solar cell according to an embodiment of the present invention.
The attached drawings are marked as follows:
1-silicon nitride passivation layer, 2-third intrinsic amorphous silicon layer, 3-semiconductor substrate, 3-1-first surface, 3-2-second surface, 4-tunneling oxide layer, 4-1-first tunneling oxide layer, 4-2-second tunneling oxide layer, 5-P-type doped crystalline silicon layer, 5-1-first P-type doped crystalline silicon layer, 5-2-second P-type doped crystalline silicon layer, 6-second electrode layer, 7-second gate line, 8-first intrinsic amorphous silicon layer, 8-1-first sub-intrinsic amorphous silicon layer, 8-2-second sub-intrinsic amorphous silicon layer, 9-N-type doped amorphous silicon layer, 9-1-first N-type doped amorphous silicon layer, 9-2-second N-type doped amorphous silicon layer, 10-first gate line, 11-isolation layer, 12-isolation trench, 13-first electrode layer, B-first region, C-second region, a-staggered overlapping region, A1-first overlapping region, A2-staggered overlapping region.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In one aspect of the invention, a back contact solar cell is presented. According to an embodiment of the present invention, referring to fig. 1, a back contact solar cell includes: a semiconductor substrate 3, the semiconductor substrate 3 including a first surface 3-1 and a second surface 3-2 opposite to each other, the first surface 3-1 including a first region (B region), a second region (C region), and a staggered overlap region (a region) between the first region (B region) and the second region (C region), a distance between the first region (B region) and a center line of the semiconductor substrate 3 in the width direction is greater than a distance between the second region (C region) and a center line of the semiconductor substrate 3 in the width direction, and a distance between the staggered overlap region (a region) and a center line of the semiconductor substrate 3 in the width direction is equal to a distance between the first region (B region) and a center line of the semiconductor substrate 3 in the width direction; a first tunneling oxide layer 4-1 and a first P-type doped crystalline silicon layer 5-1, where the first tunneling oxide layer 4-1 is on the first area (area B), and the first P-type doped crystalline silicon layer 5-1 is on the surface of the first tunneling oxide layer 4-1 away from the semiconductor substrate 3; a first sub intrinsic amorphous silicon layer 8-1 and a first N type doped amorphous silicon layer 9-1, the first P type doped amorphous silicon layer 5-1 and the first N type doped amorphous silicon layer 9-1 have opposite conductivity types, the first sub intrinsic amorphous silicon layer 8-1 is on the second region (region C), the first N type doped amorphous silicon layer 9-1 is on the surface of the first sub intrinsic amorphous silicon layer 8-1 far away from the semiconductor substrate 3; the staggered superposed layer comprises a second tunneling oxide layer 4-2, a second P-type doped crystalline silicon layer 5-2, a second sub intrinsic amorphous silicon layer 8-2 and a second N-type doped amorphous silicon layer 9-2 which are sequentially arranged in a staggered superposed area (area A), and the conductivity types of the second P-type doped crystalline silicon layer 5-2 and the second N-type doped amorphous silicon layer 9-2 are opposite; and the isolation structure comprises an isolation layer and an isolation groove, the isolation layer is arranged between the second sub intrinsic amorphous silicon layer 8-2 and the second P-type doped crystalline silicon layer 5-2, and the isolation groove penetrates through the second N-type doped amorphous silicon layer 9-2 and the second sub intrinsic amorphous silicon layer 8-2. Therefore, compared with the HBC battery structure in the prior art, the HBC battery structure adopts the tunneling oxide layer + P-poly-Si layer passivation contact to replace the intrinsic a-Si: H + a-Si: H (P) film layer passivation in the prior HBC battery structure, and because the tunneling oxide layer + P-poly-Si layer has relatively low sensitivity to laser thermal damage, the influence on the P region passivation effect can be reduced in the laser film opening process, the process window is further enlarged, and the process difficulty is reduced. Compared with the TBC cell structure in the prior art, the intrinsic amorphous silicon layer i-a-Si + N-a-Si layer passivation contact is adopted to replace SiOx + N-poly-Si in the existing TBC cell structure, so that the problem of serious concentric circles of a silicon wafer caused by high-temperature preparation of p poly and N poly in the TBC cell is solved, the surface passivation effect of an N region is improved, and the electrical property of the solar cell is improved. Therefore, the back contact solar cell not only increases the preparation process window of the back contact solar cell, reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, the open-circuit voltage Uoc, the short-circuit current Isc and the filling factor FF of the solar cell can reach the level equivalent to the structure of the conventional HBC cell.
In the embodiment of the present invention, the distance between the first region (B region) and the center line of the semiconductor substrate 3 in the width direction is larger than the distance between the second region and the center line of the semiconductor substrate 3 in the width direction, and the distance between the staggered overlapping region and the center line of the semiconductor substrate 3 in the width direction is equal to the distance between the first region (B region) and the center line of the semiconductor substrate 3 in the width direction, which is formed because: in the preparation process of the back contact solar cell, the second region (C region) is subjected to etching texturing, so that the recess of the second region (C region) is formed, and therefore the boundary region of the second region (C region) and the staggered overlapping region is discontinuous, for example, the second region (C region) and the staggered overlapping region are staggered up and down, and the first region (B region) and the staggered overlapping region are continuous.
In some examples, the second region (region C) interfaces diagonally with the interface of the staggered overlap region. It should be noted that the back contact solar cell includes a plurality of first regions (B regions), alternately stacked regions, and a plurality of second regions (C regions), which are alternately arranged on the first surface 3-1, and only one first region (B region) (B regions), alternately stacked regions, and one second region (C regions) are schematically illustrated in fig. 1.
In an embodiment of the present invention, the material of the semiconductor substrate 3 may be silicon (Si) or germanium (Ge), or gallium arsenide (GaAs). It should be noted that the first surface 3-1 of the semiconductor substrate 3 is referred to as a backlight surface, and the second surface 3-2 of the semiconductor substrate 3 is referred to as a light-facing surface.
In an embodiment of the invention, specific types of the first tunnel oxide layer and the second tunnel oxide layer are not particularly limited, and as a specific example, the first tunnel oxide layer and the second tunnel oxide layer are both tunnel SiO layers 2 And (3) a layer. According to some embodiments of the present invention, the thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are both 1.2 to 1.8nm, so that a better surface passivation effect can be further ensured, and a multi-photon tunneling effect can be simultaneously ensured.
According to some embodiments of the present invention, the thicknesses of the first P-type doped crystalline silicon layer 5-1 and the second P-type doped crystalline silicon layer 5-2 are both 80-200 nm, so that the poly thickness is reduced as much as possible and the parasitic absorption is reduced while the better field passivation effect is ensured.
According to some further embodiments of the present invention, the diffusion sheet resistances of the doped crystalline silicon layers of the first P-type doped crystalline silicon layer 5-1 and the second P-type doped crystalline silicon layer 5-2 are both 80 to 120 Ω/sq, thereby ensuring a better field passivation effect and improving the contact performance between the subsequent metal paste and poly.
According to further embodiments of the present invention, the first sub-intrinsic amorphous silicon layer 8-1 and the second sub-intrinsic amorphous silicon layer 8-2 each have a thickness of 5 to 30nm, thereby having a good passivation effect on the silicon substrate surface.
According to still other embodiments of the present invention, the first and second N-doped amorphous silicon layers 9-1 and 9-2 are each 10-30 nm thick, thereby facilitating the matching of the subsequent laser and cleaning steps.
According to still other embodiments of the present invention, the doping concentrations of the elements in the first N-type doped amorphous silicon layer 9-1 and the second N-type doped amorphous silicon layer 9-2 are 10e20cm -3 ～10e21cm -3 Therefore, the passivation effect is considered, and meanwhile, the contact performance is better.
According to further embodiments of the present invention, the isolation layer includes a BSG layer between the second sub-intrinsic amorphous silicon layer 8-2 and the second P-type doped crystalline silicon layer. The BSG layer is a borosilicate glass layer, and the composition of the BSG layer is boron-doped silicon oxide. The BSG layer is used as a laser energy absorption layer and a mask layer, has the effect of reducing the influence of a laser film opening process on the passivation effect of a P area, also has the effect of providing a hydrogen source to further passivate polycrystalline silicon and a matrix, improves the passivation effect, protects the P type doped crystalline silicon layer from being subjected to alkali corrosion in a texturing process, and can simplify the process steps and avoid repeated masking in the operation process compared with a SiNx layer. The isolation trench may or may not penetrate through the BSG layer.
According to some embodiments of the present invention, the thickness of the BSG layer is 80 to 120nm, thereby further ensuring the effect of the BSG layer as a laser energy absorption layer and a mask layer.
Further, referring to fig. 1, the back contact solar cell further includes: the first electrode layer 13 is arranged on one side of the isolation groove, the first electrode layer 13 covers the first N-type doped amorphous silicon layer, the second electrode layer 6 is arranged on the other side of the isolation groove, and the second electrode layer 6 covers the second N-type doped amorphous silicon layer 9-2 and the first P-type doped crystalline silicon layer 5-1 in a covering mode. The first electrode layer 13 serves to enhance the conductivity between the N-doped amorphous silicon layer and the first gate line, and the second electrode layer 6 serves to enhance the conductivity between the P-doped amorphous silicon layer and the second gate line.
In an embodiment of the invention, the first electrode layer 13 and the second electrode layer 6 are transparent conductive layers. Specific materials of the above-described first electrode layer 13 and second electrode layer 6 are not particularly limited, and as some specific examples, the materials of the first electrode layer 13 and second electrode layer 6 are each independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydrogen oxide, and indium tungsten oxide. In some examples, the thickness of the first electrode layer 13 and the second electrode layer 6 may each independently be 60 to 100nm.
Further, referring to fig. 1, the back contact solar cell further includes: and the passivation layer comprises a third intrinsic amorphous silicon layer 2 and a silicon nitride passivation layer 1, wherein the third intrinsic amorphous silicon layer 2 is arranged on the second surface, and the silicon nitride passivation layer 1 is arranged on the surface of the third intrinsic amorphous silicon layer 2 far away from the semiconductor substrate. The silicon nitride passivation layer 11 functions as an antireflection film and a protective film, and also functions as a passivation film for suppressing recombination of photo carriers. The third intrinsic amorphous silicon layer 2 has a function of suppressing photo-carrier recombination at the junction interface with the second surface 3-2. In some examples, at least a portion of the second surface 3-2 is provided with a textured structure, i.e., at least a portion of the second surface 3-2 is provided with a plurality of types of pyramids, thereby increasing the light receiving surface of the second surface 3-2. In still other examples, the first region is a textured structure; and/or the second area is of a suede structure, and the suede structures on the first area and the second area are formed in a cleaning step in the preparation process of the back contact solar cell.
In yet another aspect of the invention, a method of fabricating a back contact solar cell is presented. According to an embodiment of the invention, the method comprises:
s100: providing a semiconductor substrate
In this step, a semiconductor substrate 3 is provided, which may be an N-type substrate or a P-type substrate, and the semiconductor substrate 3 has a first surface 3-1 and a second surface 3-2 opposite to each other, as shown in fig. 2. The first surface 3-1 of the semiconductor substrate 3 refers to a backlight surface, and the second surface 3-2 of the semiconductor substrate 3 refers to a light-facing surface. The first surface includes a first region, a second region, and an interleaved stack region between the first region and the second region.
In an embodiment of the present invention, the material of the semiconductor substrate 3 may be silicon (Si) or germanium (Ge), or gallium arsenide (GaAs).
In order to ensure the cleanliness of the semiconductor substrate 3 and remove the cutting damage layer of the silicon wafer, the bare silicon wafer can be put into a groove type polishing and cleaning machine to carry out the polishing process, in some examples, the cleaning solution is 5.5-6.5% KOH solution by mass concentration, the temperature of the solution during cleaning is 81-87 ℃, the cleaning time is 290-310s, a square block with the size of 20 +/-3 mu m is obtained, and the reflectivity of the backlight surface of the silicon wafer is 40-44%.
S200: sequentially forming a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer on the first surface
In this step, the preparation of the tunnel oxide layer 4 and the intrinsic or in-situ doped poly Si may be achieved by LPCVD, PECVD, PVD, PEALD, etc. and the deposition of the back tunnel oxide layer 4 and the polysilicon (poly) layer is preferably performed by LPCVD, wherein the deposition temperature of the tunnel oxide layer 4 is 590 ± 20 ℃ and the deposition temperature of the polysilicon (poly) layer is 590 ± 20 ℃. The deposition of the intrinsic a-si: H + a-si: H (N) film layer in the existing HBC battery structure mostly adopts expensive CVD equipment, and the low-cost LPCVD equipment is adopted to replace the expensive CVD equipment, so that the equipment investment cost is effectively reduced.
Then placing the intermediate body after depositing the polycrystalline silicon (poly) layer in a tubular diffusion furnace, introducing a boron-containing compound, converting the polycrystalline silicon into a P-type doped crystalline silicon layer 5 at a high temperature of 980-1050 ℃, and forming an isolation layer 11 (namely a BSG layer) in the annealing process by prolonging the annealing time. In some examples, the annealing time may be 40 ± 5min.
In some examples, the P-doped crystalline silicon layer 5 has a diffusion sheet resistance of 80 to 120 Ω/sq. In some examples, the P-doped crystalline silicon layer 5 has a thickness of 80 to 200nm. In some examples, the tunnel oxide layer 4 has a thickness of 1.2 to 1.8nm. In the embodiment of the invention, the specific type of the tunnel oxide layer 4 is not particularly limited, for example, the tunnel oxide layer 4 is a tunnel SiO layer 2 A layer.
The BSG layer serves as a laser energy absorption layer and a mask layer, has the effect of reducing the influence of a laser film opening process on the passivation effect of the P area, also has the effect of providing a hydrogen source to further passivate the polycrystalline silicon and the matrix, improves the passivation effect, and protects the P-type doped crystalline silicon layer 5 from being corroded by alkali in the texturing process. In some examples, the BSG layer 11 is 80 to 120nm thick, thereby further ensuring the above-described effects of the BSG layer 11.
S300: adopting laser to open the isolation layer, the P-type doped crystalline silicon layer and the tunneling oxide layer of the second region
In this step, a laser is used to open the isolation layer in the second region, so that the semiconductor substrate 3 in the second region on the first surface is exposed, the rest of the tunneling oxide layer and the P-type doped crystalline silicon layer are in the first region and the staggered and overlapped region, and the structure is shown in fig. 4, where the tunneling oxide layer 4 and the P-type doped crystalline silicon layer 5 in the first region (region B) are respectively a first tunneling oxide layer 4-1 and a first P-type doped crystalline silicon layer 5-1, and the tunneling oxide layer 4 and the P-type doped crystalline silicon layer 5 in the staggered and overlapped region (region a) are respectively a second tunneling oxide layer 4-2 and a second P-type doped crystalline silicon layer 5-2. In the step, the laser process can be directly adopted for membrane opening, the mask and the mask removing technology are not required to be used for multiple times to form patterning, and the process difficulty is reduced. In the conventional HBC battery structure, the step generally uses a large amount of masks and mask removing technology to form patterning, so that the production cost is high, the difficulty in process control is high, the steps of masking and mask removing are saved in the laser film opening process in the step, and the production efficiency is improved.
In the embodiment of the invention, the design can be carried out by adopting a pattern corresponding to a silk screen pattern, and the type of the laser can be selected from green nanosecond, ultraviolet picosecond, green picosecond or ultraviolet nanosecond.
S400: sequentially forming a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on the surface of the intermediate member prepared in the step S300, which is far away from the second surface
In this step, a first intrinsic amorphous silicon layer 8 and an N-type doped amorphous silicon layer 9 are sequentially formed on the surface of the intermediate member prepared in step S300, which is far from the second surface 3-2, using a CVD apparatus, and the prepared intermediate member is as shown in fig. 6. Specifically, the deposition temperature of the first intrinsic amorphous silicon layer 8 is 180-300 deg.c, and the deposition temperature of the N-type impurity-doped amorphous silicon layer 9 is 180-300 deg.c. The passivation contact of the first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer is adopted to replace a SiOx + doped crystalline silicon layer in the existing TBC battery structure, so that the surface passivation effect of the first doped region is improved, and the electrical property of the solar battery is improved. In some examples, a thickness of the first intrinsic amorphous silicon layerIs 5-30 nm. In some examples, the N-type doped amorphous silicon layer has a thickness of 10 to 30nm. In some examples, the doping concentration of the element in the N-type doped amorphous silicon layer is 10e20cm -3 ～10e21cm -3 。
According to an embodiment of the present invention, step S400 further includes: before the first intrinsic amorphous silicon layer 8 and the N-doped amorphous silicon layer 9 are formed, a third intrinsic amorphous silicon layer 2 and a silicon nitride passivation layer 1 are sequentially formed on the second surface 3-2. The silicon nitride passivation layer 1 has functions as an antireflection film and a protective film, and also has a function as a passivation film for suppressing recombination of photo carriers. The third intrinsic amorphous silicon layer 2 has a function of suppressing photo-carrier recombination at the junction interface with the second surface 3-2.
It should be noted that the reason why the third intrinsic amorphous silicon layer and the silicon nitride passivation layer are deposited before the first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer are formed is that: the third intrinsic amorphous silicon layer and the silicon nitride passivation layer need to be subjected to high temperature processing, thereby preventing the N-type doped amorphous silicon layer from being subjected to high temperature. In addition, the high temperature treatment of the third intrinsic amorphous silicon layer and the silicon nitride passivation layer may generate a thin layer of silicon oxide on the textured surface of the exposed second region, and thus, the exposed second region subjected to the high temperature may be exposed to an acid solution (e.g., HF solution) for about 30 seconds to be etched, thereby removing the silicon oxide.
Further, between steps S300 and S400, the method further includes: and (5) performing alkali texturing on the surface of the intermediate piece prepared in the step (S300) so as to form a pyramid-like textured structure on the second surface and the second area, and removing the residual BSG layer, tunneling oxide layer or P-type doped crystalline silicon layer in the laser second area. The solution used for cleaning may be an acid solution, such as hydrofluoric acid. Preferably, in the cleaning step, the second surface 3-2 may be simultaneously subjected to texturing, specifically, the silicon wafer is first placed in an HF tank, the concentration of an HF solution is 1 ± 0.5%, the silicon wafer is processed at 25 ℃ for 30 ± 5s, the laser grooving area is subjected to residual BSG removal processing, and then the silicon wafer is placed in an alkaline tank for texturing, the alkaline tank solution is a KOH + texturing additive solution with a concentration of 3 ± 0.5%, the solution temperature is 82 ± 2 ℃, and the process time is 600 ± 30s, so that the silicon wafer with an etching amount of 0.6 ± 0.1g and a reflectivity of 11 ± 1% is obtained, and thus, the step completes both the removal of residues in the second area after the laser and the texturing of the second surface 3-2, as shown in fig. 5. It should be noted that, precisely due to the texturing step for the second region, the second region is recessed into the first region and the staggered overlap region, i.e., the distance between the first region and the center line of the semiconductor substrate in the width direction is greater than the distance between the second region and the center line of the semiconductor substrate in the width direction, and the distance between the staggered overlap region and the center line of the semiconductor substrate in the width direction is equal to the distance between the first region and the center line of the semiconductor substrate in the width direction.
S500: removing the first intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer and the isolation layer corresponding to the first region surface
In the step, the first intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer and the isolation layer corresponding to the surface of the first region are removed, the rest first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer are distributed in the second region and the staggered and superposed region, and the rest isolation layer is distributed in the staggered and superposed region.
Specifically, the first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer corresponding to the surface of the first region are removed by laser to expose the isolation layer. In some examples, the opening may be performed using a green nanosecond, ultraviolet picosecond, green picosecond, or ultraviolet nanosecond laser. In some examples, the laser has a power of 6-12W.
The exposed spacer layer (i.e., BSG layer) is then removed using an acid solution (e.g., HF solution) to expose the remaining P-doped crystalline silicon layer, the remaining first intrinsic amorphous silicon layer 8 and the N-doped amorphous silicon layer 9 are distributed in the second region (region C) and the overlap region (region a), and the remaining spacer layer 11 is distributed in the overlap region (region a), wherein the structure of the intermediate is shown in fig. 7. The first intrinsic amorphous silicon layer 8 in the second region (region C) is a first sub-intrinsic amorphous silicon layer 8-1, the N-doped amorphous silicon layer 9 in the second region (region C) is a first N-doped amorphous silicon layer 9-1, the first intrinsic amorphous silicon layer 8 in the staggered overlapping region (region a) is a second sub-intrinsic amorphous silicon layer 8-2, and the N-doped amorphous silicon layer 9 in the staggered overlapping region (region a) is a second N-doped amorphous silicon layer 9-2. The purpose of the step S500 is to expose the grooved region to the first P-type doped crystalline silicon layer 5-1, so as to facilitate the subsequent steps to prepare the second electrode layer and the second gate line. In addition, in S200, the tunneling oxide layer and the P-poly-Si layer are in passivation contact to replace the intrinsic a-Si: H + a-Si: H (P) film layer in the existing HBC battery structure to be passivated, and the tunneling oxide layer and the P-poly-Si layer are relatively small in sensitivity to laser thermal damage, so that the power application range of laser is widened in the process of applying laser etching, namely, the process window is enlarged, the process convenience is improved, and the product yield is improved.
S600: slotting staggered overlap regions
In this step, the staggered stacked region (a region) is grooved by using a laser ablation technique, so that an isolation groove penetrates through the N-type doped amorphous silicon layer (i.e., the second N-type doped amorphous silicon layer 9-2) and the first intrinsic amorphous silicon layer (i.e., the second sub-intrinsic amorphous silicon layer 8-2) in the staggered stacked region to expose a portion of the isolation layer 11, thereby forming an isolation groove 12, and the isolation groove 12 divides the stacked region (a region) into a first stacked region (A1 region) and a second stacked region (A2 region), as shown in fig. 9. In some examples, the width of the isolation trenches 12 is 20-200 μm, preferably 80-120 μm.
Further, after notching the staggered overlap region, the method further comprises: a first electrode layer 13 is formed on one side of the isolation trench 12, the first electrode layer 13 covers the N-type doped amorphous silicon layers 9 of the second region (region C) and the staggered overlapping region (region a), respectively, a second electrode layer 6 is formed on the other side of the isolation trench 12, and the second electrode layer 6 covers the N-type doped amorphous silicon layers 9 of the staggered overlapping region (region a) and the P-type doped crystalline silicon layers 5 of the first region (region a), and the structure of the intermediate part is shown in fig. 8. The first electrode layer 13 functions to enhance the conductivity between the N-doped amorphous silicon layer 9 and the first gate line 10, and the second electrode layer 6 functions to enhance the conductivity between the P-doped crystalline silicon layer 5 and the second gate line 7. In some embodiments, an electrode layer may be formed on the surface of the N-type doped amorphous silicon layer, the structure of the intermediate layer is as shown in fig. 8, and then the overlapping regions are grooved as shown in fig. 9.
In an embodiment of the present invention, the first electrode layer 13 and the second electrode layer 6 are transparent conductive layers. Specific materials of the above-described first electrode layer 13 and second electrode layer 6 are not particularly limited, and as some specific examples, the materials of the first electrode layer 13 and second electrode layer 6 are each independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydrogen oxide, and indium tungsten oxide. In some examples, the thickness of the first electrode layer 13 and the second electrode layer 6 may each independently be 60 to 100nm.
Further, the method further comprises: a first gate line 10 is formed on a portion of the surface of the first electrode layer 13, and a second gate line 7 is formed on a portion of the surface of the second electrode layer 6. Specifically, the first gate line 10 may be formed on a portion of the surface of the first electrode layer 13 and the second gate line 7 may be formed on a portion of the surface of the second electrode layer 6 by screen printing, ink jet printing, laser transfer, electroless plating, electroplating, or PVD.
According to the method provided by the embodiment of the invention, compared with the preparation process of the HBC battery in the prior art, the method adopts the passivating contact of the tunneling oxide layer and the P-poly-Si layer to replace the passivation of the intrinsic a-Si: H + a-Si: H (P) film layer in the existing HBC battery structure, and the tunneling oxide layer and the P-poly-Si layer have relatively small sensitivity to laser thermal damage and can reduce the influence on the P region passivation effect in the laser film opening process, so that the laser process can be directly adopted for film opening in the steps S500 and S600, the influence on the P region passivation effect can be reduced by the laser film opening process, the process window is further increased, and the process difficulty is reduced. In the conventional HBC cell structure, a large amount of masks and mask removal technologies are generally used in the step to form patterning, so that the production cost is high and the difficulty in process control is high. Meanwhile, the method adopts the BSG layer to replace the SiNx mask layer, reduces the film coating process required by the preparation of the SiNx mask layer, has simple process and integrally reduces the manufacturing cost of the battery; compared with the SiNx mask layer, the BSG layer has higher density, higher stability and less falling off during etching. In addition, the method combines the texturing process with local etching, thereby saving the previous texturing process. In the deposition process of the tunneling oxide layer and the P-poly-Si of the P-type doped crystalline silicon layer, expensive CVD equipment is replaced by low-cost LPCVD equipment, and the equipment investment cost is effectively reduced.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
The following embodiments of the present invention are described in detail, and it should be noted that the following embodiments are exemplary only, and are not to be construed as limiting the present invention. In addition, all reagents used in the following examples are commercially available or can be synthesized according to methods herein or known, and are readily available to those skilled in the art for reaction conditions not listed, if not explicitly stated.
Example 1
The embodiment provides a solar cell, and a preparation method thereof is as follows:
1) An N-type 1.3. Omega. Cm 166 x 166 wafer was provided having a thickness of 165 μm.
2) Polishing and cleaning: putting the silicon wafer into a groove type alkali polishing machine table for polishing and cleaning, wherein the working volume of a groove body of the cleaning machine is 360L, firstly, pre-cleaning the silicon wafer, and removing organic and other contaminants generated in the cutting and transportation processes of the silicon wafer; in the embodiment, an SC1 reagent for standard RCA cleaning is used for cleaning, and the main function of the SC1 reagent cleaning is alkaline oxidation, removal of particles on a silicon wafer, oxidation and removal of a small amount of organic matters on the surface and metal atom pollution of Au, ag, cu, ni, cd, zn, ca, cr and the like; washing the residual chemicals with water, and performing alkali polishing with 5.97% by weight of KOH at 80 deg.C for 300s to remove the damage and polish. And cleaning SC1, cleaning with ozone, and finally carrying out acid pickling and dehydration to finish polishing and cleaning. The temperature is controlled below 80 ℃ during cleaning, and the temperature is controlled below 80 ℃ so as to reduce the loss caused by volatilization of ammonia and hydrogen peroxide.
3) Sending the polished silicon wafer into low pressure vapor deposition LPCVD (low pressure vapor deposition), and depositing tunneling SiO with the thickness of 1.4nm 2 And intrinsic polysilicon poly Si with thickness of 90nm, tunneling SiO 2 The deposition temperature of (1) is 590 deg.C and the deposition temperature of intrinsic polysilicon poly Si is 590 deg.C.
4) Placing the intermediate body after depositing the polycrystalline silicon (poly) layer in a tubular diffusion furnace, and introducing BCl 3 And carrying out boron doping on the poly Si region at 1000 ℃ and completing the crystallization of poly to form a P-type crystalline silicon layer P-poly-Si with the diffusion sheet resistance of 100 omega/sq. During the annealing of the P-poly-Si layer of the P-type silicon layer, a BSG layer with a thickness of 90nm is formed. The reason for the complete crystallization of poly is: poly si changes from amorphous to crystalline at high temperatures where 100% crystallization can be achieved due to the high temperature of the boron diffusion.
5) And (3) opening the BSG film in the N area by adopting a 532nm green light nanosecond laser to expose the backlight surface of the silicon wafer, namely the C area in the figure 1.
6) The silicon wafer after laser is placed in a texturing machine, the working volume of a machine groove is 360L, and the main processes and the functions are as follows: (1) the first functional tank used 1% by weight of HF at a constant temperature of 25 ℃ for the removal of the residue. (2) After the cleaning, the silicon wafer was put into the next texturing bath with a solution of KOH 3.29% by weight at a texturing temperature of 82 ℃ for 570 seconds, thereby completing the texturing treatment of the front and back laser regions. (3) Then carrying out efficient SC1 cleaning with NH as cleaning solution 4 OH-H 2 O 2 -H 2 O, the volume ratio of the three is 1:1:5, the cleaning temperature is 65 ℃, and the cleaning time is 300s. (4) With 50ppm O 3 Water and HF were added to the mixture to conduct pyramid rounding, and the concentration of hydrofluoric acid was 0.31 wt%. (5) SC2 is cleaned to remove metal residues, and the cleaning solution is HCL-H 2 O 2 -H 2 And O, the volume ratio of the three is 1. (6) Finally, the etching is finished by 5 percent by weight of hydrofluoric acid cleaning.
7) And sequentially depositing a-si: H with the thickness of 15nm and SiNx with the thickness of 90nm on the front surface, wherein the deposition temperature of the a-si: H is 200 ℃, and the deposition temperature of the SiNx is 550 ℃.
8) H (i.e., the first intrinsic amorphous silicon layer i-a-Si) and H (N) (i.e., the N-type amorphous silicon layer N-a-Si) were deposited on the back surface of the silicon wafer using a CVD apparatus to a thickness of 10 nm. The deposition temperature of a-si: H is 200 ℃ and the deposition temperature of a-si: H (N) is 200 ℃.
9) And (3) opening the N-type amorphous silicon layer N-a-Si and the first intrinsic amorphous silicon layer i-a-Si on the B area by adopting nanosecond laser to expose the BSG layer on the B area, wherein the laser power is 12w.
10 ) the BSG layer exposed in the 8-wt% hydrofluoric acid cleaning step 7) was employed, whereby the BSG layer of the trench region was removed to expose a portion of the P-type doped crystalline silicon layer P-poly-Si.
11 A layer of ITO (indium tin oxide) with a thickness of 80nm was deposited on the back side.
12 Ultraviolet picosecond laser is used for slotting to expose the BSG layer, an isolation slot is formed to insulate the N region and the P region, and leakage caused by interconnection of the N/P regions is prevented. The insulation resistance of the insulation region is tested to be more than 10M omega.
13 The back metallized electrode is prepared by a screen printing technology by adopting metal silver, and is solidified and annealed.
Example 2
The present embodiment provides a solar cell, and the present embodiment is different from embodiment 1 only in that:
3) The polished wafer was sent to a low pressure vapor deposition LPCVD to deposit SiO with a thickness of 1.4nm 2 And intrinsic polycrystalline silicon poly Si with a thickness of 120nm.
Example 3
The present embodiment provides a solar cell, and the present embodiment is different from embodiment 1 only in that:
3) Feeding the polished wafer into low pressure vapor deposition LPCVD to deposit SiO with a thickness of 1.4nm 2 And intrinsic polysilicon poly Si with a thickness of 150 nm.
Example 4
The present embodiment provides a solar cell, and the present embodiment is different from embodiment 1 only in that:
9) And (3) opening the N-type amorphous silicon layer N-a-Si and the first intrinsic amorphous silicon layer i-a-Si on the B area by adopting nanosecond laser to expose the BSG layer on the B area, wherein the laser power is 10w.
Example 5
The present embodiment provides a solar cell, and the present embodiment is different from embodiment 1 only in that:
9) And opening the N-type amorphous silicon layer N-a-Si and the first intrinsic amorphous silicon layer i-a-Si on the B area by nanosecond laser to expose the BSG layer on the B area, wherein the laser power is 8w.
Example 6
The present embodiment provides a solar cell, and the present embodiment is different from embodiment 1 only in that:
9) And (3) opening the N-type amorphous silicon layer N-a-Si and the first intrinsic amorphous silicon layer i-a-Si on the B area by adopting nanosecond laser to expose the BSG layer on the B area, wherein the laser power is 6w.
Example 7
The present embodiment provides a solar cell, and the present embodiment is different from embodiment 2 only in that:
9) And opening the N-type amorphous silicon layer N-a-Si and the first intrinsic amorphous silicon layer i-a-Si on the B area by nanosecond laser to expose the BSG layer on the B area, wherein the laser power is 10w.
Example 8
The present embodiment provides a solar cell, and the present embodiment is different from embodiment 3 only in that:
9) And (3) opening the N-type amorphous silicon layer N-a-Si and the first intrinsic amorphous silicon layer i-a-Si on the B area by adopting nanosecond laser to expose the BSG layer on the B area, wherein the laser power is 10w.
Comparative example 1
The present comparative example provides a method for producing an HBC solar cell, comprising the steps of:
1) An N-type 1.3. Omega. Cm 166 x 166 silicon wafer was provided, 165 μm thick.
2) Polishing and cleaning: putting the silicon wafer into a groove type alkali polishing machine table for polishing and cleaning, wherein the working volume of a groove body of the cleaning machine is 360L, firstly, pre-cleaning the silicon wafer, and removing organic and other contaminants generated in the cutting and transportation processes of the silicon wafer; in this example, cleaning was carried out using standard RCA cleaning solution No. 1, in which NH was used as the cleaning solution No. 1 4 OH-H 2 O 2 -H 2 O, the volume ratio of the three components is 1:1:5,the temperature during cleaning is 65 ℃; the main function of cleaning with the SC-1 reagent is alkaline oxidation, removal of particles on a silicon wafer, oxidation and removal of a small amount of organic matters on the surface and metal atom pollution of Au, ag, cu, ni, cd, zn, ca, cr and the like; after washing with water and the residual chemicals, alkali polishing was carried out at a temperature of 80 ℃ for 300 seconds in an alkali polishing formulation of 5.97% by weight of KOH, and damage removal and polishing were carried out. And then cleaning SC1, cleaning with ozone, and finally, carrying out acid washing and dehydration to finish polishing and cleaning.
3) Depositing a SiNx mask layer on the back surface of the silicon wafer by using PECVD equipment, wherein the thickness of the SiNx mask layer is 200nm, and the refractive index of the SiNx mask layer is 2.4%;
4) In a groove type cleaning machine, firstly, a silicon wafer is put into an HF groove, the mass concentration of an HF solution is 1%, and the silicon wafer is treated at normal temperature for 30s to remove SiNx on the side edge and the front surface of a battery in a winding manner. And then, allowing the mixture to enter an alkali tank for texturing, wherein a texturing solution is a KOH + texturing additive solution with the mass concentration of 2.5%, the texturing temperature is 82 ℃, and the texturing time is 780s. Then enters HNO 3 Smooth treatment of suede in HF tank with solution volume ratio of HNO 3 HF =1, total etching amount 1.8g, high texture microstructure with 12% of front surface reflectivity and 4um of textured pyramid size, and final normal temperature treatment in 8 wt% HF bath for 300s to completely remove the SiNx mask remaining on the back surface.
5) In a CVD device, 15nm of intrinsic a-si: H, 25nm of phosphorus-doped a-si: H (N), 200nm of SiNx layer and 15nm of intrinsic a-si: H are sequentially deposited on the back surface of a silicon wafer.
6) And (3) slotting the intrinsic a-si: H of the outermost layer of the back by adopting laser, and opening a P + region which is a region for depositing the intrinsic a-si: H and the intrinsic a-si: H (P) in the subsequent steps.
7) In a groove type cleaning machine, firstly, a silicon chip is placed in an HF groove, the mass concentration of an HF solution is 8%, the processing time is 200s, and the SiNx removal processing is carried out on a laser grooving area; then the solution is put into an alkali tank for etching treatment, and the solution is 0.5 weight percent of KOH and 0.15 weight percent of H 2 O 2 And the solution is etched for 400s at the temperature of 25 ℃ to remove the residual intrinsic a-si: H and phosphorus-doped a-si: H (N) layers.
8) In the CVD equipment, the back surface of the silicon wafer is plated with intrinsic a-si: H with the thickness of 15nm and a-si: H (P) doped with B with the thickness of 25nm in sequence.
9) In CVD equipment, an intrinsic a-si: H layer with the thickness of 15nm and a SiNx layer with the thickness of 85nm are plated on the front surface of a silicon wafer in sequence.
10 Partial intrinsic a-si: H and a-si: H (P) of the back N + region are etched by laser with the laser power of 6w.
11 The SiNx layer leaking out of the N + region after the laser is removed by using an HF solution, the mass concentration of the solution is 8%, the time is 400s, and the phosphorus-doped a-si: H (N) layer is exposed.
12 A layer of ITO (indium tin oxide) was deposited on the back side to a thickness of 80nm.
13 355nm ultraviolet picosecond laser is adopted for slotting to expose the SiNx mask layer, an isolation slot is formed, the N region and the P region are insulated, and leakage caused by interconnection of the N/P regions is prevented. The insulation resistance of the insulation region is tested to be more than 10M omega, and the laser width is 100 mu M.
14 The back metallized electrode is prepared by a screen printing technology by adopting metal silver, and is solidified and annealed.
Comparative example 2
The comparative example differs from comparative example 1 only in that:
10 Partial intrinsic a-si: H and a-si: H (P) of the back N + region are etched by laser with the laser power of 10w.
Comparative example 3
The comparative example differs from comparative example 1 only in that:
10 Partial intrinsic a-si: H and a-si: H (P) of the back N + region are etched by laser with the laser power of 12w.
The solar cells prepared in examples 1 to 8 and comparative examples 1 to 3 were subjected to performance tests for energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, and fill factor FF, and the results are shown in table 1.
TABLE 1
It can be seen that, in comparative examples 1 to 3, patterning was performed by using the mask and the mask removal techniques many times, which resulted in high production cost and difficulty in process control, whereas in examples 1 to 8, tunneling SiO was used 2 Layer + P-type doped crystalline silicon layer P-poly-Si passivation contact replaces the intrinsic a-Si: H + a-Si: H (P) film passivation of comparative example 1 due to the tunneling SiO in examples 1-8 2 The layer + P type doped crystalline silicon layer P-poly-Si has relatively low sensitivity to laser thermal damage, so that the laser process can be directly adopted for opening the film in the step, and the mask and mask removing technology are not required to be used for forming patterning for many times. Comparative example 1 produced higher efficiency at lower laser power, but at greater laser power, comparative examples 2-3 exhibited a significant efficiency reduction, visible as tunneling SiO 2 The layer + P type crystalline silicon layer has relatively small sensitivity to laser thermal damage, and the influence on the passivation effect of the corresponding doped region of the first region can be reduced during the laser film opening process.
And as can be seen from table 1, the energy conversion efficiency Eta, the open circuit voltage Uoc, the short circuit current Isc, and the fill factor FF of examples 1 to 8 all reached levels comparable to those of comparative example 1, as compared to comparative examples 1 to 3.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (18)
1. A back contact solar cell, comprising:
a semiconductor substrate including opposing first and second surfaces, the first surface including a first region, a second region, and an interleaved stack region between the first and second regions, a distance between the first region and a centerline of the semiconductor substrate in a width direction being greater than a distance between the second region and the centerline of the semiconductor substrate in the width direction;
a first tunneling oxide layer and a first P-type doped crystalline silicon layer, where the first tunneling oxide layer is on the first area, and the first P-type doped crystalline silicon layer is on a surface of the first tunneling oxide layer away from the semiconductor substrate;
a first sub intrinsic amorphous silicon layer and a first N type doped amorphous silicon layer, wherein the conductivity type of the first P type doped amorphous silicon layer is opposite to that of the first N type doped amorphous silicon layer, the first sub intrinsic amorphous silicon layer is on the second region, and the first N type doped amorphous silicon layer is on the surface of the first sub intrinsic amorphous silicon layer far away from the semiconductor substrate;
the staggered and superposed layer comprises a second tunneling oxide layer, a second P-type doped crystalline silicon layer, a second sub-intrinsic amorphous silicon layer and a second N-type doped amorphous silicon layer which are sequentially arranged in the staggered and superposed area, and the conductivity types of the second P-type doped crystalline silicon layer and the second N-type doped amorphous silicon layer are opposite;
and the isolation structure comprises an isolation layer and an isolation groove, the isolation layer is arranged between the second sub intrinsic amorphous silicon layer and the second P-type doped crystalline silicon layer, and the isolation groove penetrates through the second N-type doped amorphous silicon layer and the second sub intrinsic amorphous silicon layer.
2. The back contact solar cell of claim 1, wherein the second region is a textured structure;
and/or the first area is of a suede structure;
and/or the second surface is of a textured structure.
3. The back contact solar cell of claim 1, further comprising: the first electrode layer is arranged on one side of the isolation groove, the first electrode layer covers the first N-type doped amorphous silicon layer and part of the second N-type doped amorphous silicon layer, the second electrode layer is arranged on the other side of the isolation groove, and the second electrode layer covers part of the second N-type doped amorphous silicon layer and the first P-type doped crystalline silicon layer.
4. The back contact solar cell of claim 3, wherein the first and second electrode layers are transparent conductive layers, and the materials of the first and second electrode layers are each independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydrogen oxide, and indium tungsten oxide.
5. The back contact back junction solar cell of claim 1, wherein the isolation layer comprises a BSG layer between the second sub-intrinsic amorphous silicon layer and the second P-doped crystalline silicon layer.
6. The back contact solar cell of claim 5, wherein the BSG layer has a thickness of 80-120 nm.
7. The back contact back junction solar cell of claim 1, further comprising a passivation layer comprising a third intrinsic amorphous silicon layer on the second surface and a silicon nitride passivation layer on a surface of the third intrinsic amorphous silicon layer remote from the semiconductor substrate.
8. The back contact solar cell of any of claims 1-7,
the first tunneling oxide layer and the second tunneling oxide layer are both tunneling SiO 2 A layer; and/or
The thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are both 1.2-1.8 nm; and/or
The thicknesses of the first P-type doped crystalline silicon layer and the second P-type doped crystalline silicon layer are both 80-200 nm; and/or
The diffusion sheet resistances of the first P-type doped crystalline silicon layer and the second P-type doped crystalline silicon layer are both 80-120 omega/sq; and/or
The thicknesses of the first sub intrinsic amorphous silicon layer and the second sub intrinsic amorphous silicon layer are both 5-30 nm; and/or
The thicknesses of the first N-type doped amorphous silicon layer and the second N-type doped amorphous silicon layer are both 10-30 nm; and/or
The element doping concentration of the first N-type doped amorphous silicon layer and the element doping concentration of the second N-type doped amorphous silicon layer are both 10e20cm -3 ～10e21cm -3 。
9. A method of fabricating a back contact solar cell, comprising:
providing a semiconductor substrate having opposing first and second surfaces, the first surface comprising a first region, a second region, and an interleaved stack region between the first and second regions;
sequentially forming a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer on the first surface;
adopting laser to open the film of the second area to expose part of the second area to form an intermediate piece;
sequentially forming a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on the surface of the intermediate piece, which is far away from the second surface;
removing the first intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer and the isolation layer corresponding to the surface of the first region;
and etching the staggered and superposed regions to ensure that at least part of the N-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the staggered and superposed regions are etched through to form an isolation groove.
10. The method of claim 9, further comprising:
and performing alkali texturing on the semiconductor substrate after the second area is exposed so as to form a pyramid-like textured structure on the second surface and the second area.
11. The method of claim 10, wherein after the pyramid-like textured structures are formed on the second surface and the second region, a third intrinsic amorphous silicon layer and a silicon nitride passivation layer are sequentially formed on the second surface.
12. The method of claim 9, wherein after etching the staggered stack area, the isolation trench sides of the staggered stack area are separated into a first staggered stack area and a second staggered stack area.
13. The method of claim 12, wherein a first electrode layer is formed on one side of the isolation trench and covers the N-doped amorphous silicon layer of the second region and the N-doped amorphous silicon layer of the staggered overlapping region, respectively, and a second electrode layer is formed on the other side of the isolation trench and covers the N-doped amorphous silicon layer of the staggered overlapping region and the P-doped crystalline silicon layer of the staggered overlapping region.
14. The method of claim 12, wherein a first gate line is formed on a portion of the surface of the first electrode layer and a second gate line is formed on a portion of the surface of the second electrode layer.
15. The method of claim 9, wherein the tunneling oxide layer and the P-type doped crystalline silicon layer are deposited by LPCVD.
16. The method of claim 9, wherein the isolation layer comprises BSG.
17. The method of claim 16, wherein a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer are sequentially formed on the first surface; the method comprises the following steps:
depositing a polycrystalline silicon layer after the tunneling oxide layer is formed;
performing boron diffusion on the polycrystalline silicon layer at high temperature to convert the polycrystalline silicon layer into the P-type doped crystalline silicon layer;
and prolonging the preset annealing time to form the BSG layer.
18. The method of claim 17, wherein the boron diffusion to the polysilicon layer is performed at a temperature of 980 to 1050 ℃; and/or
The predetermined annealing time is 40 +/-5 min.
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