CN117594684A - Double-sided hybrid solar cell and preparation method thereof - Google Patents
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
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- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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Abstract
The invention discloses a double-sided hybrid solar cell and a preparation method thereof, wherein the double-sided hybrid solar cell comprises: a semiconductor substrate; a tunneling oxide layer and a doped polysilicon layer; an alumina layer and an antireflection layer; an intrinsic amorphous silicon layer and a doped amorphous silicon layer. By arranging the doped poly finger (i.e. the doped polysilicon layer) in the first area of the front side, the parasitic light absorption of the front side is reduced, and the problem of higher parasitic absorption caused by the comprehensive amorphous silicon of the front side in the HJT battery is solved. And the aluminum oxide layer and the anti-reflection layer are arranged in the second area of the front surface, so that the passivation is carried out on the second area, the recombination of the front surface is reduced, the service life of minority carriers is prolonged, and the reflectivity is further reduced. In addition, the doped polysilicon layer arranged in the first area and the alumina layer arranged in the second area have low cleaning requirements (compared with HJT batteries with high cleaning requirements on amorphous silicon passivation suede), so that the process difficulty is reduced.
Description
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to a double-sided hybrid solar cell and a preparation method thereof.
Background
In recent years, with the continuous development of the related photovoltaic technology, the mass production battery efficiency of each large manufacturer is continuously improved, and the PERC battery still occupies a considerable mass as a main stream product in the current market, but the mass production efficiency of the PERC battery is approaching to the theoretical limit of 24.5%. According to the rule that the conversion efficiency of the crystalline silicon battery improves by 0.5 percentage points every year, the conversion efficiency of the crystalline silicon battery reaches the industrialization limit of 27.5 percent by 2030 and approaches the theoretical limit of 29.43 percent of the single crystalline silicon battery, thereby entering the development age of the crystalline silicon laminated battery. As a representative of high efficiency cells, three N-type technology routes, tunnel oxide passivation contact solar cells (Tunnel Oxide Passivated Contact, TOPCON), heterojunction solar cells (Hetero-Junction with Instrinsic Thin-layer, HJT) and interdigitated back contact cell technology (Interdigitated back contact, IBC), all possess very high efficiency ceils.
The current industry focuses mainly on the two passivation contact technology routes of TOPCON and HJT. The logic of the high-efficiency crystalline silicon battery technology evolution is that the recombination of battery carriers is reduced by using a lower-cost large-scale processing means, so that the open-circuit voltage and the conversion efficiency are improved. PERC cell wins BSF aluminum back field cell, and the key is to implement better passivation technique on the back of cell, enhancing internal back reflection of light, reducing back recombination. From the laboratory and industrialization results, the passivation contact technology of TOPCon and HJT batteries can greatly reduce contact recombination of metal electrodes and batteries, thereby realizing higher conversion efficiency than PERC batteries. The TOPCO battery process ratio HJT compatible with the PERC production line is a step forward in mass production cost.
The HJT battery technology is a Chinese name heterojunction battery, one of photovoltaic cells, is to deposit an amorphous silicon film on crystalline silicon, combines the advantages of the crystalline silicon battery and the film battery, has the advantages of high conversion efficiency, low process temperature, high stability, low attenuation rate, double-sided power generation and the like, and has subverted technology. The four technological processes are easier to realize than TOPCO, and the double-sided passivation contact is realized, so that the efficiency is better than that of the TOPCO on one side.
The prior double-sided HJT battery equipment has high investment, high low-temperature CVD equipment cost and poor uniformity while effectively improving the efficiency of the nanocrystalline silicon; the PVD equipment uses the target material, and the cost of double-sided coating is higher. The cleaning requirement is high, and the best passivation effect can be achieved by the intrinsic amorphous silicon with higher cleaning requirement; the amorphous silicon with the overall front surface results in higher parasitic absorption and lower current density.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. The invention aims to provide a double-sided hybrid solar cell and a preparation method thereof.
In one aspect of the invention, a bifacial hybrid solar cell is presented. According to an embodiment of the present invention, the bifacial hybrid solar cell includes:
a semiconductor substrate having opposing first and second surfaces, the first surface comprising adjacent first and second regions;
a tunneling oxide layer on the first region and a doped polysilicon layer on a surface of the tunneling oxide layer remote from the semiconductor substrate;
an aluminum oxide layer on the second region and an anti-reflection layer on a surface of the aluminum oxide layer remote from the semiconductor substrate;
an intrinsic amorphous silicon layer and a doped amorphous silicon layer, the doped polysilicon layer being of opposite conductivity type to the doped amorphous silicon layer, the intrinsic amorphous silicon layer being on the second region, the doped amorphous silicon layer being on a surface of the intrinsic amorphous silicon layer remote from the semiconductor substrate.
According to the double-sided hybrid solar cell provided by the embodiment of the invention, the doped poly finger (namely the doped polysilicon layer) is arranged in the first area of the front side, so that parasitic light absorption of the front side is reduced (as the polysilicon layer is not arranged except the grid line area on the light receiving surface, but the polysilicon and aluminum oxide are laminated, the crystallization rate of the silicon nitride and aluminum oxide is higher, the structure is of a short-range and long-range order, the polysilicon is of a short-range disordered structure, a plurality of grain boundaries are formed in the polysilicon, light recombination is easy to generate due to the existence of the grain boundaries, and the recombination can be understood as parasitic absorption of light), and the problem that the parasitic absorption is higher due to the comprehensive amorphous silicon on the front side in the HJT cell is solved. And the aluminum oxide layer and the anti-reflection layer are arranged in the second area of the front surface, so that the passivation is carried out on the second area, the recombination of the front surface is reduced, the service life of minority carriers is prolonged, and the reflectivity is further reduced. In addition, the doped polysilicon layer arranged in the first area and the alumina layer arranged in the second area have low cleaning requirements (compared with HJT batteries with high cleaning requirements on amorphous silicon passivation suede), so that the process difficulty is reduced.
In addition, the bifacial hybrid solar cell according to the above embodiment of the present invention may have the following additional technical features:
in some embodiments of the invention, the bifacial hybrid solar cell further comprises: and the first electrode is contacted with the doped polysilicon layer.
In some embodiments of the invention, the first electrode is formed on an upper surface of the doped polysilicon layer and extends to at least a portion of a side of the doped polysilicon layer.
In some embodiments of the invention, the bifacial hybrid solar cell further comprises: a transparent conductive layer on a surface of the doped amorphous silicon layer remote from the intrinsic amorphous silicon layer, and a second electrode in contact with the transparent conductive layer.
In some embodiments of the present invention, the doped amorphous silicon layer is a P-type doped amorphous silicon layer P-a-Si, and the doped polysilicon layer is an N-type doped polysilicon layer N-poly-Si; or the doped amorphous silicon layer is N-type doped amorphous silicon layer N-a-Si, and the doped polysilicon layer is P-type doped polysilicon layer P-poly-Si.
In some embodiments of the present invention, the tunnel oxide layer has a thickness of 1.2-3.5nm, preferably 1.5-2.5nm; and/or the thickness of the doped polysilicon layer is 30-270 nm; preferably 30-50nm.
In some embodiments of the invention, the intrinsic amorphous silicon layer has a thickness of 5-15 nm; and/or the doped amorphous silicon layer is a P-type doped amorphous silicon layer, the thickness of the P-type doped amorphous silicon layer is 20-30nm, or the doped amorphous silicon layer is an N-type doped amorphous silicon layer, and the thickness of the N-type doped amorphous silicon layer is 10-20nm.
In some embodiments of the invention, the alumina layer has a thickness of 4-14nm.
In yet another aspect of the invention, a method of making a bifacial hybrid solar cell is provided. According to an embodiment of the invention, the method comprises:
providing a semiconductor substrate having opposite first and second surfaces, the first surface including adjacent first and second regions;
sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface;
removing the doped polysilicon layer and the tunneling oxide layer corresponding to the second region, and removing the doped polysilicon layer and the tunneling oxide layer formed on the second surface and the side surface of the semiconductor substrate by winding plating;
sequentially forming an alumina layer and an anti-reflection layer in the second region;
and forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the second surface in sequence.
According to the method provided by the embodiment of the invention, the parasitic light absorption of the front surface is reduced by forming the doped poly finger (namely the doped polysilicon layer) in the first area of the front surface (as the polysilicon layer is not arranged except the grid line area on the light receiving surface, but the silicon nitride and the aluminum oxide are laminated, the crystallization rate of the silicon nitride and the aluminum oxide is higher, the structure of short range and long range order is adopted, the polysilicon is of a short range disordered structure, so that the polysilicon has a plurality of grain boundaries, light recombination can be easily generated due to the existence of the grain boundaries, and the recombination can be understood as the parasitic absorption of light), and the problem that the parasitic absorption is higher due to the comprehensive amorphous silicon on the front surface in the HJT battery is solved. And an alumina layer and an anti-reflection layer are formed in the second area of the front surface, and the second area is passivated, so that the recombination of the front surface is reduced, the service life of minority carriers is prolonged, and the reflectivity is further reduced. In addition, the doped polysilicon layer formed in the first area and the alumina layer formed in the second area have low cleaning requirements (compared with HJT batteries with high cleaning requirements on amorphous silicon passivation suede) so as to reduce the process difficulty.
In addition, the method according to the above embodiment of the present invention may further have the following technical solutions:
in some embodiments of the invention, the method further comprises: a first electrode is prepared and is brought into contact with the doped polysilicon layer.
In some embodiments of the invention, the method further comprises: forming a transparent conductive layer on a surface of the doped amorphous silicon layer remote from the intrinsic amorphous silicon layer; and preparing a second electrode, and enabling the second electrode to be in contact with the transparent conductive layer.
In some embodiments of the present invention, LPCVD, PECVD, PVD or PEALD is used to form the tunnel oxide layer and the doped polysilicon layer, respectively.
In some embodiments of the present invention, the removing the doped polysilicon layer and the tunneling oxide layer corresponding to the second region, and removing the doped polysilicon layer and the tunneling oxide layer formed by the second surface and the side-wrapping plating of the semiconductor substrate includes the following steps:
removing the doped oxide layer on the surface of the doped polysilicon layer corresponding to the second region;
removing a doped oxide layer on the surface of the doped polysilicon layer formed by the second surface and the side surface coiling plating of the semiconductor substrate;
removing a doped polysilicon layer formed on the second surface and the side surface of the semiconductor substrate in a winding manner, and the doped polysilicon layer corresponding to the second region;
and removing the tunneling oxide layer formed on the second surface and the side surface of the semiconductor substrate by winding plating, the tunneling oxide layer corresponding to the second region, and the doped oxide layer on the surface of the doped polysilicon layer corresponding to the first region.
In some embodiments of the invention, the aluminum oxide layer and the anti-reflective layer are formed by deposition using PECVD, PEALD, or ALD, respectively.
In some embodiments of the present invention, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are formed by deposition using a CVD apparatus, respectively.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a double-sided hybrid solar cell according to an embodiment of the present invention.
The drawings are marked:
the semiconductor device comprises a first electrode, a 2-doped polycrystalline silicon layer, a 3-antireflection layer, a 4-alumina layer, a 5-semiconductor substrate, a 6-intrinsic amorphous silicon layer, a 7-transparent conductive layer, an 8-tunneling oxide layer, a 9-doped amorphous silicon layer and a 10-second electrode.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
In one aspect of the invention, a bifacial hybrid solar cell is presented. According to an embodiment of the present invention, referring to fig. 1, a bifacial hybrid solar cell includes: a semiconductor substrate 5, the semiconductor substrate 5 having opposing first and second surfaces, the first surface comprising adjacent first and second regions; a tunneling oxide layer 8 and a doped polysilicon layer 2, the tunneling oxide layer 8 being on the first region, the doped polysilicon layer 2 being on a surface of the tunneling oxide layer 8 remote from the semiconductor substrate 5; an alumina layer 4 and an anti-reflection layer 3, the alumina layer 4 being on the second region, the anti-reflection layer 3 being on a surface of the alumina layer 4 remote from the semiconductor substrate 5; an intrinsic amorphous silicon layer 6 and a doped amorphous silicon layer 9, the doped polysilicon layer 2 being of opposite conductivity type to the doped amorphous silicon layer 9, the intrinsic amorphous silicon layer 6 being on the second region, the doped amorphous silicon layer 9 being on a surface of the intrinsic amorphous silicon layer 6 remote from the semiconductor substrate 5. Therefore, by arranging the doped poly finger (namely the doped polysilicon layer 2) in the first area of the front surface, the parasitic light absorption of the front surface is reduced (as the polysilicon layer is not arranged except the grid line area on the light receiving surface, but the silicon nitride and the aluminum oxide are laminated, the crystallization rate of the silicon nitride and the aluminum oxide is higher, the structure is of short-range and long-range order, the polysilicon is of a short-range disordered structure, a plurality of grain boundaries are formed in the polysilicon, the light recombination can be easily generated due to the existence of the grain boundaries, and the recombination can be understood as the parasitic absorption of light), and the problem that the parasitic absorption is higher due to the comprehensive amorphous silicon on the front surface in the HJT battery is solved. And the aluminum oxide layer 4 and the anti-reflection layer 3 are arranged in the second area of the front surface, so that the passivation is carried out on the second area, the recombination of the front surface is reduced, the service life of minority carriers is prolonged, and the reflectivity is further reduced. In addition, the doped polysilicon layer 2 arranged in the first area and the alumina layer 4 arranged in the second area have low cleaning requirements (compared with the HJT battery which has high cleaning requirements on amorphous silicon passivation suede, the HJT battery has epitaxial growth after intrinsic amorphous silicon deposition and is a low-temperature passivation system, and little pollution is amplified), so that the process difficulty is reduced.
In the embodiment of the present invention, the material of the semiconductor substrate 5 may be silicon (Si) or the like. In terms of conductivity type, the semiconductor substrate 5 may be an N-type semiconductor substrate 5 or a P-type semiconductor substrate 5. The first surface of the semiconductor substrate 5 refers to a light-receiving surface, and the second surface of the semiconductor substrate 5 refers to a light-receiving surface.
In the embodiment of the present invention, the doped polysilicon layer refers to a high-temperature doped polysilicon layer. The above-mentioned doped amorphous silicon layer refers to low-temperature doped amorphous silicon or doped microcrystalline silicon.
According to an embodiment of the present invention, the doped amorphous silicon layer 9 is a P-type doped amorphous silicon layer 9, and the doped polysilicon layer 2 is an N-type doped polysilicon layer 2. Or, the doped amorphous silicon layer 9 is an N-type doped amorphous silicon layer 9, and the doped polysilicon layer 2 is a P-type doped polysilicon layer 2.
In the embodiment of the present invention, the specific kind of the tunnel oxide layer 8 is not particularly limited, and as a specific example, the tunnel oxide layer 8 is tunneling SiO 2 A layer. According to some embodiments of the present invention, the thickness of the tunnel oxide layer 8 may be 1.2-3.5nm, (e.g., may be 1.2/1.5/2.0/2.5/3.0/3.5 nm), and preferably 1.5-2.5nm, thereby limiting the thickness of the tunnel oxide layer 8 to the above range, and further ensuring a better surface passivation effect and a multi-sub tunneling effect.
According to further embodiments of the present invention, the thickness of the doped polysilicon layer 2 is 30-270 nm (for example, 30/50/100/120/140/160/180/200/250/270nm may be possible), preferably 30-50nm, thereby limiting the thickness of the doped polysilicon layer 2 to the above range, and further reducing the parasitic absorption of the front surface while ensuring a good field passivation effect.
According to further embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer 6 may be set to 5 to 30nm, thereby limiting the thickness of the intrinsic amorphous silicon layer 6 to the above range and having a good passivation effect on the silicon-based surface.
According to further embodiments of the present invention, the doped amorphous silicon layer 9 is a P-type doped amorphous silicon layer 9, and the thickness of the P-type doped amorphous silicon layer 9 is 20-30nm. Or, the doped amorphous silicon layer 9 is an N-type doped amorphous silicon layer 9, and the thickness of the N-type doped amorphous silicon layer 9 is 10-20nm.
The antireflection layer 3 has a function as an antireflection film and a protective film, and also has a function as a passivation film for suppressing recombination of photocarriers. The alumina layer 4 has a function of suppressing the recombination of photocarriers at the junction interface with the second region. According to further embodiments of the present invention, the thickness of the alumina layer 4 is 4-14nm, whereby the passivation effect of the alumina layer 4 is further ensured, the recombination of the front surface is further reduced, and the minority carrier lifetime is further increased.
According to further embodiments of the present invention, referring to fig. 1, the method further includes: a first electrode 1, said first electrode 1 being in contact with said doped polysilicon layer 2. Further, the first electrode 1 is formed on the upper surface of the doped polysilicon layer 2 and extends to at least part of the side surface of the doped polysilicon layer 2, thereby further increasing the contact area between the first electrode 1 and the doped polysilicon layer and reducing the ohmic resistance therebetween.
According to further embodiments of the present invention, referring to fig. 1, the method further includes: a transparent conductive layer 7 and a second electrode 10, said transparent conductive layer 7 being on a surface of said doped amorphous silicon layer 9 remote from said intrinsic amorphous silicon layer 6, said second electrode 10 being in contact with said transparent conductive layer 7.
In yet another aspect of the invention, a method of making a bifacial hybrid solar cell is provided. According to an embodiment of the invention, a method comprises:
s100: providing a semiconductor substrate
In this step, a semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces, the first surface including adjacent first and second regions. The first surface of the semiconductor substrate is referred to as a light-receiving surface, and the second surface of the semiconductor substrate is referred to as a light-receiving surface.
Texturing the front surface prior to forming the doped poly finger on the front surface to form a pyramid-like structure on the front surface to reduce incident lightAnd the reflection improves the short-circuit current of the battery, and further improves the photoelectric conversion efficiency of the battery. Optionally, alkali solution such as sodium hydroxide, potassium hydroxide and the like can be used for alkali texturing treatment of the silicon wafer. As a specific example, bare monocrystalline silicon wafers are put into a groove type texturing cleaning machine for alkali texturing process, and the mass ratio of each component in texturing liquid is H 2 O: KOH: additive = 354:5.5:2, the main components of the additive comprising: the method comprises the steps of surfactant, nucleating agent, dispersing agent, catalyst and defoamer, wherein the temperature is 80+/-5 ℃, the process time is 400+/-200 s, the etching amount is 0.4+/-0.2 g, and the reflectivity of the front surface of the finally obtained monocrystalline silicon is 9+/-3%. Compared with the method, the method has the advantages that the front surface of the HJT battery needs to be provided with the passivation of the intrinsic amorphous silicon and the doped amorphous silicon, the requirement on the suede is higher, the reflectivity can reach 11+/-3%, and the reflectivity is 2% higher than that of the hybrid battery.
S200: sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface
In this step, a tunnel oxide layer and a doped polysilicon layer are sequentially deposited on the first surface. Specifically, the preparation of the tunneling oxide layer and the intrinsic or doped polysilicon (Poly) layer can be realized by adopting a deposition process such as LPCVD, PECVD, PVD, PEALD, and the deposition of the tunneling oxide layer and the polysilicon (Poly) layer is preferably performed by adopting LPCVD, wherein the deposition temperature of the tunneling oxide layer is 590+/-20 ℃, and the deposition temperature of the polysilicon (Poly) layer is 590+/-20 ℃.
For the preferential LPCVD deposition mode, a post-doping and annealing process is used, an intermediate after the deposition of the polysilicon (poly) layer is placed in a tubular diffusion furnace, a phosphorus-containing compound (such as phosphorus oxychloride) is introduced, and the polysilicon is converted into a phosphorus-doped polysilicon layer at a high temperature of 750-880 ℃; or by introducing a boron-containing compound (e.g., boron tribromide or boron trichloride) at a high temperature of 950-1050 c to convert the polysilicon into a boron-doped polysilicon layer. It should be noted that, in the phosphorus doping process of poly-Si, a PSG layer is naturally formed on the surface of the phosphorus doped polysilicon layer under the action of oxygen; and a BSG layer is naturally formed on the surface of the boron doped polysilicon layer under the action of oxygen in the boron doping process of poly-Si. The phosphorus doping concentration is 8E19-9E20cm -3 Preferably 3-9E20cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Boron (B)Has a doping concentration of 3-10E19cm -3 Preferably 6-10E19cm is used -3 。
S300: removing the doped polysilicon layer and the tunneling oxide layer corresponding to the second region, and removing the doped polysilicon layer and the tunneling oxide layer formed by the second surface and the side surface of the semiconductor substrate
Specifically, the method comprises the following steps:
s310: removing the doped oxide layer on the surface of the doped polysilicon layer corresponding to the second region;
and removing the doped oxide layer on the surface of the doped polysilicon layer corresponding to the second region by adopting laser. Specifically, for the phosphorus doped polysilicon layer, laser green light (532 nm) is used to etch away the PSG on its surface. For the boron doped polysilicon layer, ultraviolet (355 nm) picosecond and nanosecond laser is used to etch off the BSG on the surface. For the boron doped polysilicon layer, the BSG oxide layer removing treatment can be performed by adopting low-concentration hydrofluoric acid (4-8% by mass ratio), then the ultraviolet laser oxidation is performed on the surface of the doped polysilicon layer in the first area, a new oxide layer is formed on the surface of the doped polysilicon layer in the first area, and the non-laser area on the surface of the doped polysilicon layer in the second area is free of the oxide layer, so that the selective etching treatment is achieved.
S320: removing a doped oxide layer on the surface of the doped polysilicon layer formed by the second surface and the side surface coiling plating of the semiconductor substrate;
the method comprises the following steps: and (3) using a chain type cleaning machine, wherein the belt speed is 2m/min, the HF mass concentration is 5-10%, removing the doped oxide layer formed by back and side surface coiling plating, and protecting the oxide layer on the surface of the doped polysilicon layer in the first area by adopting a water film. For boron doped polysilicon layers, this step may be omitted if the BSG oxide layer removal process has been performed with low concentration hydrofluoric acid (4-8% by mass).
S330: removing a doped polysilicon layer formed on the second surface and the side surface of the semiconductor substrate in a winding manner, and the doped polysilicon layer corresponding to the second region;
the method comprises the following steps: the solution enters a groove type cleaning machine to remove the second surface and the side-wrapping poly layer (because a water film protects the oxide layer on the surface of the doped polysilicon layer of the first area, the oxide layer of the first area is used as a mask to protect the lower doped layer from being etched during the groove type cleaning), the main components of the solution are KOH solution with the mass concentration of 1-1.5 percent and protective additive with the mass concentration of 0.1-0.3 percent, and the additive mainly comprises: the surface active agent, the protective agent, the dispersing agent, the catalyst and the defoaming agent are used for removing the doped polysilicon layer formed by the second surface and the side surface coiling plating of the semiconductor substrate and the doped polysilicon layer corresponding to the second area at the temperature of 65610 ℃ for 300680 s. The protective additive serves to protect the tunnel oxide layer and the laser oxide layer from alkali damage.
S340: and removing the tunneling oxide layer formed on the second surface and the side surface of the semiconductor substrate by winding plating, the tunneling oxide layer corresponding to the second region, and the doped oxide layer on the surface of the doped polysilicon layer corresponding to the first region.
Specifically, the removal of the oxide layer of the first region and the tunneling layer of the second region, and the removal of the tunneling oxide layer formed by the second surface and the side-plating of the semiconductor substrate are completed in an HF solution tank (for example, 15-30% by mass concentration ratio) so that the surfaces thereof are rendered hydrophobic. After the poly is etched, a certain side etching phenomenon exists on the side edge of the poly, so that when an SEM (scanning electron microscope) test is performed, the internal local hollowed-out phenomenon exists in the poly finger region, and the cross section is uneven.
S400: sequentially forming an alumina layer and an anti-reflection layer in the second region
In this step, an alumina layer and an antireflection layer may be formed in this order in the second region by using PECVD, PEALD, ALD or the like. Preferably, a 9+ -5 nm aluminum oxide layer is deposited at 220+ -40 ℃ using a PEALD apparatus followed by a front side silicon nitride layer deposited at 530+ -50 ℃. After the deposition of the laminated film, the reflectance was 1.2% using a D8 reflectance tester, whereas the TCO back reflectance was 1.5% for a conventional HJT cell.
S500: sequentially forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the second surface
In the step, for the P-type silicon, an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer are sequentially formed on the second surface; for N-type silicon, an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer are sequentially formed on the second surface. Specifically, a CVD apparatus was used to deposit a-Si: H (i.e., intrinsic amorphous silicon layer i-a-Si) having a thickness of 10.+ -. 5nm and a P-a-Si: H (i.e., P-type amorphous silicon layer) having a thickness of 25.+ -. 5nm on the above second surface in this order, the deposition temperature of a-Si: H was 200.+ -. 20 ℃ and the deposition temperature of P-a-Si: H was 300.+ -. 30 ℃. For an N-type silicon wafer substrate, a-Si H (namely, a first intrinsic amorphous silicon layer i-a-Si) with the thickness of 10+/-5 nm and an N-a-Si H (namely, an N-type amorphous silicon layer) with the thickness of 15+/-5 nm are deposited, wherein the deposition temperature of the N-type amorphous silicon layer is 200+/-30 ℃.
Further, the method further comprises:
s600: preparation of the first electrode
Specifically, firstly, slotting by adopting laser, removing an alumina layer and an anti-reflection layer formed on a first area, and extending the slots to the side surfaces of the doped polysilicon layer so that the front surface and at least part of the side surfaces of the doped polysilicon layer are exposed; and then, preparing a first electrode by adopting a metal through screen printing or electroplating, vapor plating and other technologies, solidifying and annealing the first electrode to enable the first electrode to be in contact with the doped polysilicon layer and extend to the side face of the doped polysilicon layer. Therefore, the process for preparing the first electrode by low-temperature metallization can avoid the metallization compounding problem caused by high-temperature burn-through, and the parasitic absorption is improved to a certain extent by the scheme. The plating printing technology has extremely narrow gate line width, so that the optical effective area is further increased.
Further, the method further comprises:
s700: preparation of transparent conductive layer and second electrode
Specifically, a PVD or RPD device is firstly adopted to deposit a transparent conductive layer with a certain thickness on the surface of the doped amorphous silicon layer, and optionally, the material of the transparent conductive layer comprises at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide and indium tungsten oxide. And then preparing a second electrode on the surface of the transparent conductive layer, so that the second electrode is in contact with the transparent conductive layer.
According to the method provided by the embodiment of the invention, the parasitic light absorption of the front surface is reduced by forming the doped poly finger (namely the doped polysilicon layer) in the first area of the front surface, and the problem that the parasitic absorption is higher due to the comprehensive amorphous silicon of the front surface in the HJT battery is solved. And an alumina layer and an anti-reflection layer are formed in the second area of the front surface, and the second area is passivated, so that the recombination of the front surface is reduced, the service life of minority carriers is prolonged, and the reflectivity is further reduced. In addition, the doped polysilicon layer formed in the first area and the alumina layer formed in the second area have low cleaning requirements (compared with HJT batteries with high cleaning requirements on amorphous silicon passivation suede) so as to reduce the process difficulty.
The following detailed description of embodiments of the invention is provided for the purpose of illustration only and is not to be construed as limiting the invention. In addition, all reagents employed in the examples below are commercially available or may be synthesized according to methods herein or known, and are readily available to those skilled in the art for reaction conditions not listed, if not explicitly stated.
Example 1
The embodiment provides a P-type double-sided hybrid passivation contact back junction battery, which is prepared by the following steps:
1) And (3) wool making and cleaning: the bare monocrystalline silicon wafer is put into a groove type texturing cleaning machine for alkali texturing process, and the mass ratio of each component in texturing liquid medicine is H 2 O: KOH: additive = 354:5.5:2, the main components of the additive comprising: the method comprises the steps of surfactant, nucleating agent, dispersing agent, catalyst and defoamer, wherein the temperature is 80 ℃, the process time is 400s, the etching amount is 0.4g, and the reflectivity of the front surface of the finally obtained monocrystalline silicon is 9%.
2) Depositing poly Si: and depositing a tunneling oxide layer and a polycrystalline silicon (poly) layer on the first surface by LPCVD, wherein the deposition temperature of the tunneling oxide layer is 590 ℃, and the deposition temperature of the polycrystalline silicon (poly) layer is 590 ℃. Wherein the tunneling silicon oxide deposition thickness is 1.5nm and the poly silicon thickness is 40nm.
3) Forming a boron doped polysilicon layer: introducing boron-containing compound (boron trichloride), converting polysilicon into boron-doped polysilicon layer at 1000deg.C, and testing its doping concentration to 8E19cm -3 。
4) Removing an oxidation layer: and (3) using a groove type cleaning machine to acid-wash for 200s in hydrofluoric acid solution with the mass concentration ratio of 15% to remove the BSG oxide layer on the surface of the boron doped polysilicon layer.
5) Laser oxidation poly: and oxidizing the surface of the boron doped polysilicon layer in the first area by using ultraviolet (355 nm) laser, and forming a new oxide layer on the surface of the doped polysilicon layer in the first area.
6) Alkali etching: the polymer layer which is coated on the second surface and the side surface is removed by a groove type cleaning machine, the main components of the solution are KOH solution with the mass concentration of 1.5 percent and protective additive with the mass concentration of 0.3 percent, and the additive mainly comprises: surfactant, protectant (isomeric tridecanol polyoxyethylene, gum arabic, etc.), dispersant, catalyst and defoamer, the temperature is 65 ℃ and the cleaning time is 300s, and simultaneously the second surface and the side surface are removed from plating poly and the residual poly in the second area; finally, the removal of the oxide layer of the first area and the tunneling layer of the second area, and the removal of the tunneling oxide layer formed by the second surface and the side surface of the semiconductor substrate by the around plating are completed in an HF solution tank with the mass concentration ratio of 4%, so that the surface of the tunneling oxide layer reaches the hydrophobicity.
7) And (3) front surface coating: a PEALD apparatus was used to deposit 5nm of aluminum oxide in the second region at 200 ℃ followed by deposition of a silicon nitride anti-reflective film at 530 ℃.
8) Deposition of n-a-si: a low temperature CVD apparatus was used to deposit a-si: H of 10nm thickness and n-a-si: H of 15nm thickness on the second surface. The deposition temperature of a-si: H was 200℃and the deposition temperature of n-a-si: H was 200 ℃.
9) Back-side deposited TCO: an 80nm indium tin oxide layer was deposited on the back of the cell using PVD equipment.
10 Preparing a metallized electrode by adopting an electroplating technology, solidifying and annealing.
Example 2
The embodiment provides an N-type double-sided hybrid passivation contact back junction battery, which is prepared by the following steps:
1) And (3) wool making and cleaning: the bare monocrystalline silicon wafer is put into a groove type texturing cleaning machine for alkali texturing process, and the mass ratio of each component in texturing liquid medicine is H 2 O: KOH: additive = 354:5.5:2, the main components of the additive comprising: the method comprises the steps of surfactant, nucleating agent, dispersing agent, catalyst and defoamer, wherein the temperature is 85 ℃, the process time is 500s, the etching amount is 0.46g, and the reflectivity of the front surface of the finally obtained monocrystalline silicon is 8%.
2) Depositing poly Si: and depositing a tunneling oxide layer and a polycrystalline silicon (poly) layer on the first surface by LPCVD, wherein the deposition temperature of the tunneling oxide layer is 590 ℃, and the deposition temperature of the polycrystalline silicon (poly) layer is 590 ℃. Wherein the tunneling silicon oxide deposition thickness is 1.5nm and the poly silicon thickness is 40nm.
3) Forming a phosphorus doped polysilicon layer, introducing phosphorus compound (phosphorus oxychloride), converting polysilicon into phosphorus doped polysilicon layer at 800deg.C, and testing the doping concentration of 8E20cm -3 。
4) And (3) grooving the PSG on the surface of the doped polysilicon layer in the second region by using green light (532 nm) picosecond laser, wherein the non-grooving region is a grid line region. After grooving, the silicon oxide in the front grooving area is removed.
5) Selective etching (phosphorus doped poly): firstly, using a chain type cleaning machine, wherein the belt speed is 2m/min, the HF mass concentration is 8%, removing doped oxide layers formed by back and side surface coiling plating, and protecting the oxide layers on the surface of the doped polysilicon layer in the first area by adopting a water film; then the solution enters a groove type cleaning machine to remove the second surface and the side-wrapping plating poly layer, wherein the main components of the solution are KOH solution with the mass concentration of 1.5 percent and protective additive with the mass concentration of 0.3 percent, and the additive mainly comprises: a surfactant, a protective agent, a dispersing agent, a catalyst and a defoaming agent, wherein the temperature is 65 ℃, the cleaning time is 300s, and the second surface and the side wrapping poly and the residual poly in the second area are removed; finally, the removal of the oxide layer of the first area and the tunneling layer of the second area, and the removal of the tunneling oxide layer formed by the second surface and the side surface of the semiconductor substrate by the around plating are completed in an HF solution tank with the mass concentration ratio of 4%, so that the surface of the tunneling oxide layer reaches the hydrophobicity.
6) And (3) front surface coating: a PEALD apparatus was used to deposit 5nm of aluminum oxide in the second region at 200 ℃ followed by deposition of a silicon nitride anti-reflective film at 530 ℃.
7) Deposition of p-a-si: a low temperature CVD apparatus was used to deposit a-si: H of 10nm thickness and p-a-si: H of 25nm thickness on the second surface. The deposition temperature of a-si: H was 200℃and the deposition temperature of p-a-si: H was 300 ℃.
8) Back-side deposited TCO: an 80nm indium tin oxide layer was deposited on the back of the cell using PVD equipment.
9) And (3) adopting an electroplating technology to finish the preparation of the metallized electrode, solidifying and annealing.
Example 3
This embodiment differs from embodiment 1 only in that:
the thickness of the tunneling silicon oxide deposition is 1.5nm, the thickness of the boron doped polysilicon layer is 30nm, and the thickness of the aluminum oxide layer is 10nm; the thickness of the a-si H layer is 5nm; the thickness of the n-a-si H layer was 10nm.
The other steps were the same as in example 1.
Example 4
This embodiment differs from embodiment 2 only in that:
the thickness of the tunneling silicon oxide deposition is 1.5nm; the thickness of the phosphorus doped polysilicon layer is 50nm, the thickness of the aluminum oxide layer is 14nm, the thickness of the a-si: H layer is 15nm, and the thickness of the p-a-si: H layer is 20nm.
The other steps were the same as in example 2.
Comparative example 1
The comparative example provides a preparation method of an N-type HJT solar cell, which comprises the following steps:
and (5) texturing and cleaning, namely, double-sided texturing after the damage of the silicon wafer is removed.
Depositing intrinsic amorphous silicon and doped amorphous silicon by front and back low temperature CVD;
front-side and back-side PVD deposition of indium tin oxide.
The other matters were the same as in example 2.
Comparative example 2
This comparative example provides an N-type TOPCon battery comprising the steps of:
1) The silicon wafer is subjected to texturing treatment, the volume of a Jiejia creating 400-piece groove is 360L, and the texturing formula is as follows: KOH 5.8L, time TS 55.3L, and at 82 ℃, the silicon wafer with the resistivity of 0.6 omega is subjected to 460s texturing, the reflectivity after the texturing is 8.5 percent, and the weight is reduced by 0.45g.
2) And carrying out boron diffusion treatment on the front surface so as to form a boron doped layer on the front surface of the silicon wafer. The boron diffusion adopts trimethyl borate as a boron source; the process temperature of boron diffusion is 1000 ℃, and the post-boron diffusion resistance is 150Ω/≡.
3) Mixing hydrofluoric acid with the mass fraction of 49%, nitric acid with the mass fraction of 69% and deionized water in the ratio of HF to HNO3 to DIW of 1 to 4 to 1, and etching the back surface of the silicon wafer to ensure that the back surface reflectivity of the silicon wafer after etching is 36% and the weight loss of the silicon wafer in the etching process is 0.45g.
4) The tunnel oxide layer thickness was 1.45nm and the poly thickness was 250nm by LPCVD deposition on the back side. Adopts LPCVD phosphorus expansion mode to dope phosphorus on the back side poly, and the phosphorus concentration after doping is 6e20cm -3 。
5) Using a chain cleaner, the belt speed was 2m/Min, and the HF (feed liquid concentration was: 49%) concentration ratio is 7%, removing the back PSG layer, then entering a 360L groove type cleaning machine to remove the winding plating poly layer, and the solution ratio is 18L KOH+3L Tong BP series protection additive. The front side is cleaned at 75 ℃ for 250s to complete the poly removal and the laser region poly removal for front side cladding.
6) And performing single-plug double plating by using micro-conductive ALD to passivate the front and back surfaces of the silicon wafer, wherein the thickness is 5nm.
7) Front side SINx deposition was performed using PECVD with a thickness of 75nm, refractive index of 2.09, back side 30nm SINx, refractive index of 2.3.
8) And (5) printing, testing and sorting the battery pieces.
Comparative example 3
This comparative example provides an N-type hybrid battery (front-side all-sided N-poly) comprising the steps of:
1) And (3) wool making and cleaning: the bare monocrystalline silicon wafer is put into a groove type texturing cleaning machine for alkali texturing process, and the mass ratio of each component in texturing liquid medicine is H2O: KOH: additive = 354:5.5:2, the main components of the additive comprising: the method comprises the steps of surfactant, nucleating agent, dispersing agent, catalyst and defoamer, wherein the temperature is 85 ℃, the process time is 500s, the etching amount is 0.46g, and the reflectivity of the front surface of the finally obtained monocrystalline silicon is 8%.
2) Depositing poly Si: and depositing a tunneling oxide layer and a polycrystalline silicon (poly) layer on the first surface by LPCVD, wherein the deposition temperature of the tunneling oxide layer is 590 ℃, and the deposition temperature of the polycrystalline silicon (poly) layer is 590 ℃. Wherein the tunneling silicon oxide deposition thickness is 1.5nm and the poly silicon thickness is 40nm.
3) Forming a phosphorus doped polysilicon layer, introducing phosphorus compound (phosphorus oxychloride), converting polysilicon into phosphorus doped polysilicon layer at 800deg.C, and testing the doping concentration of 8E20cm -3 。
4) Using a chain cleaner, the belt speed was 2m/Min, and the HF (feed liquid concentration was: 49 percent) concentration ratio is 7 percent, the front PSG layer is removed, then the solution enters a 360L groove type cleaning machine to remove the winding plating poly layer, and the solution is prepared from 18L KOH+3L Tong BP series protection additive. The front side is cleaned at 75 ℃ for 250s to complete the poly removal and the laser region poly removal for front side cladding.
5) And (3) front surface coating: an 80nm silicon nitride antireflective film was deposited at 460 c using a PECVD apparatus.
6) Deposition of p-a-si: a low temperature CVD apparatus was used to deposit a-si: H of 10nm thickness and p-a-si: H of 25nm thickness on the second surface. The deposition temperature of a-si: H was 200℃and the deposition temperature of p-a-si: H was 300 ℃.
7) Back-side deposited TCO: an 80nm indium tin oxide layer was deposited on the back of the cell using PVD equipment.
8) Screen printing: and (3) adopting an electroplating technology to finish the preparation of the metallized electrode, solidifying and annealing.
The solar cells prepared in examples 1 to 4 and comparative examples 1 to 3 were respectively subjected to performance tests of energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, and fill factor FF, and the results are shown in table 1.
TABLE 1
| Project | Eta(％) | Uoc(V) | Isc(A) | FF(％) |
| Example 1 | 25.62 | 0.745 | 11.53 | 83.50 |
| Example 2 | 26.19 | 0.749 | 11.62 | 84.00 |
| Example 3 | 26.23 | 0.745 | 11.58 | 83.78 |
| Example 4 | 26.17 | 0.747 | 11.54 | 83.45 |
| Comparative example 1 | 25.09 | 0.74 | 11.20 | 83.10 |
| Comparative example 2 | 24.72 | 0.721 | 11.34 | 83.50 |
| Comparative example 3 | 23.70 | 0.744 | 10.52 | 83.80 |
It can be seen that the open voltage of examples 1-4 was not significantly reduced and the current (ISC) was significantly increased by about 0.4A as compared to the HJT cell of comparative example 1. Examples 1-4 have higher open voltage performance than the N-type TOPCon cell of comparative example 2, and the current is not significantly reduced, even higher than the SE-free TOPCon cell. Compared with the N-type all-round N-poly battery of comparative example 3, the current of examples 1-4 is 1A higher, the efficiency is nearly 2% higher, i.e. the situation that the all-round doped polysilicon can greatly reduce the parasitic absorption is avoided, thereby improving the battery efficiency.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (15)
1. A bifacial hybrid solar cell comprising:
a semiconductor substrate having opposing first and second surfaces, the first surface comprising adjacent first and second regions;
a tunneling oxide layer on the first region and a doped polysilicon layer on a surface of the tunneling oxide layer remote from the semiconductor substrate;
an aluminum oxide layer on the second region and an anti-reflection layer on a surface of the aluminum oxide layer remote from the semiconductor substrate;
an intrinsic amorphous silicon layer and a doped amorphous silicon layer, the doped polysilicon layer being of opposite conductivity type to the doped amorphous silicon layer, the intrinsic amorphous silicon layer being on the second region, the doped amorphous silicon layer being on a surface of the intrinsic amorphous silicon layer remote from the semiconductor substrate.
2. The bifacial hybrid solar cell according to claim 1, further comprising: and the first electrode is contacted with the doped polysilicon layer.
3. The bifacial hybrid solar cell of claim 2, wherein the first electrode is formed on an upper surface of the doped polysilicon layer and extends to at least a portion of a side of the doped polysilicon layer.
4. The bifacial hybrid solar cell according to claim 1, further comprising: a transparent conductive layer on a surface of the doped amorphous silicon layer remote from the intrinsic amorphous silicon layer, and a second electrode in contact with the transparent conductive layer.
5. The bifacial hybrid solar cell according to claim 1 wherein said doped amorphous silicon layer is a P-type doped amorphous silicon layer and said doped polysilicon layer is an N-type doped polysilicon layer;
or the doped amorphous silicon layer is an N-type doped amorphous silicon layer, and the doped polysilicon layer is a P-type doped polysilicon layer.
6. The bifacial hybrid solar cell according to claim 1, wherein,
the thickness of the tunneling oxide layer is 1.2-3.5nm, preferably 1.5-2.5nm;
and/or the thickness of the doped polysilicon layer is 30-270 nm; preferably 30-50nm.
7. The bifacial hybrid solar cell according to claim 1, wherein,
the thickness of the intrinsic amorphous silicon layer is 5-15 nm;
and/or the doped amorphous silicon layer is a P-type doped amorphous silicon layer, the thickness of the P-type doped amorphous silicon layer is 20-30nm, or the doped amorphous silicon layer is an N-type doped amorphous silicon layer, and the thickness of the N-type doped amorphous silicon layer is 10-20nm.
8. The bifacial hybrid solar cell according to claim 1, wherein the thickness of the aluminum oxide layer is 4-14nm.
9. A method of making the bifacial hybrid solar cell of any one of claims 1-8, comprising:
providing a semiconductor substrate having opposite first and second surfaces, the first surface including adjacent first and second regions;
sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface;
removing the doped polysilicon layer and the tunneling oxide layer corresponding to the second region, and removing the doped polysilicon layer and the tunneling oxide layer formed on the second surface and the side surface of the semiconductor substrate by winding plating;
sequentially forming an alumina layer and an anti-reflection layer in the second region;
and forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the second surface in sequence.
10. The method as recited in claim 9, further comprising:
a first electrode is prepared and is brought into contact with the doped polysilicon layer.
11. The method as recited in claim 9, further comprising:
forming a transparent conductive layer on a surface of the doped amorphous silicon layer remote from the intrinsic amorphous silicon layer;
and preparing a second electrode, and enabling the second electrode to be in contact with the transparent conductive layer.
12. The method of claim 9, wherein the tunnel oxide layer and the doped polysilicon layer are formed using LPCVD, PECVD, PVD or PEALD, respectively.
13. The method of claim 9, wherein the removing the doped polysilicon layer and the tunnel oxide layer corresponding to the second region, and removing the doped polysilicon layer and the tunnel oxide layer formed by the second surface and the side-by-side plating of the semiconductor substrate comprises the steps of:
removing the doped oxide layer on the surface of the doped polysilicon layer corresponding to the second region;
removing a doped oxide layer on the surface of the doped polysilicon layer formed by the second surface and the side surface coiling plating of the semiconductor substrate;
removing a doped polysilicon layer formed on the second surface and the side surface of the semiconductor substrate in a winding manner, and the doped polysilicon layer corresponding to the second region;
and removing the tunneling oxide layer formed on the second surface and the side surface of the semiconductor substrate by winding plating, the tunneling oxide layer corresponding to the second region, and the doped oxide layer on the surface of the doped polysilicon layer corresponding to the first region.
14. The method of claim 9, wherein the aluminum oxide layer and the anti-reflective layer are formed by deposition using PECVD, PEALD, or ALD, respectively.
15. The method of claim 9, wherein the intrinsic amorphous silicon layer and the doped amorphous silicon layer are formed by deposition using a CVD apparatus, respectively.
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