CN118016733A - Solar cell and method for manufacturing solar cell - Google Patents

Solar cell and method for manufacturing solar cell Download PDF

Info

Publication number
CN118016733A
CN118016733A CN202410415038.9A CN202410415038A CN118016733A CN 118016733 A CN118016733 A CN 118016733A CN 202410415038 A CN202410415038 A CN 202410415038A CN 118016733 A CN118016733 A CN 118016733A
Authority
CN
China
Prior art keywords
layer
doping
doped polysilicon
gate line
line region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202410415038.9A
Other languages
Chinese (zh)
Other versions
CN118016733B (en
Inventor
韩秉伦
柳伟
陈达明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Trina Solar Co Ltd
Original Assignee
Trina Solar Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Trina Solar Co Ltd filed Critical Trina Solar Co Ltd
Priority to CN202410415038.9A priority Critical patent/CN118016733B/en
Publication of CN118016733A publication Critical patent/CN118016733A/en
Application granted granted Critical
Publication of CN118016733B publication Critical patent/CN118016733B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The application discloses a solar cell and a preparation method of the solar cell, and belongs to the technical field of solar cells. The solar cell includes: the semiconductor device comprises a silicon substrate, a first tunneling oxide layer, a first doped polysilicon layer, a first grid line, a transparent conductive medium layer and a first passivation layer, wherein the first doped polysilicon layer is divided into a first grid line area and a first non-grid line area, the first grid line is located in the first grid line area, the transparent conductive medium layer is located in the first non-grid line area, and the band gap width of the transparent conductive medium layer is different from that of the first doped polysilicon layer. According to the solar cell, the first doped polysilicon layers and the transparent conductive medium layers with different band gap widths are arranged in the front non-grid line area, so that larger band offset is formed, reverse saturation current is reduced, passivation performance of the cell is effectively improved, front shading area can be reduced by the transparent conductive medium layer, contact resistance is reduced, and conversion efficiency of the cell is effectively improved.

Description

Solar cell and method for manufacturing solar cell
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to a solar cell and a preparation method of the solar cell.
Background
The tunneling oxidation passivation contact (TOPCon) battery is one of solar batteries, and a passivation contact structure is formed by the tunneling oxide layer and the doped polysilicon layer, so that electron-hole recombination is reduced, the open-circuit voltage and short-circuit current of the battery are improved, and the solar battery has the characteristics of high conversion efficiency, low attenuation performance, high mass production cost performance and the like.
The theoretical limit efficiency of TOPCon cells reaches 28.7%, approaching the efficiency limit 29.43% of crystalline silicon photovoltaic cells, and the parasitic absorption of sunlight and the passivation performance of cells are important factors affecting the final conversion efficiency of TOPCon cells. At present, the parasitic absorption of light is mostly reduced through doping concentration, but the improvement of passivation performance of the battery by the technology is limited, and the final conversion efficiency of the battery is lower.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides the solar cell and the preparation method of the solar cell, which can enhance the passivation performance of the cell and help to improve the conversion efficiency of the cell.
In a first aspect, the present application provides a solar cell comprising:
a silicon substrate;
the first tunneling oxide layer is arranged on the light-receiving surface of the silicon substrate;
The first doped polysilicon layer is arranged on one surface of the first tunneling oxide layer, which is far away from the silicon substrate, and is divided into a first grid line area and a first non-grid line area, and the first doped polysilicon layer comprises a first doping element;
the first grid line is arranged on one surface of the first doped polysilicon layer, which is far away from the first tunneling oxide layer, and is positioned in the first grid line area;
The transparent conductive medium layer is arranged on one surface of the first doped polycrystalline silicon layer, which is far away from the first tunneling oxide layer, and is positioned in the first non-grid line area, and the band gap width of the transparent conductive medium layer is different from that of the first doped polycrystalline silicon layer;
the first passivation layer is arranged on one surface, far away from the first doped polycrystalline silicon layer, of the transparent conductive medium layer.
According to the solar cell, the first doped polycrystalline silicon layer and the transparent conductive medium layer are arranged in the non-grid line area on the front side of the cell to be in contact, the band gap widths of the first doped polycrystalline silicon layer and the transparent conductive medium layer are different, so that larger energy band offset is formed, reverse saturation current is reduced, passivation performance of the cell is effectively improved, the front side shading area can be reduced, contact resistance is reduced, and conversion efficiency of the cell is effectively improved.
According to one embodiment of the present application, further comprising:
The second tunneling oxide layer is arranged on the backlight surface of the silicon substrate;
The second doped polysilicon layer is arranged on one surface of the second tunneling oxide layer, which is far away from the silicon substrate, and comprises a second doping element with the doping type opposite to that of the first doping element, and the second doped polysilicon layer is divided into a second grid line region and a second non-grid line region;
the second grid line is arranged on one surface of the second doped polysilicon layer, which is far away from the second tunneling oxide layer, and is positioned in the second grid line area;
The second passivation layer is arranged on one surface of the second doped polysilicon layer, which is away from the second tunneling oxide layer, and is positioned in the second non-gate line region.
According to one embodiment of the present application, the second gate line region further includes a third doping element.
According to an embodiment of the present application, the third doping element is an oxygen element.
According to one embodiment of the present application, the doping concentration of the second doping element in the second gate line region is greater than the doping concentration of the second doping element in the second non-gate line region.
According to one embodiment of the present application, the doping concentration of the first doping element in the first gate line region is greater than the doping concentration of the first doping element in the first non-gate line region.
According to one embodiment of the application, the transparent conductive dielectric layer is a transparent conductive oxide film.
In a second aspect, the present application provides a method for manufacturing a solar cell, the method comprising:
Preparing a first tunneling oxide layer on a light receiving surface of a silicon substrate, and preparing a first precursor layer on one surface of the first tunneling oxide layer far away from the silicon substrate;
Doping the first precursor layer by using a first doping element to obtain a first doped polysilicon layer, wherein the first doped polysilicon layer is divided into a first grid line region and a first non-grid line region;
preparing a transparent conductive medium layer in the first non-gate line region of the first doped polysilicon layer far away from one side of the first tunneling oxide layer, wherein the band gap width of the transparent conductive medium layer is different from that of the first doped polysilicon layer;
preparing a first passivation layer on one surface of the transparent conductive medium layer, which is far away from the first doped polysilicon layer, and preparing a first grid line in the first grid line area on one surface of the first doped polysilicon layer, which is far away from the first tunneling oxide layer.
According to the preparation method of the solar cell, the first doped polysilicon layer and the transparent conductive medium layer are arranged in the front non-grid line area of the cell to be in contact, the band gap widths of the first doped polysilicon layer and the transparent conductive medium layer are different, so that larger energy band offset is formed, reverse saturation current is reduced, passivation performance of the cell is effectively improved, front shading area can be reduced by the transparent conductive medium layer, contact resistance is reduced, and conversion efficiency of the cell is effectively improved.
According to one embodiment of the application, the method further comprises:
preparing a second tunneling oxide layer on the backlight surface of the silicon substrate, and preparing a second precursor layer on the surface, far away from the silicon substrate, of the second tunneling oxide layer;
doping the second precursor layer by using a second doping element with the doping type opposite to that of the first doping element to obtain a second doped polysilicon layer, wherein the second doped polysilicon layer is divided into a second grid line region and a second non-grid line region;
preparing a second grid electrode in the second grid line area of one surface of the second doped polycrystalline silicon layer far away from the second tunneling oxide layer, and preparing a second passivation layer in the second non-grid line area of one surface of the second doped polycrystalline silicon layer far away from the second tunneling oxide layer.
According to one embodiment of the present application, the doping of the second precursor layer with a second doping element of opposite doping type to the first doping element comprises:
Performing diffusion of the second doping element on the second precursor layer;
performing laser die sinking on the second grid line area;
and doping the second doping element and the third doping element in the second grid line region.
According to an embodiment of the present application, the doping of the second doping element and the third doping element in the second gate line region includes:
And taking the second doping element and the third doping element as doping sources, and generating the second doped polysilicon layer through plasma enhanced chemical vapor deposition.
According to one embodiment of the present application, the doping concentration of the second doping element in the second gate line region is greater than the doping concentration of the second doping element in the second non-gate line region.
According to one embodiment of the present application, the doping concentration of the first doping element in the first gate line region is greater than the doping concentration of the first doping element in the first non-gate line region.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a solar cell according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a solar cell according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a method for manufacturing a solar cell according to an embodiment of the present application;
Fig. 5 is a second schematic structural diagram of a method for manufacturing a solar cell according to an embodiment of the present application.
Reference numerals:
the silicon substrate 100, the first tunnel oxide layer 210, the first gate line region 221, the first non-gate line region 222, the first gate line 230, the transparent conductive dielectric layer 240, the first passivation layer 260,
The second tunnel oxide layer 310, the first silicon oxide film layer 311, the second silicon oxide film layer 312, the second doped polysilicon layer 320, the second gate line region 321, the second non-gate line region 322, the second gate line 330, and the second passivation layer 340.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
A solar cell and a method of manufacturing the solar cell according to an embodiment of the present application are described below with reference to fig. 1 to 5.
As shown in fig. 1, the solar cell according to the embodiment of the present application may include: the first tunneling oxide layer 210, the first doped polysilicon layer, the first gate line 230, the transparent conductive medium layer 240, and the first passivation layer 260.
In this embodiment, the first tunneling oxide layer 210 is disposed on the light receiving surface of the silicon substrate 100, and the first doped polysilicon layer is disposed on a surface of the first tunneling oxide layer 210 away from the silicon substrate 100.
Wherein the first tunneling oxide layer 210 and the first doped polysilicon layer form a passivation contact structure.
In actual implementation, the silicon substrate 100 may be an N-type silicon wafer or a P-type silicon wafer; the first tunneling oxide layer 210 may be silicon oxide; the first doped polysilicon layer may be an N-type doped polysilicon layer or a P-type doped polysilicon layer.
The first doped polysilicon layer includes a first doping element, which may be phosphorus when the first doped polysilicon layer is an N-type doped polysilicon layer, and boron when the first doped polysilicon layer is a P-type doped polysilicon layer.
In this embodiment, the first doped polysilicon layer is divided into a first gate line region 221 and a first non-gate line region 222, wherein the first gate line region 221 is a region of the first doped polysilicon layer in contact with the first gate line 230, and the first non-gate line region 222 is a region of the first doped polysilicon layer without the first gate line 230.
The first gate line 230 is disposed on a surface of the first doped polysilicon layer away from the first tunneling oxide layer 210 and is located in the first gate line region 221.
In actual implementation, the first gate line 230 may be printed with a metal material such as silver paste, copper paste, or the like.
In this embodiment, the solar cell is further provided with a transparent conductive dielectric layer 240, and the transparent conductive dielectric layer 240 is disposed on a surface of the first doped polysilicon layer away from the first tunneling oxide layer 210 and is located in the first non-gate line region 222.
The transparent conductive dielectric layer 240 is a transparent and conductive dielectric layer in the first non-gate line region 222, and the transparent conductive dielectric layer 240 covers the first non-gate line region 222 and does not block sunlight entering the first doped polysilicon layer.
In this embodiment, the first passivation layer 260 is disposed on a surface of the transparent conductive medium layer 240 away from the first doped polysilicon layer, and the transparent conductive medium layer 240 is disposed between the first doped polysilicon layer and the first passivation layer 260.
The first passivation layer 260 may be made of silicon nitride, silicon oxide, or aluminum oxide.
It should be noted that, the band gap width of the transparent conductive medium layer 240 is different from the band gap width of the first doped polysilicon layer, and a larger energy band offset is formed between the first doped polysilicon layer and the transparent conductive medium layer 240, so that the recombination of electrons and holes can be effectively reduced, and the passivation performance of the solar cell can be enhanced.
The stacked first doped polysilicon layer and the transparent conductive medium layer 240 may further form a heterojunction structure, so that reverse saturation current is reduced, and the conductivity of the transparent conductive medium layer 240 may enhance the lateral transmission capability of carriers, thereby being beneficial to reducing the gate line density of the first gate line 230 on the front side of the solar cell, reducing reverse saturation current and light shielding area, and maintaining smaller contact resistance.
According to the solar cell provided by the embodiment of the application, the first doped polysilicon layer and the transparent conductive medium layer 240 are arranged in the non-grid line area on the front side of the cell to be in contact, so that the band gap widths of the first doped polysilicon layer and the transparent conductive medium layer 240 are different, larger energy band offset is formed, reverse saturation current is reduced, passivation performance of the cell is effectively improved, front side shading area of the transparent conductive medium layer 240 can be reduced, contact resistance is reduced, and conversion efficiency of the cell is effectively improved.
In some embodiments, the doping concentration of the first doping element in the first gate line region 221 is greater than the doping concentration of the first doping element in the first non-gate line region 222.
In this embodiment, the first gate line region 221 is set to be a heavy doping concentration, so that the contact performance between the first doped polysilicon layer at the first gate line region 221 and the first gate line 230 can be effectively improved, and the first non-gate line region 222 is set to be a low doping concentration, so that the parasitic absorption at the first non-gate line region 222 can be effectively reduced, and the battery conversion efficiency can be improved.
It should be noted that, the reverse saturation current is related to the doping concentration, the first non-gate line region 222 is set to have a low doping concentration, and the transparent conductive medium layer 240 with different band gap widths is disposed on the first non-gate line region 222, so as to form a larger energy band offset, thereby effectively reducing the reverse saturation current and improving the passivation performance of the battery.
The first non-gate line region 222 with a large area on the front surface of the solar cell is composed of a first doped polysilicon layer with a low doping concentration and a transparent conductive medium layer 240, the parasitic absorption is reduced by the low doping concentration, passivation performance is enhanced by the first doped polysilicon layer and the transparent conductive medium layer 240, the first gate line region 221 is a first doped polysilicon layer with a heavy doping concentration, and the heavy doping concentration is easy to form excellent contact with the first gate line 230, so that contact resistance of the cell is reduced.
In some embodiments, transparent conductive dielectric layer 240 is a transparent conductive oxide film.
Wherein, the transparent conductive oxide (TRANSPARENT CONDUCTIVE OXIDE, TCO) film mainly comprises oxides of indium (In), tin (Sn), antimony (Sb), zinc (Zn) and cadmium (Cd) and composite multi-oxide film materials thereof.
For example, the transparent conductive dielectric layer 240 may be Indium Tin Oxide (ITO) having a composition of indium oxide (In 2O3) and tin oxide (SnO 2).
It is understood that the solar cell includes the first tunneling oxide layer 210 and the first doped polysilicon layer to form a passivation contact structure, and the solar cell belongs to TOPCon cells, and the solar cell may be a double sided poly TOPCon cell.
In some embodiments, as shown in fig. 2, the solar cell may further include a second tunnel oxide layer 310, a second doped polysilicon layer 320, a second gate line 330, and a second passivation layer 340.
In this embodiment, the second tunneling oxide layer 310 is disposed on the back surface of the silicon substrate 100, and the second doped polysilicon layer 320 is disposed on the surface of the second tunneling oxide layer 310 away from the silicon substrate 100.
Wherein the second tunnel oxide layer 310 and the second doped polysilicon layer 320 form a passivation contact structure.
In actual implementation, the second tunnel oxide layer 310 may be silicon oxide; the second doped polysilicon layer 320 may be an N-type doped polysilicon layer or a P-type doped polysilicon layer.
The second doped polysilicon layer 320 includes a second doping element having a doping type opposite to that of the first doping element, and when the first doped polysilicon layer is an N-type doped polysilicon layer, the first doping element may be phosphorus, the second doped polysilicon layer 320 is a P-type doped polysilicon layer, and the second doping element may be boron; when the first doped polysilicon layer is a P-type doped polysilicon layer, the first doping element may be boron, the second doped polysilicon layer 320 is an N-type doped polysilicon layer, and the second doping element may be phosphorus.
As shown in fig. 3, the second doped polysilicon layer 320 is divided into a second gate line region 321 and a second non-gate line region 322, wherein the second gate line region 321 is a region of the second doped polysilicon layer 320 in contact with the second gate line 330, and the second non-gate line region 322 is a region of the second doped polysilicon layer 320 without the second gate line 330.
The second gate line 330 is disposed on a surface of the second doped polysilicon layer 320 away from the second tunneling oxide layer 310 and is located in the second gate line region 321.
In practical implementation, the second gate line 330 may be printed with a metal material such as silver paste, copper paste, or the like.
In this embodiment, the second passivation layer 340 is disposed on a surface of the second doped polysilicon layer 320 facing away from the second tunneling oxide layer 310 and is located in the second non-gate line region 322, where the second passivation layer 340 may be made of a material such as silicon nitride, silicon oxide or aluminum oxide.
The double-sided poly TOPCon battery has 28.5% of theoretical conversion efficiency, and the front polysilicon has large parasitic absorption of light, poor passivation contact performance and influences the conversion efficiency of the battery.
In the embodiment of the application, the first non-gate line region 222 on the light-receiving front surface of the solar cell is composed of the first doped polysilicon layer with low doping concentration and the transparent conductive medium layer 240, the parasitic absorption is reduced by the low doping concentration, the passivation performance can be effectively enhanced by the band gap difference between the first doped polysilicon layer and the transparent conductive medium layer 240, the first gate line region 221 is the first doped polysilicon layer with high doping concentration, excellent contact is formed between the first doped polysilicon layer and the first gate line 230, the contact resistance of the cell is reduced, and the conversion efficiency of the double-sided poly TOPCon cell is effectively improved.
In some embodiments, the second gate line region 321 further includes a third doping element.
It should be noted that the second doping element and the third doping element are different elements, and have a difference, and doping the third doping element into the second gate line region 321 can properly reduce the doping concentration of the second doping element of N type or P type, and form an energy band offset at the same time, so as to effectively improve the contact performance.
In some embodiments, the third doping element is an oxygen element.
In this embodiment, at the second gate line region 321 in contact with the gate line, the doping element of the second doped polysilicon layer 320 includes a third doping element, i.e., an oxygen element, in addition to the second doping element of N-type or P-type, and the doped oxygen element can effectively reduce the contact resistance between the second doped polysilicon layer 320 and the second gate line 330, thereby improving the conversion efficiency of the battery.
In practical implementation, when doping the second gate line region 321, an oxygen-containing doping source such as carbon dioxide (CO 2) may be added to dope the N-type or P-type doping source, so as to dope the oxygen element.
In some embodiments, the doping concentration of the second doping element in the second gate line region 321 is greater than the doping concentration of the second doping element in the second non-gate line region 322.
In this embodiment, the second gate line region 321 is set to a heavy doping concentration, so that the contact performance between the second doped polysilicon layer 320 and the second gate line 330 at the second gate line region 321 can be effectively improved, and the second non-gate line region 322 is set to a low doping concentration, so that the parasitic absorption at the second non-gate line region 322 can be effectively reduced, and the conversion efficiency of the battery can be improved.
In practical implementation, the second non-gate line region 322 adopts low doping concentration to ensure low parasitic absorption, and the second gate line region 321 can increase oxygen doping, improve contact performance and improve battery conversion efficiency.
In the solar cell of the embodiment of the application, the first non-gate line region 222 of the light receiving surface is set to be the first doped polysilicon layer with low doping concentration and the transparent conductive medium layer 240, the low doping concentration effectively reduces parasitic absorption, the first doped polysilicon layer with different band gaps and the transparent conductive medium layer 240 can effectively enhance passivation performance, the first gate line region 221 is formed by the first doped polysilicon layer with heavy doping concentration and forms good contact with the first gate line 230, and the contact resistance of the cell is reduced;
The second non-grid line area 322 of the back surface is set to be low doping concentration, the second grid line area 321 is set to be heavy doping concentration, passivation performance of the back surface of the battery is guaranteed, doping of oxygen elements is further increased in the second grid line area 321, contact resistance with the second grid line 330 is further reduced, the front surface and the back surface of the battery have excellent contact capability and electrical performance, and conversion efficiency of the battery is effectively improved.
The embodiment of the application also provides a preparation method of the solar cell, which can be used for preparing the solar cell.
As shown in fig. 4, the method for manufacturing the solar cell includes: steps 410 to 440.
Step 410, a first tunneling oxide layer 210 is prepared on the light-receiving surface of the silicon substrate 100, and a first precursor layer is prepared on a surface of the first tunneling oxide layer 210 away from the silicon substrate 100.
The silicon substrate 100 may be an N-type silicon wafer or a P-type silicon wafer.
In this step, a first tunnel oxide layer 210 is prepared on the light receiving surface of the silicon substrate 100, the first tunnel oxide layer 210 may be silicon oxide, and after the first tunnel oxide layer 210 is prepared, a first precursor layer is prepared on a surface of the first tunnel oxide layer 210 away from the silicon substrate 100.
Wherein the first precursor layer is a hierarchical structure for doping to prepare a first doped polysilicon layer.
In practical implementations, the first precursor layer may be microcrystalline silicon and amorphous silicon, and the polysilicon is formed after performing a doping process such as high-temperature diffusion.
And step 420, doping the first precursor layer by using the first doping element to obtain a first doped polysilicon layer.
The first doping element may be an N-type doping element or a P-type doping element.
In this embodiment, the first doping element may be phosphorus, and the first precursor layer is doped with the first doping element, so that an N-type doped first doped polysilicon layer may be obtained; the first doping element may be boron, and the first precursor layer is doped by using the first doping element, so that a P-type doped first doped polysilicon layer can be obtained.
In this step, a zoned doping process may be performed on the first precursor layer through a mask or the like, and the first doped polysilicon layer is divided into a first gate line region 221 and a first non-gate line region 222.
The first gate line region 221 is a region on the first doped polysilicon layer, which is in contact with the first gate line 230, and the first non-gate line region 222 is a region on the first doped polysilicon layer, which is free of the first gate line 230, and may perform regional doping treatment on the first precursor layer according to a printing pattern corresponding to the first gate line 230 as a mask.
Step 430, preparing the transparent conductive medium layer 240 in the first non-gate line region 222 on the surface of the first doped polysilicon layer far from the first tunneling oxide layer 210.
Wherein, the band gap width of the transparent conductive medium layer 240 is different from the band gap width of the first doped polysilicon layer.
It should be noted that, the band gap width of the transparent conductive medium layer 240 is different from the band gap width of the first doped polysilicon layer, and a larger energy band offset is formed between the first doped polysilicon layer and the transparent conductive medium layer 240, so that the recombination of electrons and holes can be effectively reduced, and the passivation performance of the solar cell can be enhanced.
The stacked first doped polysilicon layer and the transparent conductive medium layer 240 may further form a heterojunction structure, so that reverse saturation current is reduced, and the conductivity of the transparent conductive medium layer 240 may enhance the lateral transmission capability of carriers, thereby being beneficial to reducing the gate line density of the first gate line 230 on the front side of the solar cell, reducing reverse saturation current and light shielding area, and maintaining smaller contact resistance.
In some embodiments, transparent conductive dielectric layer 240 may be a transparent conductive oxide film.
In step 440, a first passivation layer 260 is formed on a surface of the transparent conductive medium layer 240 away from the first doped polysilicon layer, and a first gate line 230 is formed on a first gate line region 221 of the surface of the first doped polysilicon layer away from the first tunneling oxide layer 210.
In practical implementation, the first gate line 230 may be printed with a metal material such as silver paste, copper paste, etc., and the first passivation layer 260 may be made with a material such as silicon nitride, silicon oxide, or aluminum oxide, etc.
According to the preparation method of the solar cell provided by the embodiment of the application, the first doped polysilicon layer and the transparent conductive medium layer 240 are arranged in the non-grid line area on the front side of the cell to be in contact, so that the band gap widths of the first doped polysilicon layer and the transparent conductive medium layer 240 are different, larger energy band offset is formed, reverse saturation current is reduced, passivation performance of the cell is effectively improved, front side shading area of the transparent conductive medium layer 240 can be reduced, contact resistance is reduced, and conversion efficiency of the cell is effectively improved.
In some embodiments, the doping concentration of the first doping element in the first gate line region 221 is greater than the doping concentration of the first doping element in the first non-gate line region 222.
In this embodiment, the first gate line region 221 is set to be a heavy doping concentration, so that the contact performance between the first doped polysilicon layer at the first gate line region 221 and the first gate line 230 can be effectively improved, and the first non-gate line region 222 is set to be a low doping concentration, so that the parasitic absorption at the first non-gate line region 222 can be effectively reduced, and the battery conversion efficiency can be improved.
In some embodiments, doping the first precursor layer with the first doping element at step 420 may include:
performing diffusion of a first doping element on the first precursor layer;
The first doping element is pushed in the position corresponding to the first gate line region 221 by using the laser, so that the doping concentration of the first doping element in the first gate line region 221 is greater than that in the first non-gate line region 222.
In this embodiment, the first diffusion of the first doping element may be performed by high temperature deposition, so as to form a first doped polysilicon layer with a low doping concentration as a whole; and then, using laser secondary doping to push the first doping element at the corresponding position of the first grid line region 221 so as to form a first doped polysilicon layer with heavy doping concentration.
In actual implementation, when the second doping is performed, the first gate line region 221 may be printed with the slurry containing the doping source to perform the pushing, so as to form a first non-gate line region 222 with a low doping concentration and a gate line region with a heavy doping concentration.
In this embodiment, the first gate line region 221 is set to be a heavy doping concentration, so that the contact performance between the first doped polysilicon layer at the first gate line region 221 and the first gate line 230 can be effectively improved, and the first non-gate line region 222 is set to be a low doping concentration, so that the parasitic absorption at the first non-gate line region 222 can be effectively reduced, and the battery conversion efficiency can be improved.
It should be noted that, the reverse saturation current is related to the doping concentration, the first non-gate line region 222 is set to have a low doping concentration, and the transparent conductive medium layer 240 with different band gap widths is disposed on the first non-gate line region 222, so as to form a larger energy band offset, thereby effectively reducing the reverse saturation current and improving the passivation performance of the battery.
The preparation method of the solar cell provided by the embodiment of the application can also be used for preparing the double-sided poly TOPCon cell.
In some embodiments, as shown in fig. 5, the method for manufacturing the solar cell includes: steps 510 to 530.
Step 510, preparing a second tunneling oxide layer 310 on the backlight surface of the silicon substrate 100, and preparing a second precursor layer on the surface of the second tunneling oxide layer 310 away from the silicon substrate 100.
The second tunneling oxide layer 310 may be silicon oxide, and after the first tunneling oxide layer 210 is formed, the second precursor layer is a layered structure for doping to form the second doped polysilicon layer 320.
In practical implementations, the second precursor layer may be microcrystalline silicon and amorphous silicon, and the polysilicon is formed after performing a doping process such as high-temperature diffusion.
Step 520, doping the second precursor layer with a second doping element having a doping type opposite to that of the first doping element, to obtain a second doped polysilicon layer 320.
In this embodiment, when the first doped polysilicon layer is an N-type doped polysilicon layer, the first doping element may be phosphorus, the second doped polysilicon layer 320 is a P-type doped polysilicon layer, and the second doping element may be boron; when the first doped polysilicon layer is a P-type doped polysilicon layer, the first doping element may be boron, the second doped polysilicon layer 320 is an N-type doped polysilicon layer, and the second doping element may be phosphorus.
Wherein the second doped polysilicon layer 320 is divided into a second gate line region 321 and a second non-gate line region 322.
The second gate line region 321 is a region of the second doped polysilicon layer 320 in contact with the second gate line 330, and the second non-gate line region 322 is a region of the second doped polysilicon layer 320 without the second gate line 330.
In step 530, a second gate is fabricated on the second gate line region 321 on the side of the second doped polysilicon layer 320 away from the second tunneling oxide layer 310, and a second passivation layer 340 is fabricated on the second non-gate line region 322 on the side of the second doped polysilicon layer 320 away from the second tunneling oxide layer 310.
In practical implementation, the second gate line 330 may be printed with a metal material such as silver paste, copper paste, etc., and the second passivation layer 340 may be made with a material such as silicon nitride, silicon oxide, or aluminum oxide, etc.
In some embodiments, step 520, doping the second precursor layer with a second doping element of an opposite doping type to the first doping element, comprises:
diffusing a second doping element into the second precursor layer;
performing laser die sinking on the second grid line area 321;
Doping of the second doping element and the third doping element is performed in the second gate line region 321.
In this embodiment, at the second gate line region 321 in contact with the gate line, the doping element of the second doped polysilicon layer 320 includes the third doping element in addition to the second doping element of N-type or P-type, so that the contact resistance between the second doped polysilicon layer 320 and the second gate line 330 can be effectively reduced, and the conversion efficiency of the battery can be improved.
It can be appreciated that doping the third doping element into the second gate line region 321 can properly reduce the doping concentration of the second doping element of N-type or P-type, and form the energy band offset, so as to effectively improve the contact performance.
In practical implementation, the third doping element may be an oxygen element, and when doping the second gate line region 321, an oxygen-containing doping source such as carbon dioxide (CO 2) may be added to dope the N-type or P-type doping source, so as to dope the oxygen element.
In this embodiment, the second precursor layer is diffused with the second doping element to form a low-doped second doped polysilicon layer 320, the second doped polysilicon layer 320 is correspondingly subjected to laser die sinking in the second gate line region 321, borosilicate glass or phosphosilicate glass formed during diffusion of the second doping element is removed, borosilicate glass or phosphosilicate glass of the second non-gate line region 322 is reserved as a mask, and doping of the second doping element and the third doping element is performed in the second gate line region 321.
In practical implementation, the laser die opening may remove a portion of the silicon oxide film layer on the second tunnel oxide layer 310, and when the second doped polysilicon layer 320 is prepared by doping the second doped element and the third doped element, a silicon oxide film layer complementary to the second tunnel oxide layer 310 may be deposited.
For example, as shown in fig. 3, borosilicate glass or phosphosilicate glass formed during diffusion of the second doping element in the second gate line region 321 is removed by laser die opening, a part of the first silicon oxide film 311 is removed, and when doping is performed subsequently, a second silicon oxide film 312 is formed in the second gate line region 321.
In some embodiments, doping the second doping element and the third doping element in the second gate line region 321 may include:
the second doped polysilicon layer 320 is generated by plasma enhanced chemical vapor deposition with the second doping element and the third doping element as doping sources.
Among them, plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD) is a method for preparing semiconductor thin film materials and other thin film materials by chemical reaction Deposition on a substrate after a Deposition chamber ionizes it by glow discharge.
In this embodiment, the polysilicon layer doped with oxygen is prepared by PECVD, and the surface concentration is high during the PECVD preparation, so that the contact effect of the second gate line region 321 can be ensured.
In practical implementation, the second doping element may be boron or phosphorus, the third doping element may be oxygen, and the doping source including the third doping element may be oxygen-containing doping source such as carbon dioxide (CO 2)
In some embodiments, the doping concentration of the second doping element in the second gate line region 321 is greater than the doping concentration of the second doping element in the second non-gate line region 322.
In this embodiment, the second gate line region 321 is set to a heavy doping concentration, so that the contact performance between the second doped polysilicon layer 320 and the second gate line 330 at the second gate line region 321 can be effectively improved, and the second non-gate line region 322 is set to a low doping concentration, so that the parasitic absorption at the second non-gate line region 322 can be effectively reduced, and the conversion efficiency of the battery can be improved.
In practical implementation, the second non-gate line region 322 adopts low doping concentration to ensure low parasitic absorption, and the second gate line region 321 can increase oxygen doping, improve contact performance and improve battery conversion efficiency.
A specific embodiment is described below.
An N-type silicon wafer is taken as a silicon substrate 100, and is textured and cleaned to remove dirt on the surface of the N-type silicon wafer.
A silicon oxide layer (corresponding to the first tunnel oxide layer 210) and a first precursor layer are formed on an N-type silicon wafer by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD).
The LPCVD N-type silicon wafer is placed in a phosphorus expanding tube, high-temperature deposition and promotion are carried out to form a front-side low-doped N-type first doped polysilicon layer, and laser is adopted to carry out secondary doping to form a heavy doped first doped polysilicon layer in the first grid line region 221.
It is understood that phosphosilicate glass (PSG) is also formed on the back side of the N-type silicon wafer in the phosphorus expander, and the back side PSG is removed using a chain machine, and polished and cleaned.
The N-type silicon wafer is placed in LPCVD to form the first silicon oxide film 311 and the second precursor layer on the back side, the silicon wafer is placed in a boron expander, and the second doped polysilicon layer 320 of the back side low doped P-type is deposited and advanced at high temperature.
The laser film opening removes borosilicate glass (BSG) of the second gate line region 321 on the back and uses a polishing/texturing scheme to remove laser damage, and after the treatment, the first silicon oxide film 311 is still processed, and part of the silicon oxide film is thinned, so that contact deterioration caused by excessive thickness of silicon oxide is prevented.
And (3) placing the silicon wafer in PECVD to generate a second silicon dioxide film layer 312 and a heavily doped P-type second doped polysilicon layer 320, adjusting the flow of boron sources such as B 2H6 and the like through PECVD to realize heavy doping, wherein the oxygen doping of the second grid line region 321 can be realized through CO 2.
The INK mask is used to protect the second doped polysilicon layer 320 of the P type of the second gate line region 321, and the rest is used to remove borosilicate glass by a chain machine and is polished.
After cleaning, a transparent conductive dielectric layer 240 is deposited on the front first non-gate line region 222 by magnetron sputtering (PVD) and Reactive Plasma Deposition (RPD) in combination with a reticle.
The cell is placed on the PECVD double-sided deposition of a first passivation layer 260 and a second passivation layer 340, and the front first grid line 230 and the back second grid line 330 are prepared by adopting a slurry printing mode after the passivation layer is prepared.
In this embodiment, the first non-gate line region 222 of the light receiving surface of the prepared solar cell is set to be a first doped polysilicon layer and a transparent conductive medium layer 240 with low doping concentration, the low doping concentration effectively reduces parasitic absorption, the first doped polysilicon layer and the transparent conductive medium layer 240 with different band gaps can effectively enhance passivation performance, the first gate line region 221 is formed by the first doped polysilicon layer with heavy doping concentration to be in good contact with the first gate line 230, and contact resistance of the cell is reduced;
The second non-grid line area 322 of the back surface is set to be low doping concentration, the second grid line area 321 is set to be heavy doping concentration, passivation performance of the back surface of the battery is guaranteed, doping of oxygen elements is further increased in the second grid line area 321, contact resistance with the second grid line 330 is further reduced, the front surface and the back surface of the battery have excellent contact capability and electrical performance, and conversion efficiency of the battery is effectively improved.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
In the description of the present application, it should be understood that the terms "upper," "lower," "front," "rear," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the application, a "first feature" or "second feature" may include one or more of such features.
In the description of the present application, "plurality" means two or more.
In the description of the application, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by another feature therebetween.
In the description of the application, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.

Claims (13)

1. A solar cell, comprising:
a silicon substrate;
the first tunneling oxide layer is arranged on the light-receiving surface of the silicon substrate;
The first doped polysilicon layer is arranged on one surface of the first tunneling oxide layer, which is far away from the silicon substrate, and is divided into a first grid line area and a first non-grid line area, and the first doped polysilicon layer comprises a first doping element;
the first grid line is arranged on one surface of the first doped polysilicon layer, which is far away from the first tunneling oxide layer, and is positioned in the first grid line area;
The transparent conductive medium layer is arranged on one surface of the first doped polycrystalline silicon layer, which is far away from the first tunneling oxide layer, and is positioned in the first non-grid line area, and the band gap width of the transparent conductive medium layer is different from that of the first doped polycrystalline silicon layer;
the first passivation layer is arranged on one surface, far away from the first doped polycrystalline silicon layer, of the transparent conductive medium layer.
2. The solar cell of claim 1, further comprising:
The second tunneling oxide layer is arranged on the backlight surface of the silicon substrate;
The second doped polysilicon layer is arranged on one surface of the second tunneling oxide layer, which is far away from the silicon substrate, and comprises a second doping element with the doping type opposite to that of the first doping element, and the second doped polysilicon layer is divided into a second grid line region and a second non-grid line region;
the second grid line is arranged on one surface of the second doped polysilicon layer, which is far away from the second tunneling oxide layer, and is positioned in the second grid line area;
The second passivation layer is arranged on one surface of the second doped polysilicon layer, which is away from the second tunneling oxide layer, and is positioned in the second non-gate line region.
3. The solar cell of claim 2, wherein the second gate line region further comprises a third doping element.
4. The solar cell according to claim 3, wherein the third doping element is an oxygen element.
5. The solar cell of claim 2, wherein a doping concentration of the second doping element in the second gate line region is greater than a doping concentration of the second doping element in the second non-gate line region.
6. The solar cell of any one of claims 1-5, wherein a doping concentration of the first doping element in the first gate line region is greater than a doping concentration of the first doping element in the first non-gate line region.
7. The solar cell of any one of claims 1-5, wherein the transparent conductive dielectric layer is a transparent conductive oxide film.
8. A method of manufacturing a solar cell, comprising:
Preparing a first tunneling oxide layer on a light receiving surface of a silicon substrate, and preparing a first precursor layer on one surface of the first tunneling oxide layer far away from the silicon substrate;
Doping the first precursor layer by using a first doping element to obtain a first doped polysilicon layer, wherein the first doped polysilicon layer is divided into a first grid line region and a first non-grid line region;
preparing a transparent conductive medium layer in the first non-gate line region of the first doped polysilicon layer far away from one side of the first tunneling oxide layer, wherein the band gap width of the transparent conductive medium layer is different from that of the first doped polysilicon layer;
preparing a first passivation layer on one surface of the transparent conductive medium layer, which is far away from the first doped polysilicon layer, and preparing a first grid line in the first grid line area on one surface of the first doped polysilicon layer, which is far away from the first tunneling oxide layer.
9. The method of manufacturing a solar cell according to claim 8, further comprising:
preparing a second tunneling oxide layer on the backlight surface of the silicon substrate, and preparing a second precursor layer on the surface, far away from the silicon substrate, of the second tunneling oxide layer;
doping the second precursor layer by using a second doping element with the doping type opposite to that of the first doping element to obtain a second doped polysilicon layer, wherein the second doped polysilicon layer is divided into a second grid line region and a second non-grid line region;
preparing a second grid electrode in the second grid line area of one surface of the second doped polycrystalline silicon layer far away from the second tunneling oxide layer, and preparing a second passivation layer in the second non-grid line area of one surface of the second doped polycrystalline silicon layer far away from the second tunneling oxide layer.
10. The method of claim 9, wherein doping the second precursor layer with a second doping element of a doping type opposite to the first doping element, comprises:
Performing diffusion of the second doping element on the second precursor layer;
performing laser die sinking on the second grid line area;
and doping the second doping element and the third doping element in the second grid line region.
11. The method of claim 10, wherein doping the second doping element and the third doping element in the second gate line region comprises:
And taking the second doping element and the third doping element as doping sources, and generating the second doped polysilicon layer through plasma enhanced chemical vapor deposition.
12. The method of claim 10, wherein the doping concentration of the second doping element in the second gate line region is greater than the doping concentration of the second doping element in the second non-gate line region.
13. The method of any one of claims 8-12, wherein the doping concentration of the first doping element in the first gate line region is greater than the doping concentration of the first doping element in the first non-gate line region.
CN202410415038.9A 2024-04-08 2024-04-08 Solar cell and method for manufacturing solar cell Active CN118016733B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410415038.9A CN118016733B (en) 2024-04-08 2024-04-08 Solar cell and method for manufacturing solar cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410415038.9A CN118016733B (en) 2024-04-08 2024-04-08 Solar cell and method for manufacturing solar cell

Publications (2)

Publication Number Publication Date
CN118016733A true CN118016733A (en) 2024-05-10
CN118016733B CN118016733B (en) 2024-06-25

Family

ID=90958891

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410415038.9A Active CN118016733B (en) 2024-04-08 2024-04-08 Solar cell and method for manufacturing solar cell

Country Status (1)

Country Link
CN (1) CN118016733B (en)

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332619A (en) * 2005-04-28 2006-12-07 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device
KR101626248B1 (en) * 2015-01-09 2016-05-31 고려대학교 산학협력단 Silicon solar cell and method of manufacturing the same
CN208336240U (en) * 2018-07-16 2019-01-04 英利能源（中国）有限公司 Solar battery and solar cell module
JP2019054028A (en) * 2017-09-13 2019-04-04 株式会社半導体エネルギー研究所 Semiconductor device, and display device
US20190131472A1 (en) * 2017-10-27 2019-05-02 Industrial Technology Research Institute Solar cell
CN112133769A (en) * 2019-06-24 2020-12-25 泰州隆基乐叶光伏科技有限公司 Solar cell and method for manufacturing same
CN113206123A (en) * 2021-04-22 2021-08-03 南京大学 Perovskite/crystalline silicon laminated cell and preparation method thereof
CN113437179A (en) * 2021-06-04 2021-09-24 浙江爱旭太阳能科技有限公司 Solar cell and preparation method thereof
CN113629155A (en) * 2021-08-06 2021-11-09 常州时创能源股份有限公司 Crystalline silicon solar cell
CN114497259A (en) * 2020-10-27 2022-05-13 一道新能源科技(衢州)有限公司 Solar cell and preparation method thereof
CN115132855A (en) * 2022-09-01 2022-09-30 国晟能源股份有限公司 Nano fully-passivated contact crystalline silicon heterojunction double-sided solar cell and manufacturing method thereof
CN115513309A (en) * 2022-08-31 2022-12-23 隆基绿能科技股份有限公司 Back contact solar cell and preparation method thereof
WO2023045347A1 (en) * 2021-09-22 2023-03-30 泰州隆基乐叶光伏科技有限公司 Back-contact cell and manufacturing method therefor
CN115985992A (en) * 2022-12-29 2023-04-18 江苏爱康能源研究院有限公司 N-type monocrystalline silicon HBC solar cell structure and preparation method thereof
CN116230783A (en) * 2023-05-09 2023-06-06 天合光能股份有限公司 Solar cell, solar cell sheet and photovoltaic module
CN117038754A (en) * 2023-10-08 2023-11-10 长三角物理研究中心有限公司 Flexible thin film silicon-based solar cell and preparation method thereof
CN117594684A (en) * 2022-12-16 2024-02-23 隆基绿能科技股份有限公司 Double-sided hybrid solar cell and preparation method thereof

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332619A (en) * 2005-04-28 2006-12-07 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device
KR101626248B1 (en) * 2015-01-09 2016-05-31 고려대학교 산학협력단 Silicon solar cell and method of manufacturing the same
JP2019054028A (en) * 2017-09-13 2019-04-04 株式会社半導体エネルギー研究所 Semiconductor device, and display device
US20190131472A1 (en) * 2017-10-27 2019-05-02 Industrial Technology Research Institute Solar cell
CN208336240U (en) * 2018-07-16 2019-01-04 英利能源（中国）有限公司 Solar battery and solar cell module
CN112133769A (en) * 2019-06-24 2020-12-25 泰州隆基乐叶光伏科技有限公司 Solar cell and method for manufacturing same
CN114497259A (en) * 2020-10-27 2022-05-13 一道新能源科技(衢州)有限公司 Solar cell and preparation method thereof
CN113206123A (en) * 2021-04-22 2021-08-03 南京大学 Perovskite/crystalline silicon laminated cell and preparation method thereof
CN113437179A (en) * 2021-06-04 2021-09-24 浙江爱旭太阳能科技有限公司 Solar cell and preparation method thereof
CN113629155A (en) * 2021-08-06 2021-11-09 常州时创能源股份有限公司 Crystalline silicon solar cell
WO2023010858A1 (en) * 2021-08-06 2023-02-09 常州时创能源股份有限公司 Crystalline silicon solar cell
WO2023045347A1 (en) * 2021-09-22 2023-03-30 泰州隆基乐叶光伏科技有限公司 Back-contact cell and manufacturing method therefor
CN115513309A (en) * 2022-08-31 2022-12-23 隆基绿能科技股份有限公司 Back contact solar cell and preparation method thereof
CN115132855A (en) * 2022-09-01 2022-09-30 国晟能源股份有限公司 Nano fully-passivated contact crystalline silicon heterojunction double-sided solar cell and manufacturing method thereof
CN117594684A (en) * 2022-12-16 2024-02-23 隆基绿能科技股份有限公司 Double-sided hybrid solar cell and preparation method thereof
CN115985992A (en) * 2022-12-29 2023-04-18 江苏爱康能源研究院有限公司 N-type monocrystalline silicon HBC solar cell structure and preparation method thereof
CN116230783A (en) * 2023-05-09 2023-06-06 天合光能股份有限公司 Solar cell, solar cell sheet and photovoltaic module
CN117038754A (en) * 2023-10-08 2023-11-10 长三角物理研究中心有限公司 Flexible thin film silicon-based solar cell and preparation method thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
VAN CLEEF: "Significance of tunneling in p+ amorphous silicon carbide n crystalline silicon heterojunction solar cells", APPLIED PHYSICS LETTERS, vol. 73, no. 18, 2 November 1998 (1998-11-02), pages 2609 - 2611, XP012021283, DOI: 10.1063/1.122521 *
吴斌;汪建华;满卫东;熊礼威;谢鹏;孙蕾;: "多晶硅薄膜太阳能电池的研究现状", 世界科技研究与发展, vol. 30, no. 06, 15 December 2008 (2008-12-15), pages 688 - 693 *

Also Published As

Publication number Publication date
CN118016733B (en) 2024-06-25

Similar Documents

Publication Publication Date Title
EP4322227A1 (en) Solar cell structure and manufacturing method therefor
CN217306521U (en) Solar cell and photovoltaic module
JP7148753B1 (en) Solar cell, photovoltaic module and method for manufacturing solar cell
CN117712193A (en) Solar cell, preparation method thereof and photovoltaic module
CN108615775B (en) Interdigital back contact heterojunction monocrystalline silicon battery
KR20180018895A (en) Bifacial silicon solar cell
CN118053924A (en) Solar cell, preparation method thereof, laminated cell and photovoltaic module
CN220543926U (en) Solar cell and photovoltaic module
CN114725225A (en) Efficient P-type IBC battery and preparation method thereof
CN208507687U (en) Interdigital back contact heterojunction monocrystalline silicon battery
CN115000198B (en) Solar cell and photovoltaic module
CN111463306A (en) Novel heterojunction battery and preparation method thereof
CN115020533B (en) Preparation method of POLO-IBC battery
CN114975668B (en) P-type full back contact solar cell with front floating junction overlapped with SE and manufacturing method thereof
CN118016733B (en) Solar cell and method for manufacturing solar cell
CN115985992A (en) N-type monocrystalline silicon HBC solar cell structure and preparation method thereof
WO2022134994A1 (en) Solar cell, production method, and photovoltaic module
CN212874518U (en) Solar cell
CN212783486U (en) Double-sided heterojunction solar cell and photovoltaic module
CN113437161A (en) Solar cell, preparation method thereof and photovoltaic module
CN114744064A (en) Solar cell, production method and photovoltaic module
CN111864014A (en) Solar cell and manufacturing method thereof
CN214753796U (en) Cell structure, solar cell and photovoltaic module
CN218849510U (en) N-type monocrystalline silicon HBC solar cell structure
CN210110794U (en) Low surface concentration deep junction solar cell

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant