CN115985992A - N-type monocrystalline silicon HBC solar cell structure and preparation method thereof - Google Patents
N-type monocrystalline silicon HBC solar cell structure and preparation method thereof Download PDFInfo
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Abstract
The invention relates to an N-type monocrystalline silicon HBC solar cell structure and a preparation method thereof, wherein the N-type monocrystalline silicon HBC solar cell structure comprises a monocrystalline silicon substrate, wherein a silicon nitride layer and an amorphous silicon N + type crystalline silicon layer are sequentially arranged on the front surface of the monocrystalline silicon substrate from top to bottom; the back surface of the monocrystalline silicon substrate is provided with a first back surface unit and a second back surface unit which are alternately arranged, the first back surface unit comprises a silicon dioxide tunneling layer, a P + type polycrystalline silicon layer and a first composite film layer which are sequentially arranged from top to bottom, and the second back surface unit comprises an intrinsic amorphous silicon layer, an N + type amorphous silicon layer and a second composite film layer which are sequentially arranged from top to bottom; and electrodes are arranged on the outer sides of the first composite film layer and the second composite film layer. The invention solves the problem of low amorphous silicon doping efficiency by depositing the tunneling oxide layer and the polycrystalline silicon instead of amorphous silicon.
Description
Technical Field
The invention relates to the technical field of suede laminated solar cells, in particular to an N-type monocrystalline silicon HBC solar cell structure and a preparation method thereof.
Background
The interdigital Back Contact Heterojunction monocrystalline Silicon Solar Cell (HBC Solar Cell for short) has the advantages of both the interdigital Back Contact Solar Cell (IBC Solar Cell for short) and the Heterojunction Solar Cell (HIT Solar Cell for short) with a Thin Intrinsic layer, removes a front surface metal electrode, reduces shading loss and obtains larger short-circuit current, and also greatly reduces an interface state, reduces surface recombination and improves open-circuit voltage by inserting a high-quality Intrinsic amorphous Silicon passivation layer between the heavily doped amorphous Silicon and the crystalline Silicon, thereby being the monocrystalline Silicon Solar Cell with the highest photoelectric conversion efficiency in the world at present.
The HBC cell represents the highest efficiency level of the crystalline silicon cell, but the HBC has been limited by the high production cost and has been developed in a zigzag manner. The HBC battery retains the advantages of the HBC battery and the HJT battery and simultaneously retains the difficulty of respective production processes of the IBC battery and the HJT battery. The key problem of the IBC battery technology is how to prepare P regions and N regions which are arranged at intervals in an interdigital manner on the back of the battery and respectively form metallized contacts and grid lines on the P regions and the N regions. The processes of 'mask-slotting-deposition-etching' and the like are not avoided in the preparation of the PN region and TCO of the conventional HBC battery.
For example, chinese patent CN109216509B provides a method for manufacturing a back contact heterojunction solar cell, in which amorphous silicon, doped amorphous silicon and a transparent conductive film are deposited on the back surface of the cell by a "mask-deposition-etching" process, the process steps of the invention are complicated, the process window in the cell manufacturing process is narrow, the requirement on process cleanliness is extremely high, and the cost of the HBC cell is very high. In addition, the existing HBC battery manufacturing technology has the defects that the absorption of the amorphous silicon film on a long-wave spectrum is low, the spectrum penetrates through the battery and cannot be effectively utilized, and the efficiency of the battery cannot be improved.
Disclosure of Invention
The invention aims to overcome the defects and provides an N-type monocrystalline silicon HBC solar cell structure and a preparation method thereof.
The purpose of the invention is realized as follows:
an N-type monocrystalline silicon HBC solar cell structure comprises a monocrystalline silicon substrate, wherein a silicon nitride layer and an amorphous silicon N + type crystalline silicon layer are sequentially arranged on the front surface of the monocrystalline silicon substrate from top to bottom; the back surface of the monocrystalline silicon substrate is provided with a first back surface unit and a second back surface unit which are alternately arranged, the first back surface unit comprises a silicon dioxide tunneling layer, a P + type polycrystalline silicon layer and a first composite film layer which are sequentially arranged from top to bottom, and the second back surface unit comprises an intrinsic amorphous silicon layer, an N + type amorphous silicon layer and a second composite film layer which are sequentially arranged from top to bottom; and electrodes are arranged on the outer sides of the first composite film layer and the second composite film layer.
Further, the first composite film layer is a composite film layer of a TCO conductive film and a metal film, and the second composite film layer has the same structure as the first composite film layer and is also a composite film layer of the TCO conductive film and the metal film.
Furthermore, the TCO conducting film in the first composite film layer is made of a material with a work function larger than 5.2ev, the thickness of the TCO conducting film is 10 to 130nm, and the thickness of the metal film in the first composite film layer is 10 to 200nm.
Furthermore, the TCO conducting film in the second composite film layer is made of a material with a work function smaller than 4.2ev, the thickness of the TCO conducting film is 10 to 130nm, and the thickness of the metal film in the second composite film layer is 10 to 200nm.
Furthermore, an insulation gap is arranged between the P + type polycrystalline silicon layer and the N + type amorphous silicon layer, and the distance between the insulation gaps is 0.1 to 10 micrometers.
A preparation method of an N-type monocrystalline silicon HBC solar cell structure comprises the following steps:
step one, silicon wafer cleaning:
selecting an N-type silicon wafer, and cleaning and texturing the N-type silicon wafer; cleaning a silicon wafer, and then making wool, wherein a suede layer is formed on the front side of the silicon wafer;
step two, tunneling oxide layer and polysilicon deposition:
forming a tunneling oxide layer and a polysilicon layer on the back of the cleaned silicon wafer by using the technologies such as LPVCVD, PECVD and the like;
step three, phosphorus diffusion:
expanding phosphorus to the polycrystalline silicon layer through high-temperature boron diffusion to form an effective doping layer;
step four, laser etching:
the tunneling oxide layer and the polycrystalline silicon of part of the N area are subjected to ablation etching in the N area on the back surface of the cell piece through a laser etching process; the laser etching area is the sum of the back P area and the insulation gap;
step five, efficiently cleaning the silicon wafer;
sixthly, depositing the intrinsic amorphous silicon layer on the front surface:
plating an intrinsic amorphous silicon thin film on the front surface of the cell by PECVD, HWCVD or LPCVD technology;
seventhly, depositing a front anti-reflection film:
plating an anti-reflection film on the front surface of the cell by a PECVD technology, wherein the anti-reflection film is made of a micro silicon nitride material;
step eight, depositing a back intrinsic amorphous silicon layer:
plating an intrinsic amorphous silicon thin film on the back surface of the cell by PECVD, HWCVD or LPCVD technology;
step nine, depositing a back P-type amorphous silicon layer:
depositing a P-type amorphous silicon layer by adopting a mask-etching technology, wherein the size of a protection region is the sum of the size of an N region doping region and the size of a gap; plating a P-type doped amorphous silicon film on the cell by PECVD, HWCVD or LPCVD technology;
step ten, TCO and metal film composite film layer deposition
Plating a TCO conductive film and a metal film on the battery piece by a PVD or RPD equipment technology; respectively depositing the TCO conductive films in the P area and the N area by adopting a mask-etching process; depositing a metal film by adopting a PVD or RPD equipment technology;
step ten, preparing an electrode;
and step eleven, testing.
Furthermore, in the second step, the tunneling oxide layer is made of silicon dioxide.
Further, the phosphorus doping concentration in the third step is not lower than 1e20/cm 3 。
Furthermore, in the step ten, the TCO conductive film in the P area is made of a material with a work function larger than 5.2 ev.
Further, in the step ten, the TCO conductive film of the N area adopts a material with the work function less than 4.2 ev.
Compared with the prior art, the invention has the beneficial effects that:
the microcrystal technology is a key technology of HJT future high-efficiency H cells, and the doped uc-Si: h is easier to achieve than amorphous silicon doping, and microcrystalline silicon doping is easier to approach the conduction band bottom or the valence band top than amorphous silicon, the cell can achieve higher conversion efficiency, however, microcrystalline processes face lower growth rate and higher device requirements. The N-type monocrystalline silicon HBC solar cell structure optimizes the cell structure design, and solves the problem of low amorphous silicon doping efficiency by replacing amorphous silicon with a technology of depositing a tunneling oxide layer and polycrystalline silicon.
According to the invention, the back of the cell sheet adopts a TCO and metal film composite film layer to replace a single-layer TCO conductive film to realize ohmic contact between polycrystalline silicon and amorphous silicon and an electrode, and the transmission of the infrared long wave band is reduced through the emission effect of metal, so that the utilization rate of the long wave band is improved, the current of the cell is finally improved, and the conversion efficiency of the cell is improved.
The invention solves the defect that new donors and the like in the silicon wafer body can not be eliminated, and the impurity content of the silicon wafer per se is high, thereby influencing the battery efficiency; the HJT battery technology is a low-temperature process, a high-temperature heat treatment technology is not adopted, the conventional technology needs to carry out additional heat treatment on the silicon wafer to solve the defect problem of the silicon wafer, and the high-temperature process in the early stage in the preparation method can effectively eliminate the defects of new donors and the like in the silicon wafer body and improve the conversion efficiency of the battery.
Drawings
Fig. 1 is a schematic structural diagram of an N-type monocrystalline silicon HBC solar cell structure according to the present invention.
Fig. 2 is a schematic view of a process for manufacturing a solar cell structure according to the present invention.
Wherein:
the silicon-based solar cell comprises a monocrystalline silicon substrate 1, an amorphous silicon N + type crystalline silicon layer 2, a silicon nitride layer 3, a first back unit 4, a silicon dioxide tunneling layer 41, a P + type polycrystalline silicon layer 42, a first composite film layer 43, a second back unit 5, an intrinsic amorphous silicon layer 51, an N + type amorphous silicon layer 52, a second composite film layer 53 and an electrode 6.
Detailed Description
Example 1:
referring to fig. 1, the N-type monocrystalline silicon HBC solar cell structure according to the present invention includes a monocrystalline silicon substrate 1, wherein a silicon nitride layer 3 and an amorphous silicon N + type crystalline silicon layer 2 are sequentially disposed on a front surface of the monocrystalline silicon substrate 1 from top to bottom; the back of the monocrystalline silicon substrate 1 is provided with a first back unit 4 and a second back unit 5 which are alternately arranged, the first back unit 4 comprises a silicon dioxide tunneling layer 41, a P + type polycrystalline silicon layer 42 and a first composite film layer 43 which are sequentially arranged from top to bottom, and the second back unit 5 comprises an intrinsic amorphous silicon layer 51, an N + type amorphous silicon layer 52 and a second composite film layer 53 which are sequentially arranged from top to bottom.
The first composite film layer 43 is a composite film layer of a TCO conductive film and a metal film, the metal film is made of silver, the TCO conductive film in the first composite film layer 43 is made of a material with a work function larger than 5.2ev, the thickness of the TCO conductive film is 10 to 130nm, and the thickness of the metal film in the first composite film layer 43 is 10 to 200nm; the structure of the second composite film layer 53 is the same as that of the first composite film layer 43, the second composite film layer is a composite film layer of a TCO conductive film and a metal film, the metal film is made of silver, the TCO conductive film in the second composite film layer 53 is made of a material with the work function smaller than 4.2ev, the thickness of the TCO conductive film is 10 to 130nm, and the thickness of the metal film in the second composite film layer 53 is 10 to 200nm.
A certain gap is arranged between the first back unit 4 and the second back unit 5, an insulation gap is arranged between the P + type polycrystalline silicon layer 42 and the N + type amorphous silicon layer 52, and the distance between the insulation gaps is 0.1 to 10 μm.
And the outer sides of the first composite film layer 43 and the second composite film layer 53 are both provided with electrodes 6.
The thickness of the monocrystalline silicon substrate 1 is 80 to 150 mu m; the thickness of the silicon nitride layer is 40 to 120nm; the thickness of the silicon dioxide tunneling layer 41 is 0.5-2nm; the thickness of the P + type polycrystalline silicon layer 42 is 50-150nm; the thickness of the film layer of the intrinsic amorphous silicon layer 51 is 1 to 20nm.
The positive surface of the battery structure ensures field passivation and surface passivation, and simultaneously improves the antireflection effect; the back emitter region adopts a tunneling passivation film and polycrystalline silicon of a high-temperature process to replace intrinsic amorphous silicon and P-type amorphous silicon, the doping efficiency of the P region is improved, the performance of the cell is improved, the polycrystalline silicon and the amorphous silicon are connected with the electrode, ohmic contact is realized by adopting a transition layer mode of a TCO and metal film composite film layer, in addition, the TCO and the metal film composite film layer can realize the reflection efficiency of the long wave band of the cell, the optical utilization of the long wave band is improved, and the conversion efficiency of the cell is improved
Referring to fig. 2, the method for preparing an N-type monocrystalline silicon HBC solar cell structure according to the present invention includes the following steps:
step one, cleaning silicon chip
Selecting an N-type silicon wafer, and performing texturing and cleaning treatment on the N-type silicon wafer; etching the silicon wafer after efficient cleaning, and forming a textured layer on the front side of the silicon wafer; the thickness of the N-type silicon wafer is 80 mu m;
step two, growing tunneling oxide layer, polysilicon and depositing
Forming a tunneling oxide layer and a polysilicon layer on the back of the cleaned silicon wafer by using the technologies such as LPVCVD, PECVD and the like; the tunneling oxide layer is made of silicon dioxide materials, the thickness of the tunneling oxide layer is 0.5nm, and the thickness of the polycrystalline silicon layer is 50nm;
step three, phosphorus diffusion
Expanding phosphorus to the polycrystalline silicon layer through high-temperature diffusion to form an effective doping layer; the phosphorus doping concentration is not less than 1e20/cm 3 ；
Step four, laser etching
The tunneling oxide layer and the polycrystalline silicon in part of the N area are subjected to ablation etching in the back N area through a laser etching process; the laser etching area is the sum of the back P area and the insulation gap; the insulation gap ensures insulation of the P area and the N area in the power generation process; the size of the insulation gap is 0.1 μm;
step five, high-efficiency cleaning of silicon wafers
Carrying out efficient cleaning treatment on the silicon wafer; removing a damaged layer and other impurities from the silicon wafer in the laser processing process; cleaning the plating produced during the LPCVD processing of the silicon wafer;
sixthly, depositing a front intrinsic amorphous silicon layer
Plating an intrinsic amorphous silicon thin film on the front surface of the cell through PECVD, HWCVD or LPCVD technology, wherein the thickness of the intrinsic amorphous silicon thin film is 1nm;
step seven, deposition of front anti-reflection film
Plating an anti-reflection film on the front surface of the cell by a PECVD (plasma enhanced chemical vapor deposition) technology, wherein the anti-reflection film is made of micro silicon nitride and has the thickness of 40nm;
eighth step, deposition of back intrinsic amorphous silicon layer
Plating an intrinsic amorphous silicon film on the back surface of the cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the intrinsic amorphous silicon layer is 1nm;
nine steps, depositing the back P type amorphous silicon layer
Depositing a P-type amorphous silicon layer on the back surface of the cell by adopting a mask-etching process, wherein the size of the protection region is the sum of the size of the N region doping region and the size of the gap, and the size of the insulation gap is 0.1 mu m; plating a P-type doped amorphous silicon film on the cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the P-type doped amorphous silicon film is 1nm;
step ten, TCO and metal film composite film layer deposition
A P area and an N area on the back surface of the battery piece adopt a mask-etching deposition process to deposit a composite film layer of TCO and a metal film; plating a transparent conductive film on the cell sheet by adopting PVD or RPD equipment technology, wherein the work function of the target material In an N region is less than 4.2ev, and In is adopted 2 O 3 /SnO 2 The mass ratio is 97; the work function of the target material In the P area is more than 5.2ev, and In is adopted 2 O 3 /SnO 2 The mass ratio is 95; the deposition of the metal film layer adopts a PVD equipment technology, the material of the metal film is silver, and the thickness of the metal film is 10nm;
step eleven, electrode preparation
Metallization, printing conductive paste by a screen printing technology, and printing a battery pattern; the conductive slurry is low-temperature silver paste; the battery pattern is designed into a multi-main-grid technology, and the number of main grid lines of the battery is 17;
twelfth, test
Through testing the efficiency of the cell, the Voc reaches 735mV, the Isc is 41.61mA/cm < 2 >, the FF is 83.57%, and the cell conversion efficiency reaches 25.56%.
Example 2:
the N-type monocrystalline silicon HBC solar cell structure related to this embodiment 2 includes the following steps:
step one, cleaning silicon chip
Selecting an N-type silicon wafer, and performing texturing and cleaning treatment on the N-type silicon wafer; etching the silicon wafer after efficient cleaning, and forming a textured layer on the front side of the silicon wafer; the thickness of the N-type silicon wafer is 130 mu m;
step two, growing a tunneling oxide layer, polysilicon and depositing
Forming a tunneling oxide layer and a polysilicon layer on the back of the cleaned silicon wafer by using the technologies such as LPVCVD, PECVD and the like; the tunneling oxide layer is made of silicon dioxide materials, the thickness of the tunneling oxide layer is 1.2nm, and the thickness of the polycrystalline silicon layer is 100nm;
step three, phosphorus diffusion
Expanding phosphorus to the polycrystalline silicon layer through high-temperature diffusion to form an effective doping layer; the phosphorus doping concentration is not less than 1e20/cm 3 ；
Step four, laser etching
The tunneling oxide layer and the polycrystalline silicon in part of the N area are subjected to ablation etching in the back N area through a laser etching process; the laser etching area is the sum of the back P area and the insulation gap; the insulation gap ensures insulation of the P area and the N area in the power generation process; the size of the insulation gap is 1 μm;
step five, high-efficiency cleaning of silicon wafers
Carrying out efficient cleaning treatment on the silicon wafer; removing a damaged layer and other impurities in the laser processing process of the silicon wafer; cleaning the winding plating generated during the silicon wafer LPCVD processing, and cleaning;
sixthly, depositing the intrinsic amorphous silicon layer on the front surface
Plating an intrinsic amorphous silicon thin film on the front surface of the cell through PECVD, HWCVD or LPCVD technology, wherein the thickness of the intrinsic amorphous silicon thin film is 5nm;
step seven, deposition of front anti-reflection film
Plating an anti-reflection film on the front surface of the cell by a PECVD (plasma enhanced chemical vapor deposition) technology, wherein the anti-reflection film is made of micro silicon nitride and has the thickness of 90nm;
eighth step, deposition of back intrinsic amorphous silicon layer
Plating an intrinsic amorphous silicon film on the back surface of the cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the intrinsic amorphous silicon layer is 5nm;
step nine, depositing a back P-type amorphous silicon layer
Depositing a P-type amorphous silicon layer on the back surface of the cell by adopting a mask-etching process, wherein the size of the protection region is the sum of the size of the N region doping region and the size of the gap, and the size of the insulation gap is 1 mu m; plating a P-type doped amorphous silicon film on the cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the P-type doped amorphous silicon film is 8nm;
step ten, TCO and metal film composite film layer deposition
A P area and an N area on the back surface of the battery piece adopt a mask-etching deposition process to deposit a composite film layer of TCO and a metal film; plating a transparent conductive film on the cell sheet by adopting PVD or RPD equipment technology, wherein the work function of the target material In an N region is less than 4.2ev, and In is adopted 2 O 3 /SnO 2 The mass ratio is 97; the work function of the target material In the P area is more than 5.2ev, and In is adopted 2 O 3 /SnO 2 The mass ratio is 95; the deposition of the metal film layer adopts a PVD equipment technology, the material of the metal film is silver, and the thickness of the metal film is 100nm;
step eleven, electrode preparation
Metallization, printing conductive slurry by a silk screen printing technology, and printing a battery pattern; the conductive slurry is low-temperature silver paste; the design of the battery pattern is a multi-main-grid technology, and the number of main grid lines of the battery is 17;
twelfth, test
Through testing the efficiency of the cell piece, the Voc reaches 734mV, the Isc is 41.65mA/cm < 2 >, the FF is 83.78%, and the cell conversion efficiency reaches 25.61%.
Example 3:
the N-type monocrystalline silicon HBC solar cell structure related to this embodiment 3 includes the following steps:
step one, cleaning silicon chip
Selecting an N-type silicon wafer, and performing texturing and cleaning treatment on the N-type silicon wafer; etching the silicon wafer after efficient cleaning, and forming a textured layer on the front side of the silicon wafer; the thickness of the N-type silicon wafer is 150 mu m;
step two, growing a tunneling oxide layer, polysilicon and depositing
Forming a tunneling oxide layer and a polysilicon layer on the back of the cleaned silicon wafer by using the technologies such as LPVCVD, PECVD and the like; the tunneling oxide layer is made of silicon dioxide materials, the thickness of the tunneling oxide layer is 2nm, and the thickness of the polycrystalline silicon layer is 150nm;
step three, phosphorus diffusion
Expanding phosphorus to the polycrystalline silicon layer through high-temperature diffusion to form an effective doping layer; phosphorus doping concentration is not less than 1e20/cm 3 ；
Step four, laser etching
The tunneling oxide layer and the polycrystalline silicon of part of the N area are subjected to ablation etching in the back N area through a laser etching process; the laser etching area is the sum of the back P area and the insulation gap; the insulation gap ensures insulation of the P area and the N area in the power generation process; the size of the insulation gap is 10 μm;
step five, efficiently cleaning the silicon wafer
Carrying out efficient cleaning treatment on the silicon wafer; removing a damaged layer and other impurities from the silicon wafer in the laser processing process; cleaning the plating produced during the LPCVD processing of the silicon wafer;
sixthly, depositing a front intrinsic amorphous silicon layer
Plating an intrinsic amorphous silicon thin film on the front surface of the cell through PECVD, HWCVD or LPCVD technology, wherein the thickness of the intrinsic amorphous silicon thin film is 20nm;
step seven, deposition of front anti-reflection film
Plating an anti-reflection film on the front surface of the cell by a PECVD (plasma enhanced chemical vapor deposition) technology, wherein the anti-reflection film is made of micro silicon nitride and has the thickness of 120nm;
eighth, depositing a back intrinsic amorphous silicon layer
Plating an intrinsic amorphous silicon film on the back surface of the cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the intrinsic amorphous silicon layer is 20nm;
nine steps, depositing the back P type amorphous silicon layer
Depositing a P-type amorphous silicon layer on the back surface of the cell by adopting a mask-etching process, wherein the size of the protection region is the sum of the size of the N region doping region and the size of the gap, and the size of the insulation gap is 10 mu m; plating a P-type doped amorphous silicon film on the cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the P-type doped amorphous silicon film is 20nm;
step ten, TCO and metal film composite film layer deposition
A P area and an N area on the back surface of the battery piece adopt a mask-etching deposition process to deposit a composite film layer of TCO and a metal film; plating a transparent conductive film on the cell sheet by adopting PVD or RPD equipment technology, wherein the work function of the target material In an N region is less than 4.2ev, and In is adopted 2 O 3 /SnO 2 The mass ratio is 97, and the thickness is 130nm; the work function of the target material In the P area is more than 5.2ev, and In is adopted 2 O 3 /SnO 2 The mass ratio is 95; the deposition of the metal film layer adopts a PVD equipment technology, the material of the metal film is silver, and the thickness of the metal film is 200nm;
step eleven, electrode preparation
Metallization, printing conductive slurry by a silk screen printing technology, and printing a battery pattern; the conductive slurry is low-temperature silver paste; the design of the battery pattern is a multi-main-grid technology, and the number of main grid lines of the battery is 17;
twelfth, test
Through testing the efficiency of the cell, the Voc reaches 736mV, the Isc is 41.7mA/cm < 2 >, the FF is 83.39 percent, and the cell conversion efficiency is as high as 25.64 percent.
Comparative example 1:
step one, cleaning of silicon wafer
Selecting an N-type silicon wafer, wherein the thickness of the silicon wafer is 130 microns, and performing texturing and cleaning treatment on the N-type silicon wafer; organic dirt, metal impurities and a surface damage layer on the surface of the silicon wafer are removed through a cleaning process; etching the silicon wafer after efficient cleaning, and forming a textured layer on the front side of the silicon wafer;
step two, coating films on the double-sided intrinsic layer and the N-type amorphous silicon doped layer
Respectively plating intrinsic amorphous silicon thin films on the front surface and the back surface of the cell piece by a PECVD technology to form an amorphous silicon intrinsic layer, wherein the thickness of the film layer is 5nm;
plating an N-type amorphous silicon doped layer on the back surface of the cell through a PECVD technology, wherein the thickness of the N-type amorphous silicon doped layer is 10nm;
step three, preparation of back PN region
Preparing a back PN region through the processes of masking, slotting, depositing, etching and the like;
step four, preparing the antireflection film
Plating a SiNX anti-reflection film on the front surface of the cell piece by a PECVD method;
step five, TCO conductive film deposition
Plating a transparent TCO conductive film on the cell by adopting a PVD equipment technology;
step six, sintering of electrode printing electrode
After silver paste is printed on the back of the cell through a screen printing process, the cell is sintered at a low temperature and then is connected with the TCO film layer to realize ohmic contact;
step seven, sorting test
Through testing the efficiency of the cell, the Voc reaches 732mV, the Isc is 41.42mA/cm < 2 >, the FF is 83.59 percent, and the cell conversion efficiency is as high as 25.34 percent.
Data comparison table of cell conversion efficiencies for 3 examples of the invention and comparative example 1:
the above is only a specific application example of the present invention, and the protection scope of the present invention is not limited in any way. All the technical solutions formed by equivalent transformation or equivalent replacement fall within the protection scope of the present invention.
Claims (10)
1. An N-type monocrystalline silicon HBC solar cell structure is characterized in that: the silicon nitride-based amorphous silicon solar cell comprises a monocrystalline silicon substrate (1), wherein a silicon nitride layer (3) and an amorphous silicon n + type crystalline silicon layer (2) are sequentially arranged on the front surface of the monocrystalline silicon substrate (1) from top to bottom; the back surface of the monocrystalline silicon substrate (1) is provided with a first back surface unit (4) and a second back surface unit (5) which are alternately arranged, the first back surface unit (4) comprises a silicon dioxide tunneling layer (41), a P + type polycrystalline silicon layer (42) and a first composite film layer (43) which are sequentially arranged from top to bottom, and the second back surface unit (5) comprises an intrinsic amorphous silicon layer (51), an N + type amorphous silicon layer (52) and a second composite film layer (53) which are sequentially arranged from top to bottom; and electrodes (6) are arranged on the outer sides of the first composite film layer (43) and the second composite film layer (53).
2. The N-type monocrystalline silicon HBC solar cell structure of claim 1, wherein: the first composite film layer (43) is a composite film layer of a TCO conductive film and a metal film, and the second composite film layer (53) has the same structure as the first composite film layer (43) and is also a composite film layer of the TCO conductive film and the metal film.
3. The N-type monocrystalline silicon HBC solar cell structure according to claim 2, characterized in that: the TCO conducting film in the first composite film layer (43) is made of a material with a work function larger than 5.2ev, the thickness of the TCO conducting film is 10 to 130nm, and the thickness of the metal film in the first composite film layer (43) is 10 to 200nm.
4. The N-type monocrystalline silicon HBC solar cell structure of claim 2, wherein: the TCO conducting film in the second composite film layer (53) is made of a material with a work function smaller than 4.2ev, the thickness of the TCO conducting film is 10 to 130nm, and the thickness of the metal film in the second composite film layer (53) is 10 to 200nm.
5. The N-type monocrystalline silicon HBC solar cell structure of claim 1, wherein: an insulation gap is arranged between the P + type polycrystalline silicon layer (42) and the N + type amorphous silicon layer (52), and the distance between the insulation gaps is 0.1-10 mu m.
6. A method for preparing the N-type monocrystalline silicon HBC solar cell structure of claim 1, comprising:
step one, silicon wafer cleaning:
selecting an N-type silicon wafer, and cleaning and texturing the N-type silicon wafer; cleaning a silicon wafer, texturing, and forming a textured layer on the front side of the silicon wafer;
step two, tunneling oxide layer and polysilicon deposition:
forming a tunneling oxide layer and a polysilicon layer on the back of the cleaned silicon wafer by using the technologies such as LPVCVD, PECVD and the like;
step three, phosphorus diffusion:
expanding phosphorus to the polycrystalline silicon layer through high-temperature boron diffusion to form an effective doping layer;
step four, laser etching:
the tunneling oxide layer and the polycrystalline silicon of part of the N area are subjected to ablation etching in the N area on the back surface of the cell piece through a laser etching process; the laser etching area is the sum of the back P area and the insulation gap;
fifthly, efficiently cleaning the silicon wafer;
sixthly, depositing the intrinsic amorphous silicon layer on the front surface:
plating an intrinsic amorphous silicon thin film on the front side of the cell by PECVD, HWCVD or LPCVD technology;
step seven, depositing a front antireflection film:
plating an anti-reflection film on the front surface of the cell by a PECVD technology, wherein the anti-reflection film is made of a micro silicon nitride material;
step eight, depositing a back intrinsic amorphous silicon layer:
plating an intrinsic amorphous silicon thin film on the back surface of the cell by PECVD, HWCVD or LPCVD technology;
step nine, depositing a back P-type amorphous silicon layer:
depositing a P-type amorphous silicon layer by adopting a mask-etching technology, wherein the size of a protection region is the sum of the size of an N region doping region and the size of a gap; plating a P-type doped amorphous silicon film on the cell by PECVD, HWCVD or LPCVD technology;
step ten, TCO and metal film composite film layer deposition
Plating a TCO conductive film and a metal film on the battery piece by a PVD or RPD equipment technology; respectively depositing the TCO conductive films in the P area and the N area by adopting a mask-etching process; depositing a metal film by adopting a PVD or RPD equipment technology;
step ten, preparing an electrode;
and step eleven, testing.
7. The method for preparing an N-type monocrystalline silicon HBC solar cell structure according to claim 6, wherein the method comprises the following steps: in the second step, the tunneling oxide layer is made of silicon dioxide.
8. The method for preparing an N-type monocrystalline silicon HBC solar cell structure according to claim 6, wherein the method comprises the following steps: the phosphorus doping concentration in the third step is not lower than 1e20/cm 3 。
9. The method for preparing an N-type monocrystalline silicon HBC solar cell structure according to claim 6, wherein the method comprises the following steps: in the tenth step, the TCO conducting film in the P area is made of a material with the work function larger than 5.2 ev.
10. The method for preparing an N-type monocrystalline silicon HBC solar cell structure according to claim 6, wherein the method comprises the following steps: in the tenth step, the TCO conducting film in the N area is made of a material with the work function smaller than 4.2 ev.
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