CN116130558B - Preparation method of novel all-back electrode passivation contact battery and product thereof - Google Patents
Preparation method of novel all-back electrode passivation contact battery and product thereof Download PDFInfo
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- 238000002161 passivation Methods 0.000 title claims abstract description 77
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 39
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims abstract description 39
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052796 boron Inorganic materials 0.000 claims abstract description 34
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 26
- 239000011574 phosphorus Substances 0.000 claims abstract description 26
- 230000005641 tunneling Effects 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 22
- 239000002002 slurry Substances 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 238000007639 printing Methods 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 230000004913 activation Effects 0.000 claims abstract description 7
- 230000003213 activating effect Effects 0.000 claims abstract description 6
- 239000003513 alkali Substances 0.000 claims description 18
- 238000004140 cleaning Methods 0.000 claims description 18
- 238000005498 polishing Methods 0.000 claims description 18
- 229910004205 SiNX Inorganic materials 0.000 claims description 15
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 15
- 238000007650 screen-printing Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 238000005245 sintering Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 8
- 239000005388 borosilicate glass Substances 0.000 claims description 5
- 239000005360 phosphosilicate glass Substances 0.000 claims description 5
- 238000005554 pickling Methods 0.000 claims description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 238000005406 washing Methods 0.000 claims description 2
- 229910017107 AlOx Inorganic materials 0.000 claims 5
- 230000006798 recombination Effects 0.000 abstract description 14
- 238000005215 recombination Methods 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 230000008021 deposition Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 7
- 238000007747 plating Methods 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 238000005234 chemical deposition Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 13
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000002310 reflectometry Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 102100021765 E3 ubiquitin-protein ligase RNF139 Human genes 0.000 description 2
- 101001106970 Homo sapiens E3 ubiquitin-protein ligase RNF139 Proteins 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000001627 detrimental effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000011056 performance test Methods 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000011863 silicon-based powder Substances 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- -1 silver aluminum Chemical compound 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
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Abstract
The invention belongs to the field of solar photovoltaic industry, and particularly relates to a preparation method of a novel all-back electrode passivation contact battery and a product thereof. An ultrathin tunneling oxide layer is formed on the back surface in a one-step low-temperature diffusion deposition mode, an intrinsic microcrystalline silicon layer is formed in a low-pressure gas-phase chemical deposition mode, then a boron slurry and a phosphorus slurry are used for printing on the intrinsic microcrystalline silicon layer to form a selective boron and phosphorus doped region, the technological processes of polysilicon round plating removal, mask layer growth and high-temperature diffusion are omitted, round expansion caused by incapability of controlling air flow single-sided performance in the high-temperature diffusion process is avoided, then boron and phosphorus are doped into the intrinsic microcrystalline silicon layer at the same time by high-temperature annealing, wherein the boron doped fine gate pattern region forms a p+ layer, and the phosphorus doped fine gate pattern region forms an n+ layer. Activating the activity of doping elements in the p+ layer and the n+ layer through the activation of silicon-based ectopic elements; the current is facilitated to be conveyed, and the recombination caused by carrier transportation is reduced.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a novel all-back electrode passivation contact cell and a product thereof.
Background
At present, environmental problems are concerned, the large-scale application of new energy is urgent, solar energy can be regarded as inexhaustible energy, and the crystalline silicon solar cell has higher cost performance under the continuous progress of the technology. In recent years, single crystal silicon batteries such as: the structural superiority of PERC and TOPCon has gained industry-consistent acceptance, but due to certain limitations, further improvement of photoelectric conversion performance is still limited, so that the field of view needs to be further widened to obtain higher cost performance.
In recent years, the PERC (Passivated Emitter and Rear Cell) solar cell with the p-type monocrystalline silicon substrate has been produced in a large-scale industrialized mode, but the highest conversion efficiency of a large-area monocrystalline PERC cell laboratory is only 24.06%, and the mass production level is about 23.5%. And most recombination losses are due to metal contacts when the efficiency of silicon solar cells approaches 23%. At present, the mass production efficiency of the large-scale expansion TOPCon (Tunnel Oxide Passivated Contacts) and HJT (Heterojunction with Intrinsic Thin Layer) batteries reaches 24.5 percent. The evolution from PERC to TOPCon and HJT is a constant improvement in passivation, according to a limiting efficiency of 28%. Passivation contacts have therefore been a focus of research in the photovoltaic industry.
The full back electrode passivation contact cell is the highest level of crystalline silicon research and development and manufacture, and is currently becoming a hot spot for the research and development of new generation technology of solar cells. The doped polysilicon/microcrystalline silicon film with the full coverage of the back surface is adopted for passivation, and the passivation contact is one-dimensional, namely, the back surface recombination is effectively reduced, the open-circuit voltage and the filling factor are improved, and meanwhile, the short-circuit current is improved due to the fact that the front surface is not shielded, so that the higher battery efficiency is obtained. The full back electrode passivation contact battery is the biggest difference from the conventional passivation contact battery in that the contact electrodes of PN junction, substrate and emission area are all made on the back of the battery in an interdigital shape, so that the shading of the front surface metal grid line is completely eliminated, meanwhile, the influence of the front surface anti-reflection structure on electrode contact is not required to be considered, and more optimization space and huge potential are provided for the front surface light trapping structure and lower reflectivity. However, the technical disadvantage is that the process steps are complex, and the photoelectric conversion efficiency and the production yield are seriously affected.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is known to a person skilled in the art.
Disclosure of Invention
The invention mainly aims to provide a preparation method of a novel full back electrode passivation contact battery, which ensures conversion efficiency and simplifies the process flow and improves the production yield of the full back electrode passivation contact battery in more than ten complicated process steps of the existing full back electrode passivation contact technology.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a preparation method of a novel all-back electrode passivation contact battery comprises the following specific steps:
s1: double-sided polishing: the monocrystalline silicon wafer is used as a matrix, and surface morphology treatment is carried out on the monocrystalline silicon wafer;
s2: depositing a tunneling oxide layer and an intrinsic microcrystalline silicon layer: growing a tunneling oxide layer and an intrinsic microcrystalline silicon layer on one side of a monocrystalline silicon wafer by adopting an LPCVD/PECVD/PVD mode, and marking the tunneling oxide layer and the intrinsic microcrystalline silicon layer as the back side;
s3: interdigital pattern: printing on the intrinsic microcrystalline silicon layer on the back through boron slurry and phosphorus slurry to respectively form an interdigital boron-doped fine gate pattern and a phosphorus-doped fine gate pattern;
s4: high temperature annealing and ectopic activation: forming an interdigital n+ layer and a interdigital p+ layer on the back surface respectively through high-temperature annealing in a thermal oxidation mode; the doping concentration is mainly determined by the content of the different element slurry, namely boron slurry and phosphorus slurry, and the printing height. And then activating the silicon-based ectopic element, wherein the sheet resistance of the n+ layer is controlled to be 60-100 ohms, and the sheet resistance of the p+ layer is controlled to be 100-200 ohms.
S5: isolation tape between N/P (tree): performing laser film opening at the interdigital P/N juncture to expose the N/P type silicon substrate;
s6: front surface field: pickling to remove the front surface of the intrinsic microcrystalline silicon layer, which is made of HF/HNO 3 The corrosion rates of the silicon and the tunneling oxide layer are higher, compared with the chained HF+alkali polishing around platingThe method can clean the intrinsic microcrystalline silicon layer on a chain machine by one-time etching. Forming a front suede by using a groove type alkali velvet making mode; meanwhile, borosilicate glass and phosphosilicate glass generated in the step S4 are removed in a pickling and efficient cleaning mode, so that a clean and efficient surface is obtained; and then shallow boron doping is carried out, a front emitter is formed on the front surface, and the sheet resistance of the p+ layer on the front surface is 200-300 ohms.
S7: passivation layer: depositing an AlOx passivation layer and a SiNx passivation layer on the front surface and the back surface of the monocrystalline silicon wafer at the same time;
s8: screen printing: screen printing on the back side to form p+ finger and n+ finger; and sintering to obtain the finished product.
Further, in step S1, an n/p type silicon wafer with high minority carrier lifetime is used as a substrate, and alkali/hydrogen peroxide pre-cleaning is performed in a groove type machine, wherein alkali and H 2 O 2 The volume ratio of (1): 1-1:3, the temperature is 70-90 ℃ and the time is 2-6min. Organic and particulate matters on the surface of the original silicon wafer can be effectively removed; and then polishing is carried out in an alkali solution, wherein the volume ratio of the alkali to the polishing additive is 10:1-5:1, the temperature is 70-90 ℃ and the time is 2-6min, and the corrosion of alkali can be slowed down by the molecular adsorption action of the polishing additive, so that better flatness is formed. Specifically, an n-type silicon wafer with high minority carrier lifetime can be used as a silicon substrate, and the resistivity of the n-type silicon wafer is 0.3-1.5 omega cm, and the minority carrier lifetime is the same as that of the n-type silicon wafer>1ms. Or a p-type silicon wafer with high minority carrier lifetime is used as a silicon substrate, the resistivity is 1-2 omega cm, and the minority carrier lifetime is prolonged>0.5ms. The improvement of minority carrier lifetime has a larger gain on efficiency, but the resistivity needs to be balanced to avoid affecting the contact performance, which is a process of balancing minority carrier lifetime and resistivity with each other.
Further, in step S2, a good decoupling layer and a contact volume layer can be formed, wherein the decoupling layer, that is, the tunneling oxide layer, can effectively block the contact volume layer from directly contacting the silicon substrate, and the contact volume layer, that is, the intrinsic microcrystalline silicon layer, forms a container similar to a container filled with electrons/holes after being doped with boron and phosphorus, and can form a good contact. The thickness of the tunneling oxide layer is 1-2.5nm, an effective barrier cannot be formed when the thickness is lower than 1nm, and tunneling is difficult to form when the thickness is higher than 2.5 nm; the thickness of the intrinsic microcrystalline silicon layer is 100-500nm. A thickness of 100nm or more can form better contact performance, but not too high, and a parasitic absorption higher than 500nm can generate low collection rate of short-circuit current density.
Further, in step S3, the desired n+ layer and p+ layer may be formed by screen printing in a patterning manner at one time. Respectively printing boron slurry and phosphorus slurry on the intrinsic microcrystalline silicon layer to form an interdigital pattern, wherein the boron doped fine gate pattern region forms a p+ layer, and the line width of the p+ layer is 70-120 mu m; below 70 μm does not facilitate alignment of electrode prints; higher than 120 μm may lead to increased surface recombination, resulting in unnecessary losses; the phosphorus doped fine grid pattern region forms an n+ layer, and the line width of the n+ layer is 70-120 mu m; likewise, less than 70 μm is detrimental to alignment of electrode printing; higher than 120 μm may result in increased recombination, causing unnecessary losses; the line spacing between the p+ layer and the n+ layer is 10-30 μm. The interval is lower than 10 mu m, which is not beneficial to blocking the transverse current conduction of n/p, and leads to the increase of the leakage rate; but above 30, excessive losses are incurred to collect current.
Further, in step S4, the high temperature annealing is performed with aerobic pushing at 950 ℃, and the process time is 2 hours; wherein the surface of the n+ layer has a maximum concentration of 1-6X10 20 atoms/cm 3 The concentration reaches 1X 10 20 atoms/cm 3 Only good contact can be made, but above 6 x 10 20 atoms/cm 3 Additional auger recombination may result. Junction depths of 0.1-0.2 μm, below 0.1 μm are detrimental to forming good ohmic contacts, above 0.2 μm result in heavier auger recombination; the highest concentration of the surface of the p+ layer is 1-10X10 19 atoms/cm 3 Since the solid solubility of boron in silicon is limited to 1×10 20 atoms/cm 3 Under the condition of the existing slurry, the concentration reaches 1 multiplied by 10 19 atoms/cm 3 Only good contact can be made, but above 10 x 10 19 atoms/cm 3 Additional auger recombination may result. Junction depths of 0.3-0.6 μm, with lower p+ surface concentrations, require greater than 0.3 μm for good ohmic contact, but greater than 0.6 μm also results in heavier auger recombination; then silicon-based ectopic element activation is carried out, and an n+ layer is formedThe sheet resistance of the p+ layer is controlled to be 60-100 ohms and the sheet resistance of the p+ layer is controlled to be 100-200 ohms. The current is facilitated to be conveyed, and the recombination caused by carrier transportation is reduced.
In step S5, compared with the mask back etching, the method has the advantages of simple process flow and low cost, and the method performs laser film opening at the P/N interface of the back interdigital to expose the N/P type silicon substrate, wherein the back N type layer and the P type layer are mutually alternated, and a PN junction is formed on the N/P interface. The slotting depth is 2-5 mu m, which is mainly limited by the inward expansion depth of n+/p+ in Si, and better insulation can be formed when the slotting depth is higher than 2 mu m, but unnecessary current loss can be caused when the slotting depth is higher than 5 mu m, the line width is 15-45 mu m, the interval is lower than 15 mu m, and the transverse current conduction of P/N is not blocked, so that the leakage rate is increased; but above 45 μm, excessive losses are incurred to collect current.
Further, in step S6, the front side of the intrinsic silicon layer is removed by chain pickling/acid etching, which is performed by HF/HNO 3 The corrosion rates of the silicon and the oxide layer are higher, and compared with the round plating cleaning of chain type HF (high frequency) alkali polishing, the round plating cleaning can etch the intrinsic silicon layer on a chain type machine at one time. Forming a good front suede by using a groove type alkali velvet making mode; the edge of the silicon wafer inevitably diffuses phosphorus or boron during diffusion due to thermal oxidation. The photo-generated electrons collected at the front side of the PN junction flow to the back side of the PN junction along the region where phosphorus or boron is diffused along the edge, causing a short circuit. Therefore, the phosphosilicate glass layer and the borosilicate glass layer are required to be removed in battery production, and the phosphosilicate glass layer and the borosilicate glass layer are removed in an acid washing and efficient cleaning mode, so that a clean and efficient surface is obtained. And then shallow boron doping is carried out on the front surface, a front emitter is formed on the front surface, and the sheet resistance of the p+ layer on the front surface is 200-300 ohms. The current is facilitated to be conveyed, and the recombination caused by carrier transportation is reduced.
Further, in step S7, a plasma atomic layer deposition (PEALD)/Atomic Layer Deposition (ALD) technique is used to perform double-sided passivation on aluminum oxide (AlOx), where the thicknesses of the front and back AlOx passivation layers are 2-20nm; wherein, the thickness of the metal film is larger than 2nm, which can achieve good passivation effect, and too high causes cost waste and mismatch of metallization process; the front and back sides of the silicon nitride (SiNx) are plated in a PECVD mode, the thickness of the front and back SiNx passivation layers is 80-90nm, the thickness is the optimal range value of a blue film, light can be well absorbed, the refractive index is 1.8-2.1, the PID effect is considered, and excessive high refractive index can cause extinction absorption, so that current collection is not facilitated.
Further, in step S8, non-burn-through silver paste is adopted to form p+ finger and n+ finger through screen printing on the back surface, and the finished product is obtained through a sintering process at 700-850 ℃. The sintering temperature of the non-burn-through slurry can meet the requirement of contact performance at 700 ℃, but the sintering temperature higher than 850 ℃ can lead to silver to be internally expanded into Si, so that unnecessary metal compounding is caused. Therefore, the sintering temperature needs to be strictly controlled, and the performance of the finished product is ensured.
The second purpose of the invention is to produce a novel all-back electrode passivation contact battery according to the novel preparation method, thereby realizing the industrialized popularization of the all-back electrode passivation contact battery.
The novel full back electrode passivation contact battery takes an N/P type silicon wafer with high minority carrier lifetime as a matrix, wherein the front surface of the matrix is sequentially provided with a front surface field, an AlOx passivation layer and a SiNx passivation layer, the back surface of the matrix is sequentially provided with a tunneling oxide layer, a p+ layer formed by a boron-doped intrinsic microcrystalline silicon layer, an n+ layer formed by a phosphorus-doped intrinsic microcrystalline silicon layer, an AlOx passivation layer, a SiNx passivation layer, a p+ finger, an n+ finger and an isolation belt between N/P.
The invention has the beneficial effects that:
according to the invention, an ultrathin tunneling oxide layer is formed on the back surface in a one-step low-temperature diffusion deposition mode, an intrinsic microcrystalline silicon layer is formed in a low-pressure gas-phase chemical deposition mode, then a boron slurry and a phosphorus slurry are used for printing on the intrinsic microcrystalline silicon layer to form a selective boron and phosphorus doped region, the single-sided nature of the printing mode is benefited, the technological processes of polysilicon round plating removal, mask layer growth and high-temperature diffusion are omitted, round expansion caused by incapability of controlling the single-sided nature of gas flow in the high-temperature diffusion process is avoided, then boron and phosphorus are doped into the intrinsic microcrystalline silicon layer simultaneously by utilizing high-temperature annealing, wherein the boron doped fine gate pattern region forms a p+ layer, and the phosphorus doped fine gate pattern region forms an n+ layer. Activating the activity of doping elements in the p+ layer and the n+ layer through the activation of silicon-based ectopic elements; the current is facilitated to be conveyed, and the recombination caused by carrier transportation is reduced. The lateral conductivity is increased compared to the amorphous or nanocrystalline layer in the heterojunction. On the other hand, the n-type POLO (nPOLO) and the p-type POLO (pPOLO) contacts are separated through laser film opening, so that the direct contact of the p+ and n+ type polycrystalline silicon regions with high defects is avoided, and the strong recombination is generated. The process flow is simplified as a whole, the investment is reduced, the yield is improved by more than 10%, and the industrialized popularization is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of a novel full back electrode passivation contact cell in an embodiment of the invention;
FIG. 2 is a flow chart of the preparation of a novel all back electrode passivation contact cell in an embodiment of the invention;
FIG. 3 is a flow chart of the preparation of a conventional all back electrode passivation contact cell of comparative example 1;
fig. 4 is a flow chart of the preparation of a conventional all back electrode passivation contact cell of comparative example 2.
Reference numerals: 1. a base; 2. a front surface field; 3. an AlOx passivation layer; 4. a SiNx passivation layer; 5. tunneling the oxide layer; 6. doping the boron intrinsic polycrystalline silicon to form a p++ layer; 7. doping phosphorus intrinsic polysilicon to form an n+ layer; 8. an AlOx passivation layer; 9. a SiNx passivation layer; 10. p+ finger; 11. n+ finger; 12. isolation strips between N/P.
Detailed Description
In order to further illustrate the technical means and effects adopted by the invention to achieve the preset aim, the preparation method of the novel all-back electrode passivation contact battery provided by the invention has the specific implementation mode, the characteristics and the effects, and the detailed description is as follows.
In the examples of the present invention, commercially available materials were sourced as follows:
example 1
The manufacturing steps of the novel all-back electrode passivation contact battery shown in the figures 1-2 are as follows:
an n-type silicon wafer with high minority carrier lifetime is used as a substrate, and the resistivity is 0.5 omega cm, and the minority carrier lifetime is more than 1.5ms.
S1: double-sided polishing: in the trough machine, RCA1# (NaOH/H) is adopted first 2 O 2 ) Pre-cleaning; and then alkali polishing is performed in an alkali polishing solution.
S2: depositing a tunneling oxide layer and an intrinsic microcrystalline silicon layer: in tube LPCVD (low pressure vapor chemical deposition), a tunneling oxide layer and an intrinsic microcrystalline silicon layer are deposited on both sides, wherein the thickness of the tunneling oxide layer is 1nm, and the thickness of the intrinsic microcrystalline silicon layer is 300nm.
S3: interdigital pattern: printing boron slurry and phosphorus slurry on the intrinsic microcrystalline silicon layer by utilizing a screen printing technology to form a required interdigital pattern, wherein a p+ layer is formed in the boron doped region, and the line width of the p+ layer is 100 mu m; forming an n+ layer by doping the fine gate pattern with phosphorus, wherein the line width of the n+ layer is 90 mu m; the line spacing of the p+ layer and the n+ layer was 15 μm.
S4: high temperature annealing and ectopic activation: aerobic propulsion is carried out at 950 ℃ for a process time of less than 2 hours. The highest concentration of the surface of the formed p+ layer is 5×10 19 atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the The highest concentration of the surface of the n+ layer is 2×10 20 atoms/cm 3 . Then activating silicon-based ectopic elements; the sheet resistance of the n+ layer is 60-100 ohms, and the sheet resistance of the p+ layer is 100-200 ohms.
S5: isolation tape between N/P: carrying out laser grooving on the back surface by utilizing the wavelength 532nm of a nanosecond laser, wherein the grooving depth is 3 mu m, and the width is 30 mu m;
s6: front surface field: and removing the front winding coating by using chain type alkali cleaning, and then performing front texturing in a groove type alkaline solution. Meanwhile, borosilicate glass and phosphosilicate glass are removed by pickling, so that a clean and efficient surface is obtained; then shallow boron doping is carried out, and a front emitter is formed on the front surface;
s7: passivation layer: depositing AlOx passivation layers on the front surface and the back surface of the monocrystalline silicon wafer simultaneously by utilizing an Atomic Layer Deposition (ALD) technology; the thickness of the AlOx passivation layer is controlled to be 4nm; and then plating silicon nitride on the front and back surfaces to form SiNx passivation layers, wherein the thickness of the SiNx passivation layers is controlled at 85nm, and the refractive index is 1.95.
S8: screen printing: firstly, printing a main grid on the back, secondly, printing an n+ layer and a p+ layer fine grid to form a p+ finger and an n+ finger, and finally, completing the manufacturing of a finished product through sintering process temperature of 760 ℃.
Example 2
The manufacturing steps of the novel full back electrode passivation contact battery are as follows:
the p-type silicon chip with high minority carrier lifetime is used as a substrate, and the resistivity is 1.5 omega cm, and the minority carrier lifetime is more than 0.5ms.
S1: double-sided polishing: in the trough machine, RCA1# (NaOH/H) is adopted first 2 O 2 ) Pre-cleaning; and then alkali-polished in TMAOH (tetramethylammonium hydroxide) polishing solution.
S2: depositing a tunneling oxide layer and an intrinsic microcrystalline silicon layer: in the tube PECVD (plasma chemical vapor deposition), a tunneling oxide layer and an intrinsic microcrystalline silicon layer are deposited, wherein the thickness of the tunneling oxide layer is 2.5nm, and the thickness of the intrinsic microcrystalline silicon layer is 200nm.
S3: interdigital pattern: spraying a boron source and a phosphorus source onto the intrinsic microcrystalline silicon layer by using an ink-jet printing technology to form a required interdigital pattern, wherein a p+ layer is formed in the boron doped region, and the line width of the p+ layer is 90 mu m; forming an n+ layer by doping the fine gate pattern with phosphorus, wherein the line width of the n+ layer is 85 mu m; the line spacing is 10 μm.
S4: high temperature annealing and ectopic activation: aerobic propulsion is carried out at 950 ℃ for a process time of less than 2 hours. Forming p+ layer with surface concentration of 7×10 19 atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the Surface concentration of n+ layer 3×10 20 atoms/cm 3 . Then activating silicon-based ectopic elements; square of n+ layerThe barrier is 60-100 ohms and the sheet resistance of the p+ layer is 100-200 ohms.
S5: isolation tape between N/P: the back side was laser grooved with a picosecond laser to a depth of 2 μm and a width of 25 μm.
S6: front surface field: and (3) removing the front winding coating by using chain acid cleaning, and then performing front texturing in a groove type TMAHH solution. And finally, removing the oxide layer on the back by using HF with the concentration of 5% by mass. Then shallow boron doping is carried out, and a front emitter is formed on the front surface;
s7: passivation layer: depositing AlOx passivation layers on the front surface and the back surface of the monocrystalline silicon wafer simultaneously by utilizing an Atomic Layer Deposition (ALD) technology; the thickness of the AlOx passivation layer is controlled to be 6nm; and then plating silicon nitride on the front and back surfaces to form SiNx passivation layers, wherein the thickness of the SiNx passivation layers is controlled to be 78nm, and the refractive index is 2.0.
S8: screen printing: first, the main grid is printed on the back, and then the n+ layer and the p+ layer fine grid are printed. And forming p+ finger and n+ finger, and finally completing the manufacturing of the finished product through the sintering process temperature of 770 ℃.
Comparative example 1
The manufacturing process of the full back electrode passivation contact battery shown in fig. 3 is as follows:
(1) Double-side polishing, namely, taking a monocrystalline silicon wafer as a silicon substrate, and carrying out surface morphology treatment on the monocrystalline silicon wafer;
(2) Tunnel oxide layer/microcrystalline silicon deposition-growing a silicon oxide layer by a thermal oxidation mode for 1-2nm, and performing microcrystalline silicon deposition by an LPCVD mode for 400nm;
(3) Boron doping annealing, namely taking boron trichloride as a boron source, and doping for 100min at 900-1000 ℃;
(4) Mask layer growth-growing a 60nm oxide layer as a mask layer in a thermal oxidation mode;
(5) Laser film opening 1- -thin gate pattern is formed in boron doped region with power of 60W by 532nm laser;
(6) Cleaning 1, namely cleaning silicon powder in a slotting area by adopting an alkali polishing mode, and cleaning by hydrofluoric acid to obtain a clean surface;
(7) Tunnel oxide layer/microcrystalline silicon deposition-growing a silicon oxide layer by a thermal oxidation mode for 2nm, and performing microcrystalline silicon deposition by an LPCVD mode for 200nm;
(8) Phosphorus doping annealing, namely doping for 120min at 900 ℃ by taking phosphorus oxychloride as a phosphorus source;
(9) Single-side texturing-groove alkali texturing mode to form a suede with reflectivity of 8-11%;
(10) Laser film opening 2-thin gate pattern is formed in the phosphor doped region with power 60W by 532nm laser;
(11) Cleaning 2, namely cleaning silicon powder in a slotting area in an alkali polishing mode, and cleaning by hydrofluoric acid to obtain a clean surface;
(12) Passivation-in situ deposition of alumina 3-6nm, PECVD deposition of silicon nitride 75-90nm;
(13) Screen-screen printing, in which the front and back electrodes are printed by screen printing and sintered in a chain sintering furnace.
Comparative example 2
A full back electrode passivation contact battery shown in FIG. 4 selects p-type monocrystalline silicon wafer with resistivity of 0.8-1.5 ohm.cm and minority carrier lifetime of > 2.5ms, thickness of 170 μm and size of 166mm×166mm; the manufacturing process comprises the following steps:
(1) Double-sided texturing-in KOH and H 2 O 2 Removing a damaged layer on the surface of the silicon wafer in the mixed solution, and then performing texturing in a KOH solution to form pyramid texture on the surface of the silicon wafer, wherein the size of the pyramid texture is controlled to be 3 mu m;
(2) After oxidation-texturing is completed, the front surface of the silicon wafer is oxidized by adopting chain oxygen at 800 ℃, and a chain hydrofluoric acid is used for removing an oxidation layer on the back surface of the silicon wafer;
(3) Polishing-alkali polishing (polishing the back of the silicon wafer) to ensure that the reflectivity of the back surface of the silicon wafer is more than 40 percent;
(4) n/p dopant doping-preparing tunneling layer (2 nm) and amorphous silicon intrinsic deposition (150 nm) on the back of silicon wafer by LPCVD process; printing solid or liquid dopants containing V group elements (one or more of phosphorus, arsenic and antimony) on the back surface of the silicon wafer locally, printing solid or liquid dopants containing III group elements (one or more of boron, gallium and indium) on the back surface of the silicon wafer locally, and isolating the printing areas of the two dopants from each other;
(5) PIN structure-then tubular normal pressure annealing at 1000 ℃ for 30min to complete the PIN structure on the back of the silicon wafer;
(6) Cleaning-obtaining a clean surface by hydrofluoric acid cleaning;
(7) Passivation-then 8nm thick aluminum oxide was deposited by ALD on both sides of the wafer and 80nm thick silicon nitride was prepared using PECVD; depositing silicon nitride with the thickness of 100nm on the back surface of the silicon wafer to finish the preparation of the battery precursor;
(8) After the passivation of the surface of the silk screen-silicon wafer is finished, the front and the back of the silicon wafer are metallized, a silver paste electrode is printed on the back of the silicon wafer and a silver aluminum paste electrode is printed on the front of the silicon wafer in sequence in a silk screen printing mode, and then the preparation of the battery is finished through sintering.
Battery performance test results
The examples were subjected to structural characterization of the blue membrane, i.e. pre-electrode preparation testing, and the performance test results are shown in table 1: the data are battery blue membrane data, the data can reflect that the scheme can be implemented, and the scheme is mainly used for providing an application scheme of a novel preparation method of the full back electrode passivation contact battery.
TABLE 1
As shown in the table above, the novel all-back electrode passivation contact battery prepared by the embodiment of the invention avoids the complicated processes of polysilicon coiling and plating removal, mask layer growth and high-temperature diffusion in the traditional preparation method of the all-back electrode passivation contact battery by optimizing the preparation flow, and can obviously shorten the process flow and simplify the preparation scheme. Comparative examples 1-2 provide a method for preparing a traditional all-back electrode passivation contact battery, which is completely different from the preparation process of the all-back electrode passivation contact battery in the application, and the result shows that the invention can achieve similar effects.
Compared with example 1, in comparative example 1, the process has more cleaning and high temperature steps, the process is too complicated, the difficulty of production line control is large, the industrialization is not facilitated, and the process yield loss is more than 10%.
In comparison with example 1, in comparative example 2, the oxidation step is added for growing the mask layer oxide layer, and in comparison with the oxidation step, the invention adopts the mode of firstly growing the back surface and forming the mask layer by using the step S4, and no additional step is needed. Meanwhile, the step S5 of the invention is not carried out in the comparison document 2, so that the leakage current is easy to be higher, and the invention forms an isolation belt between N/P through laser isolation, so that the leakage current is obviously reduced; the comparative example 2 does not have a front surface field, and the present invention cannot utilize the front surface field; the current is facilitated to be conveyed, and the recombination caused by carrier transportation is reduced. And the PIN structure formed in the comparative example 2 is difficult to control the diffusion of n/p dopants, and has lower efficiency; moreover, the internal leakage risk exists, so that the hot spot is invalid, the industrialization is not facilitated, and the process yield loss is more than 14%.
It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A preparation method of a novel all-back electrode passivation contact battery is characterized by comprising the following steps: the method comprises the following specific steps:
s1: double-sided polishing: the monocrystalline silicon wafer is used as a matrix, and surface morphology treatment is carried out on the monocrystalline silicon wafer;
s2: depositing a tunneling oxide layer and an intrinsic microcrystalline silicon layer: growing a tunneling oxide layer and an intrinsic microcrystalline silicon layer on one side of the monocrystalline silicon wafer, and marking the tunneling oxide layer and the intrinsic microcrystalline silicon layer as the back side;
s3: interdigital pattern: printing on the intrinsic microcrystalline silicon layer on the back through boron slurry and phosphorus slurry to respectively form an interdigital boron-doped fine gate pattern and a phosphorus-doped fine gate pattern;
s4: high temperature annealing and ectopic activation: high-temperature annealing, respectively forming an interdigital n+ layer and a interdigital p+ layer on the back surface; then activating silicon-based ectopic elements;
s5: isolation tape between N/P: laser film opening is carried out at the P/N juncture of the interdigital shape to expose the silicon substrate;
s6: front surface field: acid washing to remove the intrinsic microcrystalline silicon layer which is plated around on the front surface, and forming a front surface suede; meanwhile, borosilicate glass and phosphosilicate glass are removed by pickling, so that a clean and efficient surface is obtained; then shallow boron doping is carried out, and a front emitter is formed on the front surface; the sheet resistance of the front surface p+ layer is 200-300 ohm;
s7: passivation layer: depositing an AlOx passivation layer and a SiNx passivation layer on the front surface and the back surface of the monocrystalline silicon wafer at the same time;
s8: screen printing: screen printing on the back side to form p+ finger and n+ finger; and sintering to obtain the finished product.
2. The method for preparing the novel all-back electrode passivation contact battery according to claim 1, which is characterized in that: in the step S1, an n/p type silicon wafer with high minority carrier lifetime is used as a substrate, and alkali/hydrogen peroxide pre-cleaning is performed in a groove type machine, and then polishing is performed in an alkali solution.
3. The method for preparing the novel all-back electrode passivation contact battery according to claim 1, which is characterized in that: in the step S2, the thickness of the tunneling oxide layer is 1-2.5nm, and the thickness of the intrinsic microcrystalline silicon layer is 100-500nm.
4. The method for preparing the novel all-back electrode passivation contact battery according to claim 1, which is characterized in that: in the step S3, boron slurry and phosphorus slurry are printed on the intrinsic microcrystalline silicon layer respectively by utilizing a screen printing technology to form an interdigital pattern, a p+ layer is formed in a boron doped fine grid pattern area, and the line width of the p+ layer is 70-120 mu m; the phosphorus doped fine grid pattern region forms an n+ layer, and the line width of the n+ layer is 70-120 mu m; the line spacing between the p+ layer and the n+ layer is 10-30 mu m.
5. A novel all back electrode passivation according to claim 1The preparation method of the contact battery is characterized by comprising the following steps: in the step S4, the high-temperature annealing is performed with aerobic propulsion at 950 ℃, and the process time is 2 hours; wherein the surface of the n+ layer has a maximum concentration of 1-6X10 20 atoms/cm 3 The junction depth is 0.1-0.2 mu m; the highest concentration of the surface of the p+ layer is 1-10X10 19 atoms/cm 3 The junction depth is 0.3-0.6 mu m; and then shallow doping boron is carried out, the sheet resistance of the n+ layer is 60-100 ohms, and the sheet resistance of the p+ layer is 100-200 ohms.
6. The method for preparing the novel all-back electrode passivation contact battery according to claim 1, which is characterized in that: in the step S5, laser film opening is carried out at the P/N juncture of the back interdigital type, the N/P type silicon substrate is exposed, the slotting depth is 2-5 mu m, and the line width is 15-45 mu m.
7. The method for preparing the novel all-back electrode passivation contact battery according to claim 1, which is characterized in that: in the step S7, the thicknesses of the front surface AlOx passivation layer and the rear surface AlOx passivation layer are 2-20nm; the SiNx passivation layer has a thickness of 80-90nm and a refractive index of 1.8-2.1.
8. The method for preparing the novel all-back electrode passivation contact battery according to claim 1, which is characterized in that: in the step S8, non-burnt-through silver paste is adopted for screen printing on the back surface, and a sintering process is carried out at 700-850 ℃ to obtain a finished product.
9. The novel all-back electrode passivation contact battery prepared by the method according to any one of claims 1-8, which is characterized in that: the battery takes an N/P type silicon wafer with high minority carrier lifetime as a matrix, the front surface of the matrix is sequentially provided with a front surface field, an AlOx passivation layer and a SiNx passivation layer, the back surface of the matrix is sequentially provided with a tunneling oxide layer, a p+ layer formed by a boron-doped intrinsic microcrystalline silicon layer, an n+ layer formed by a phosphorus-doped intrinsic microcrystalline silicon layer, an AlOx passivation layer, a SiNx passivation layer, a p+ finger, an n+ finger and an isolation belt between N/P.
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| CN115274913A (en) * | 2021-04-30 | 2022-11-01 | 泰州中来光电科技有限公司 | Preparation method of IBC solar cell with passivation contact structure, cell, module and system |
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