CN116666479B - Efficient selective emitter crystalline silicon battery with double-sided power generation and preparation method thereof - Google Patents

Efficient selective emitter crystalline silicon battery with double-sided power generation and preparation method thereof Download PDF

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CN116666479B
CN116666479B CN202310719206.9A CN202310719206A CN116666479B CN 116666479 B CN116666479 B CN 116666479B CN 202310719206 A CN202310719206 A CN 202310719206A CN 116666479 B CN116666479 B CN 116666479B
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CN116666479A (en
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丁建宁
王芹芹
李绿洲
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Yangzhou University
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Abstract

The invention belongs to the field of solar photovoltaic industry, and particularly relates to a double-sided power generation efficient selective emitter crystalline silicon battery and a preparation method thereof. The battery takes an N/P type monocrystalline silicon wafer as a matrix, and the front side of the battery is sequentially provided with a tunneling layer, a heavily doped p++/n++ nanocrystalline compound layer, a lightly doped p++/n+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and a p++/n++ finger; the back is provided with a tunneling layer, a heavily doped n++/p++ nanocrystalline compound layer, a lightly doped n++/p+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and an n++/p++ finger in sequence. According to the invention, the high-efficiency selective emitter crystalline silicon battery with double-sided power generation is prepared, and on one hand, a front-back full-passivation contact layer is formed; the open circuit voltage can be obviously improved; on the other hand, the selective emitter is formed, so that parasitic light absorption is further reduced.

Description

Efficient selective emitter crystalline silicon battery with double-sided power generation and preparation method thereof
Technical Field
The invention belongs to the field of solar photovoltaic industry, and particularly relates to a double-sided power generation efficient selective emitter crystalline silicon battery and a preparation method thereof.
Background
Along with the photovoltaic technology around the first principle of 'unit degree electricity cost', the photovoltaic technology is continuously developed along the technical route of 'cost reduction and efficiency improvement' and 'large size and flaking'. Development to reduce the photovoltaic cost is imperative. At present, two methods for reducing the photovoltaic power cost (LCOE) exist, one is to reduce the construction and operation and maintenance costs, and the other is to improve the generated energy, effectively reduce the efficiency loss of the assembly by using the efficient battery assembly, and improve the power generation efficiency of the assembly, thereby improving the generated energy of a power station system.
Currently, in the efficient battery assembly, PERC (PassivatedEmitter andRear Cell) solar cells of P-type monocrystalline silicon substrates have been produced on a large scale with a mass production level of about 23.5%, and for conventional PERC technology, the existing process of double-sided PERC is fully compatible with it. The double-sided PERC can maintain the high conversion efficiency of the original single-sided PERC, and simultaneously the back side can generate power, so that the double-sided power generation increases the system power generation gain by about 10% -25% for the whole system. But the efficiency of PERC solar cells approaches 24%, most of the recombination losses are due to metal contact. Passivation contacts have therefore been a focus of research in the photovoltaic industry.
The current TOPCon and HJT batteries with large-scale production expansion can perfectly solve the composite loss caused by metal contact. In principle, the next-generation battery is a passivation contact battery with a double-sided selective emitter, but the high-efficiency double-sided passivation contact battery has the defects of complex process and high investment cost in the commercialized crystalline silicon battery, and is limited by industrialization. The invention aims at the complex ten or more process steps of the prior double-sided full passivation contact technology, simplifies the process flow, reduces the investment and promotes the vector production while ensuring the conversion efficiency.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is known to a person skilled in the art.
Disclosure of Invention
The first object of the invention is to provide a high-efficiency selective emitter crystalline silicon cell with double-sided power generation, by which, on one hand, a full passivation contact layer on the front and back surfaces is formed; the open circuit voltage can be obviously improved; on the other hand, the selective emitter is formed, so that parasitic light absorption is further reduced.
The technical aim of the invention is realized by the following technical scheme:
the high-efficiency selective emitter crystalline silicon battery with double-sided power generation uses an N/P type monocrystalline silicon wafer as a matrix, and the front side of the battery is sequentially provided with a tunneling layer, a heavily doped p++/n++ nanocrystalline compound layer, a lightly doped p++/n+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and a p++/n++ finger; the back is provided with a tunneling layer, a heavily doped n++/p++ nanocrystalline compound layer, a lightly doped n++/p+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and an n++/p++ finger in sequence.
Preferably, the battery takes an N/P type monocrystalline silicon wafer as a matrix, and the front surface of the battery is sequentially provided with a tunneling layer, a heavily doped p++ nanocrystalline compound layer, a lightly doped p+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and a p++ finger; the back is provided with a tunneling layer, a heavily doped n++ nanocrystalline compound layer, a lightly doped n+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and an n++ finger in sequence.
Preferably, the battery takes an N/P type monocrystalline silicon wafer as a matrix, and the front surface of the battery is sequentially provided with a tunneling layer, a heavily doped n++ nanocrystalline compound layer, a lightly doped n+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and an n++ finger; the back is provided with a tunneling layer, a heavily doped p++ nanocrystalline compound layer, a lightly doped p+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and a p++ finger in sequence.
The doped nanocrystalline layer is a polycrystalline silicon layer doped with III-group elements/V-group elements.
The second object of the invention is to provide a preparation method of a high-efficiency selective emitter crystalline silicon battery with double-sided power generation, which comprises the steps of firstly forming an ultrathin tunneling layer and a doped nanocrystalline compound layer, and then forming a nanocrystalline silicon compound re-expansion area through a high-temperature annealing process; and then a light expansion area is formed by adopting a mode of loosening a film by laser and polishing, cleaning and removing damage, so that the technological processes of removing polysilicon by winding plating, growing a mask layer and diffusing at high temperature are omitted, and the production efficiency is improved.
The technical aim of the invention is realized by the following technical scheme:
a preparation method of a double-sided power generation high-efficiency selective emitter crystalline silicon battery comprises the following operation steps:
(1) Double-sided texturing: taking an N/P type monocrystalline silicon wafer as a silicon substrate, pre-cleaning with alkali/hydrogen peroxide in a groove type machine, and then texturing to form an inverted pyramid surface structure; the front surface is textured, the light limiting effect can be utilized, the absorption of the N/P type monocrystalline silicon wafer to sunlight is increased, the reflectivity is reduced, and the short-circuit current density Jsc is improved. Meanwhile, the reflection of light is reduced, the internal light absorption is improved, and the light utilization rate is improved. Finally, the surface area of the silicon wafer can be increased, and the PN junction area is further increased.
Preferably, in the step (1), the minority carrier lifetime of the N/P type monocrystalline silicon piece is more than 1ms, and the resistivity is 0.5-2.1 Ω cm; in the pre-cleaning process, the volume ratio of alkali to hydrogen peroxide is 1:2 to 5, the temperature is 65 to 85 ℃ and the time is 1.5 to 4 minutes; the alkali is NaOH or KOH, and then the alkali is placed in an alkali texturing solution for alkali texturing, wherein the alkali texturing solution is KOH, the additive is sodium lactate and the surfactant (wherein the additive comprises sodium hydroxide, polyether modified polysiloxane defoamer and sodium hydroxide, the polyether modified polysiloxane defoamer comprises 1:2-5 (mass ratio)), methyl glucose polyoxyethylene ether, glucose, polyacrylamide, deionized water, and the mass ratio of sodium lactate, the surfactant, methyl glucose polyoxyethylene ether, glucose, polyacrylamide and deionized water is 5:8:1:2:1:53), and the alkali texturing solution can effectively improve product defects caused by phenomena of bubble adhesion, silicon wafer floatation, silicon wafer jump and the like existing in a texturing product due to no alcohol addition. The gram weight of the thinning amount is 0.4-0.6 g, and the reflectivity is 8-10%.
(2) Front deposition of tunneling layer, p++/n++ doped nanocrystalline compound and mask layer: sequentially growing a tunneling layer, a p++/n++ doped nanocrystalline compound and a mask layer on one side of a monocrystalline silicon wafer by adopting PECVD/Cat-CVD/PVD and other modes, marking the tunneling layer as a front side, wherein the tunneling layer is one of ultrathin oxide, nitride and alumina;
a tunneling layer grows between the N/P type monocrystalline silicon piece and the p++/n++ doped nanocrystalline compound, so that the influence of doping elements on passivation is reduced, and the composite current density J is reduced 0 Meanwhile, the tunneling layer forms a tunneling barrier, so that the minority carrier can tunnel, and the minority carrier is blocked, thereby being beneficial to improving the theoretical open-circuit voltage.
The p++/n++ doped nanocrystalline compound is formed by deposition, and the selective mobility of carriers can be improved and the recombination rate of electrons and holes can be reduced by energy band bending caused by work function difference between the p++/n++ doped nanocrystalline compound and the N/P type monocrystalline silicon wafer substrate. Meanwhile, the p++/n++ doped nanocrystalline compound is a heavily doped layer, ohmic contact is formed between the p++/n++ doped nanocrystalline compound and metal, and contact resistivity and parasitic absorption are reduced.
The mask layer can reduce the coiling plating, and thin the doped nanocrystalline compound after the laser mold opening is carried out on the non-electrode area to form a lightly doped area.
Preferably, in the step (2), when the p++ doped nanocrystalline compound is deposited on the front surface, the nanocrystalline compound is doped in situ by adopting a III group element, the thickness of the tunneling layer is 1-2 nm, the thickness of the doped nanocrystalline compound is 100-500 nm, and the thickness of the mask layer is 20-100 nm;
when n++ doped nanocrystalline compound is deposited on the front surface, V group element is adopted to dope nanocrystalline compound in situ, the thickness of tunneling layer is 1-2 nm, the thickness of doped nanocrystalline compound is 50-200 nm, and the thickness of mask layer is 20-50 nm.
(3) Backside texture: forming a polished surface/acid etched surface on the back surface by adopting a chain type alkali polishing/acid etching mode, and then cleaning the back surface;
the back surface is a polished surface, so that the internal reflection of light can be increased, the recombination rate of the carrier surface is reduced, and the photoelectric conversion efficiency of the battery is improved. The polished surface morphology of the back of the crystalline silicon cell is beneficial to the back reflection of long-wave band light and the uniformity of a film layer formed on the back subsequently.
Preferably, in the step (3), the washing is performed using 5 to 6 mass% hydrochloric acid.
(4) A tunneling layer, an n++/p++ doped nanocrystalline compound and a mask layer are deposited on the back surface: sequentially growing a tunneling layer, an n++/p++ doped nanocrystalline compound and a mask layer on the back surface of the monocrystalline silicon wafer by adopting PECVD/Cat-CVD/PVD and other modes, wherein the tunneling layer is one of ultrathin oxide, nitride and alumina;
preferably, in the step (4), when the p++ doped nanocrystalline compound is deposited on the front surface, the n++ doped nanocrystalline compound is deposited on the back surface, the nanocrystalline compound is doped in situ by adopting V group elements, the thickness of the tunneling layer is 1-2 nm, the thickness of the doped nanocrystalline compound is 50-200 nm, and the thickness of the mask layer is 20-50 nm;
when n++ doped nanocrystalline compounds are deposited on the front surface, p++ doped nanocrystalline compounds are deposited on the back surface, III group elements are adopted to dope nanocrystalline compounds in situ, the thickness of the tunneling layer is 1-2 nm, the thickness of the doped nanocrystalline compounds is 100-500 nm, and the thickness of the mask layer is 20-100 nm.
(5) High-temperature annealing: and introducing inert gas 5-10 slm to anneal the monocrystalline silicon piece at high temperature, wherein the inert gas is nitrogen, argon, hydrogen and the like. Activating doping elements on the front side and the back side at high temperature to respectively form full passivation contact structures on the front side and the back side of the monocrystalline silicon wafer; namely a p++ region and an n++ region. The invention adopts in-situ doping, namely, doping of III group elements/V group elements is directly carried out in the process of depositing poly, and then adopts high-temperature annealing to activate the doping source, namely, the n++ region and the p++ region are simultaneously activated in one step, thereby omitting an additional high-temperature diffusion process.
Preferably, in the step (5), the high-temperature annealing temperature is 850-900 ℃ and the time is 30-60 min, and full passivation contact structures are respectively formed on the front surface and the back surface of the battery; wherein the surface concentration of the p++ region is 5 to 10×10 19 atom/cm 3 The junction depth is 0.12-0.52 mu m, and the sheet resistance is 50-150 ohm; the surface concentration of the n++ region is 1 to 10×10 20 atom/cm 3 The junction depth is 0.07-0.22 mu m; the sheet resistance is 35-150 ohm.
(6) Laser film opening and light expansion region formation: opening the mask layers on the front and back surfaces, wherein the opening width is 0.5-1.5 mm; then thinning the doped nanocrystalline compound in the film opening area, forming light expansion areas on the front and back surfaces respectively, and then adopting HF acid washing with the mass fraction of 5-6% and high-efficiency cleaning (O) 3 Acid washing) to remove borosilicate glass and phosphosilicate glass to obtain clean and efficient surfaces; the step can remove polysilicon such as borosilicate glass/phosphosilicate glass generated during in-situ diffusion, does not need to carry out additional mask layer growth and removal processes, simplifies the process steps and improves the mass production efficiency.
Preferably, in the step (6), the mask layer of the n++ region is opened by utilizing light with the laser power of 25-50W and the wavelength of 532nm, and then the doped nanocrystalline compound of the opened region is thinned in a groove type alkali polishing groove to form an n+ region, wherein the junction depth is 0.03-0.1 mu m; the sheet resistance is 150-250 ohm;
opening a mask layer of the p++ region by utilizing light with the laser power of 25-50W and the wavelength of 532nm, and then thinning the doped nanocrystalline compound of the opening region in a groove type alkali polishing groove to form a p+ region, wherein the junction depth is 0.05-0.15 mu m; the sheet resistance is 200-300 ohm.
(7) Passivation layer: passivating aluminum oxide on the front side and the back side of the monocrystalline silicon piece by utilizing an Atomic Layer Deposition (ALD) technology, wherein the thickness of the aluminum oxide is 2-20 nm; then passivating silicon nitride on the front and back of the monocrystalline silicon wafer, wherein the thickness of the silicon nitride is 70-90 nm, and the refractive index is 1.8-2.1;
(8) Screen printing: using non-burn-through pure silver paste, and adopting screen printing to form p++ finger and n++ finger; during printing, firstly printing a main grid and a fine grid on the back; and then turning over and printing the main grid and the fine grid on the front surface, and completing the manufacture of the finished product through a sintering process at 700-850 ℃.
The beneficial effects of the invention are as follows:
the method comprises the steps of forming an ultrathin tunneling layer on the front side and the back side respectively through low-temperature diffusion deposition or chemical vapor deposition, forming a doped nanocrystalline compound layer through in-situ doping in a plasma chemical vapor deposition mode, and forming a nanocrystalline silicon compound re-expansion area through a high-temperature annealing process; at this time, the high-temperature annealing activates the doping source, and the extra high-temperature diffusion process flow is omitted. Then a light expansion area is formed by adopting a mode of loosening a film by laser and polishing, cleaning and removing damage, and meanwhile, the winding plating formed in the polysilicon deposition process is removed, so that the extra winding plating removal of polysilicon is omitted; compared with the prior art, the invention forms the full passivation contact layer on the front and back surfaces; the open circuit voltage can be obviously improved; on the other hand, a selective emitter is formed, and parasitic light absorption is further reduced. The process flow is simplified as a whole, the investment is reduced, the efficiency is improved by more than 0.5%, and the industrialized popularization is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of a structure of a high-efficiency selective emitter crystalline silicon cell for double-sided power generation in example 1 of the present invention;
the reference numerals in fig. 1 are: 101. a base; 102. a tunneling layer; 103. heavily doped p++ nanocrystalline compound layer; 104. lightly doping the p+ nanocrystalline compound layer; 105. an aluminum oxide/silicon nitride passivation layer; 106. a tunneling layer; 107. heavily doped n++ nanocrystalline compound layer; 108. lightly doping the n+ nanocrystalline compound layer; 109. an aluminum oxide/silicon nitride passivation layer; 110. p++ finger; 111. n++ finger;
FIG. 2 is a schematic diagram of a structure of a high-efficiency selective emitter crystalline silicon cell for double-sided power generation in example 2 of the present invention;
the reference numerals in fig. 2 are: 201. a base; 202. a tunneling layer; 203. heavily doped n++ nanocrystalline compound layer; 204. lightly doping the n+ nanocrystalline compound layer; 205. an aluminum oxide/silicon nitride passivation layer; 206. a tunneling layer; 207. heavily doped p++ nanocrystalline compound layer; 208. lightly doping the p+ nanocrystalline compound layer; 209. an aluminum oxide/silicon nitride passivation layer; 210. n++ finger; 211. p++ finger;
FIG. 3 is a flow chart of the fabrication of a high efficiency selective emitter crystalline silicon cell for double sided power generation in an embodiment of the present invention;
fig. 4 is a schematic structural view of a double-sided selective emission highly efficient crystalline silicon cell according to comparative example 1 of the present invention;
the reference numerals in fig. 4 are: 401. a substrate; 402. a tunneling alumina layer 403, a front heavily doped intrinsic polysilicon layer; 404. a P+ layer; 405. an N++ layer; 406. tunneling the oxide layer; 407. forming an N+ layer by intrinsic polycrystalline silicon; 408. an alumina passivation layer; 409. a silicon nitride passivation layer; 410. a silicon nitride passivation layer; 411. p+ finger; 412. n+ finger;
fig. 5 is a schematic structural diagram of an N-type TOPCon solar cell according to comparative example 1 of the present invention;
the reference numerals in fig. 5 are: 501. an N-type crystalline silicon matrix; 502. tunneling oxide layer; 503. an intrinsic amorphous silicon layer; 504. a p+ doped layer; 505. passivating the antireflection film; 506. a passivation film; 507. masking; 508. a borosilicate glass layer; 509. a front side auxiliary grid; 510. and a back side auxiliary grid.
Detailed Description
In order to further describe the technical means and effects adopted by the invention to achieve the preset aim, the specific implementation mode, the characteristics and the effects of the high-efficiency selective emitter crystalline silicon battery for double-sided power generation provided by the invention are described in detail below.
In the examples of the present invention, commercially available materials were sourced as follows:
example 1
As shown in FIG. 1, an efficient selective emitter crystalline silicon cell with double-sided power generation is characterized in that an N-type silicon wafer with minority carrier lifetime of >1ms and resistivity of 0.5-2.1 Ω & cm is used as a substrate 101, a tunneling layer 102, a heavily doped p++ nanocrystalline compound layer 103, a lightly doped p+ nanocrystalline compound layer 104, an alumina/silicon nitride passivation layer 105 and a p++ finger110 are sequentially arranged on the front surface of the cell; the back surface is provided with a tunneling layer 106, a heavily doped n++ nanocrystalline compound layer 107, a lightly doped n+ nanocrystalline compound layer 108, an alumina/silicon nitride passivation layer 109 and an n++ finger111 in sequence.
As shown in fig. 3, a preparation method of a double-sided power generation high-efficiency selective emitter crystalline silicon battery comprises the following preparation steps:
(1) Double-sided texturing: in the trough machine, RCA1# (NaOH/H) is adopted first 2 O 2 ) Pre-cleaning; then alkali texturing is carried out in alkali texturing solution, the gram weight is 0.4g, and the reflectivity is 8-10%.
(2) Front deposition of tunneling layer, p++ doped nanocrystalline compound and mask layer: and a tunneling silicon oxynitride layer (SiOxNy) is grown on one side in a PECVD mode, the thickness is 1.5nm, a boron element is utilized to dope the nanocrystalline compound in situ, the thickness is 300nm, and SiNx is deposited as a mask layer, and the thickness is 40nm.
(3) Single-sided polishing: and forming a back polished surface by adopting a chained alkali polishing mode, and then cleaning by using hydrochloric acid/hydrofluoric acid mixed acid with the mass fraction of 5% of salt.
(4) A tunneling layer, an n++ doped nanocrystalline compound and a mask layer are deposited on the back surface: and growing a tunneling oxide layer on one side of the polished surface in a PECVD (plasma enhanced chemical vapor deposition) mode, wherein the thickness is 1.5nm, adopting phosphorus in-situ doped nanocrystalline compound, the thickness is 120nm, and depositing SiNx as a mask layer, and the thickness is 40nm.
(5) High-temperature annealing: introducing nitrogen gas 5-10 slm, annealing at 900 deg.C for 50min, forming p++ layer and n++ layer on the front and back, and concentrating the surface of p++ layer by 5×10 19 atom/cm 3 The junction depth is 0.32 mu m, and the sheet resistance is controlled at 120ohm; surface concentration of n++ layer 5×10 20 atom/cm 3 Junction depth 0.14 μm; the sheet resistance was controlled at 40ohm.
(6) Laser film opening and light expansion region formation: using light with the wavelength of 532nm and laser power of 40W to perform film opening on the mask layers of the n++ layer and the p++ layer, wherein the film opening width is 1.2mm; then, thinning the film opening area by doping nano crystal compound in a groove type alkali polishing groove to form a p+ area and an n+ area, wherein the junction depth of the p+ area is 0.1 mu m, and the sheet resistance is 250ohm; the junction depth of the n+ region was 0.05 μm and the sheet resistance was 180ohm. Finally, 5 mass percent hydrofluoric acid pickling and efficient cleaning (ozone pickling) are adopted to remove borosilicate glass and phosphosilicate glass, so as to obtain a clean and efficient surface.
(7) And (3) passivation layer generation: double-sided passivation of aluminum oxide (AlOx) is performed by utilizing an Atomic Layer Deposition (ALD) technology, and the thickness is controlled to be 3nm; then plating silicon nitride on both sides, controlling the thickness of the front surface at 75nm and the refractive index at 1.9; the back surface thickness was controlled at 80nm and the refractive index was 2.1.
(8) Screen printing: printing a main grid of a back n++ layer by using non-burn-through pure silver paste, and printing a fine grid of the back n+ layer; and then turning over and printing a main grid with a front p++ layer and a fine grid with a p+ layer. And finally, the finished product is manufactured through the sintering process temperature of 750 ℃.
Example 2
As shown in fig. 2, a P-type silicon wafer with minority carrier lifetime >0.8ms and resistivity 1-1.5 Ω cm is used as a substrate 201, a tunneling layer 202, a heavily doped n++ nanocrystalline compound layer 203, a lightly doped n+ nanocrystalline compound layer 204, an alumina/silicon nitride passivation layer 205, and an n++ finger210 are sequentially arranged on the front surface of the cell; the back surface is provided with a tunneling layer 206, a heavily doped p++ nanocrystalline compound layer 207, a lightly doped p+ nanocrystalline compound layer 208, an alumina/silicon nitride passivation layer 209 and a p++ finger211 in sequence.
The manufacturing steps of the high-efficiency selective emitter crystalline silicon battery with double-sided power generation are as follows:
(1) Double-sided texturing: in the trough machine, RCA1# (NaOH/H) is adopted first 2 O 2 ) Pre-cleaning; then alkali texturing is carried out in alkali texturing solution, the gram weight is 0.35g, and the reflectivity is 9%.
(2) Depositing a tunneling layer, n++ doped nano silicon oxide and a mask layer: and a Cat-CVD mode is adopted to grow a tunneling silicon oxide layer (SiOx) on one side, the thickness is 1.6nm, the phosphorus element is doped with nano silicon oxide in situ, the thickness is 150nm, and SiOx is deposited as a mask layer, and the thickness is 50nm.
(3) Single-sided acid etching: the method comprises the steps of forming a back acid etching surface by adopting a chain hydrofluoric acid/nitric acid mixed acid mode, and then cleaning the surface by using hydrochloric acid and hydrogen peroxide with the mass fraction of 6%.
(4) Depositing a tunneling layer, p++ doped nano silicon oxide and a mask layer: and growing a tunneling oxide layer on one side of an acid etching surface in a Cat-CVD mode, wherein the thickness is 2nm, adopting boron element in-situ doped nano silicon oxide, the thickness is 350nm, and depositing SiOx as a mask layer, and the thickness is 50nm.
(5) High-temperature annealing: introducing 1% hydrogen gas, annealing at 880 deg.C for 45min to form n++ layer and p++ layer on the front and back surfaces, and surface concentration of n++ layer is 3E 20 atom/cm 3 The junction depth is 0.17 mu m, and the sheet resistance is controlled at 35ohm; surface concentration of p++ layer 1E 20 atom/cm 3 Junction depth 0.37 μm; the sheet resistance was controlled at 100 ohms.
(6) Laser film opening and light expansion region formation: using light with wavelength of 35W and 532nm to perform film opening on the mask layer in the n++ and p++ regions, wherein the film opening width is 0.8mm; then, thinning the film opening area by doping nano silicon oxide in a groove type alkali polishing groove to form a p+ area and an n+ area, wherein the junction depth of the p+ area is 0.12 mu m, and the sheet resistance is 220ohm; the junction depth of the n+ region was 0.07 μm and the sheet resistance was 150ohm. Finally, removing borosilicate glass and phosphosilicate glass by adopting a mode of mixed acid washing of hydrofluoric acid and hydrochloric acid with the mass fraction of 6%, and obtaining the clean and efficient surface.
(7) And (3) passivation layer generation: double-sided passivation of aluminum oxide is carried out by utilizing a plasma atomic layer deposition (PEALD) technology, and the thickness is controlled to be 5nm; then plating silicon nitride on both sides, controlling the thickness of the front surface at 80nm and the refractive index at 2.0; the back surface thickness was controlled at 85nm and the refractive index was 2.05.
(8) Screen printing: printing a main grid of a back p++ layer by using non-burn-through pure silver paste, and printing a fine grid of the back p+ layer; and then the front n++ main grid and the n+ layer fine grid are printed in turn. Finally, the finished product is manufactured through sintering process temperature of 760 ℃.
Comparative example 1
Patent No. ZL 202010258865.3, the invention name is: a preparation method of a double-sided selective emitter highly efficient crystalline silicon battery is disclosed. The front light-expansion area of the battery structure is a single-layer p+ layer with a non-poly structure, the recombination is heavy, and the preparation of the process flow of the selective emitter is complex.
As shown in fig. 4, a double-sided selective emitter highly efficient crystalline silicon cell, in which an N-type silicon wafer with a high minority carrier lifetime is used as a substrate 401, and a tunneling alumina layer 402, a front heavily doped intrinsic polysilicon layer 403, a p+ layer 404, an alumina passivation layer 408, a silicon nitride passivation layer 409, a p+ fine, 411 are sequentially formed on the front; the back surface is in turn an N++ layer 405, a tunnel oxide layer 406, an intrinsic polysilicon forming an N+ layer 407, a silicon nitride passivation layer 410, N+ fins, 412.
The specific battery manufacturing steps of the double-sided selective emitter highly efficient crystalline silicon battery are as follows:
the N-type silicon wafer with high minority carrier lifetime is used as a substrate, the resistivity is 0.8 omega cm, and the minority carrier lifetime is more than 1ms.
(1) Double-sided texturing, in a groove type machine table, KOH is firstly adopted to be H 2 O 2 Pre-washing for 2min at 75 ℃ with =1:3; then, when the temperature was maintained at 80 ℃ at KOH: additive=8:1Quick texturing is carried out in 7 min; the thinning amount is controlled to be about 0.55 g.
(2) Front side deposition of intrinsic polysilicon and tunnel alumina in tube LPCVD (low pressure vapor chemical deposition), alumina deposition temperature was maintained at 250 ℃, TMA (trimethylaluminum): h 2 O (water vapor) =1: 1, time 14min, thickness 3nm; then intrinsic polysilicon deposition is carried out, the deposition temperature is 600 ℃ and SiH is carried out 4 (silane) flow 500sccm, time 90min, pressure 30mbar, intrinsic polysilicon thickness 500nm; performing thermal oxidation process at 600 ℃ to obtain O 2 (oxygen) 30L for 40min. The oxide layer is a mask layer.
(3) And forming a front surface SE (selective emitter) pattern by using a wax printing spraying mode. Then HF (hydrofluoric acid) HNO is carried out 3 Etching the non-mask region by (nitric acid) =1:3, cleaning with KOH of 5% concentration to remove wax marks, and finally cleaning with HF of 3% concentration to remove oxide layers.
(4) The front P++ layer and the front P+ layer are arranged in a tubular low-pressure diffusion furnace and utilize BCl 3 :O 2 The material is subjected to deposition at a deposition temperature of 860 ℃ for 10min, a pushing temperature of 980 ℃ for 40min, a sheet resistance of the P+ layer is controlled to be 160ohm, and the concentration of the ECV doped surface is 8-9E 18 atom/cm 3 The sheet resistance of the P++ layer is controlled to be 90ohm, and the concentration of the ECV doped surface is 1E 20 atom/cm 3 。
(5) Polysilicon was removed from the back side wrap plating, single sided polysilicon was removed with 5% potassium hydroxide (KOH) and then back side cleaning was performed with 2% HF.
(6) Back side N++ layer, in tube LPCVD (low pressure vapor chemical deposition), silicon oxide deposition temperature is maintained at 600 ℃, O 2 (oxygen) 2L for 20min, thickness 1.5nm; then intrinsic polysilicon deposition is carried out, the deposition temperature is 600 ℃ and SiH is carried out 4 (silane) flow rate 550sccm, time 40min, pressure 29mbar, intrinsic polysilicon thickness 200nm; then high temperature annealing is carried out in a low pressure diffusion furnace, the deposition temperature is maintained at 850 ℃, LN 2 (carrying POCl) 3 N of (2) 2 Flow rate): o (O) 2 Flow = 1:2; low pressure 70mbar, time 30min, high temperature annealing 900 ℃ and time 40min; the sheet resistance is controlled at 60ohm; ECV dopingThe concentration of the impurity surface is 5E 20 atom/cm 3 。
(7) And forming a front surface SE (selective emitter) pattern by using a wax printing mode through the back surface selective pattern. Then, a 5% concentration HF cleaning was performed using a chain cleaner, using an alkali polishing process potassium hydroxide (KOH): polishing additive = 3:1, temperature maintained at 75 ℃, time about 6min, polysilicon removal; and then, 5% KOH cleaning is carried out to remove wax marks, and finally, 3% HF cleaning is carried out to remove the back oxide layer.
(8) Back side n+ layer, silicon oxide deposition temperature is maintained at 600 ℃ in tube type LPCVD (low pressure vapor chemical deposition), O 2 (oxygen) 2L for 20min, thickness 1.5nm; then intrinsic polysilicon deposition is carried out, the deposition temperature is 600 ℃ and SiH is carried out 4 (silane) flow rate 550sccm, time 15min, pressure 29mbar, intrinsic polysilicon thickness 70nm; then high temperature annealing is carried out in a low pressure diffusion furnace, the deposition temperature is maintained at 850 ℃, LN 2 ：O 2 Flow = 1:4, a step of; low pressure 70mbar, time 25min, annealing temperature 850 ℃ and time 20min; the sheet resistance is controlled at 230ohm; ECV doped surface concentration 6E 19 atom/cm 3 。
(9) Removing polysilicon which is coiled and plated on the front surface, removing PSG which is coiled and plated on the front surface by using HF with the concentration of 3 percent, then removing the polysilicon on the front surface by using potassium hydroxide (KOH) which is a groove type alkali polishing process, wherein the polishing additive comprises 2 parts of sodium benzoate, 6 parts of surfactant (sodium hydroxide: polyether modified polysiloxane defoamer=1:2 (mass ratio)) 3 parts of sodium citrate, 1 part of hexadecyl trimethyl amine oxide, 1 part of polyethylene glycol, 3 parts of alkyl polyglucoside, 6 parts of palmitic acid and 78 parts of deionized water according to parts by weight, maintaining the temperature at 75 ℃ for about 3 minutes, and finally cleaning borosilicate glass and phosphosilicate glass on the front surface and the back surface by using HF with the concentration of 5 percent. Then using HCL/O with 0.05% volume concentration 3 The water (with an ozone concentration of 22 ppm) was washed for 2min to obtain a cleaner surface.
(10) Front and back passivation layers, front passivation aluminum oxide (AlOx) is performed by utilizing an Atomic Layer Deposition (ALD) technology, and the thickness is controlled to be 7nm; and then plating silicon nitride on the front and back surfaces, wherein the thickness is controlled at 85nm, and the refractive index is 1.9.
(11) And (3) screen printing, namely printing a main fine grid, wherein the front surface is made of burning-through silver-aluminum paste, and the back surface is made of non-burning-through silver paste. Finally, the finished product is manufactured through the sintering process at 800 ℃.
Comparative example 2
Application number 201911013168.5, the invention name is: the preparation method of the N-type TOPCON solar cell comprises the steps that the back surface of the cell structure is only provided with an n+ layer, and better current collection can not be carried out on the back surface; the front surface is a single-layer p+ layer with a non-poly structure, and the composition is heavier.
(1) Selecting an N-type crystalline silicon substrate 501, and performing rough polishing treatment on the back surface of the N-type crystalline silicon substrate 501 by using an etching cleaner; wherein, the resistivity of the N-type crystalline silicon substrate 501 is 1Ω·cm; the thickness of the N-type crystalline silicon substrate 501 is 80 μm.
(2) Firstly, growing an ultrathin tunneling oxide layer 502 on the back surface of the N-type crystalline silicon substrate 501 treated in the step (1); an intrinsic amorphous silicon layer 503 containing an amorphous phase is then deposited in a low pressure chemical vapor deposition apparatus. Wherein the tunneling oxide layer is made of silicon dioxide, and the preparation method of the silicon dioxide comprises thermal oxidation and HNO 3 Oxidation, O 3 Oxidation, atomic layer deposition, or the like; the thickness of the tunneling oxide layer is 0.5nm; the deposition temperature of the intrinsic amorphous silicon layer is 550 ℃, and the thickness of the intrinsic amorphous silicon layer is 50nm; the intrinsic amorphous silicon layer 503 is then doped by ion implantation of phosphorus atoms and deposited, followed by a mask layer grown over the intrinsic amorphous silicon layer. Wherein, the mask selects SiNx.
(3) And (2) performing texturing treatment on the front surface of the N-type crystalline silicon substrate 501 treated in the step (2), and simultaneously removing the coiling plating.
(4) And (3) putting the N-type crystalline silicon substrate 501 processed in the step (3) into an industrial diffusion furnace to perform boron diffusion on the textured surface to form a p+ doped layer 504 and a borosilicate glass layer on the front surface, and simultaneously activating doping atoms on the back surface at high temperature to completely convert microcrystalline silicon phase into polycrystalline silicon phase to finish crystallization to form the polycrystalline silicon layer, wherein boron source adopts boron tribromide, and the diffusion temperature is 900 ℃ and the time is 60 minutes. The sheet resistance after boron diffusion was 80. OMEGA/sqr.
(5) And (3) removing the borosilicate glass layer on the back mask and the front surface of the N-type crystalline silicon substrate 501 treated in the step (4) by using a cleaning machine.
(6) A passivation and antireflection film 505 is arranged on the front surface of the N-type crystalline silicon substrate 501 processed in the step (5), a passivation film 506 is arranged on the back surface of the N-type crystalline silicon substrate 501, wherein the passivation and antireflection film 505 on the front surface is SiO 2 With Al 2 O 3 Composite film of dielectric film, passivation film 506 of back surface is SiO 2 And a composite dielectric film composed of SiNx dielectric film. The thickness of the front surface passivation antireflection film 505 is 70nm; the thickness of the back surface passivation film 506 is not less than 20nm.
(7) The back main gate and the back sub gate are printed on the back surface of the N-type crystalline silicon substrate 501 using silver paste, and are baked, wherein the line width of the back sub gate 508 is 40um, and the back sub gate is parallel to each other. Front main grids and front auxiliary grids are printed on the front surface of the N-type crystalline silicon substrate 501 by using aluminum-doped silver paste, wherein the front auxiliary grids 507 have a line width of 40um and are parallel to each other.
(8) And (3) conveying the N-type crystalline silicon substrate 501 processed in the step (7) into a belt type sintering furnace for sintering, wherein the sintering peak temperature is 700 ℃, and thus the manufacture of the N-type TOPCon solar cell shown in fig. 5 is completed.
Battery performance test results
The blue membrane structural characterization, i.e. the test before electrode preparation, was performed for the examples and comparative examples, and the performance test results are shown in table 1: the data is cell structure blue patch data, which may reflect that the scheme is practicable.
TABLE 1
From the data, the high-efficiency selective emitter crystalline silicon battery adopting the double-sided power generation provided by the invention omits the technological processes of removing the polysilicon by winding plating, growing a mask layer and diffusing at high temperature. On one hand, a front-back full passivation contact layer is formed; the open circuit voltage can be significantly raised (example 1 raised by 5mV compared to comparative example 1 and 4mV compared to comparative example 2); on the other hand, a selective emitter is formed, and parasitic light absorption is further reduced. The process flow is simplified as a whole, the investment is reduced, the efficiency is improved by more than 0.5%, and the industrialized popularization is facilitated.
It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (9)

1. A preparation method of a double-sided power generation high-efficiency selective emitter crystalline silicon battery is characterized by comprising the following steps of: the battery takes an N/P type monocrystalline silicon wafer as a matrix, and the front side of the battery is sequentially provided with a tunneling layer, a heavily doped p++/n++ nanocrystalline compound layer, a lightly doped p++/n+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and a p++/n++ finger; the back surface is sequentially provided with a tunneling layer, a heavily doped n++/p++ nanocrystalline compound layer, a lightly doped n++/p+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and an n++/p++ finger;
the preparation method of the battery comprises the following operation steps:
(1) Double-sided texturing: taking an N/P monocrystalline silicon wafer as a silicon substrate, firstly carrying out alkali/hydrogen peroxide pre-cleaning, and then carrying out texturing to form an inverted pyramid surface structure;
(2) Front deposition of tunneling layer, p++/n++ doped nanocrystalline compound and mask layer: sequentially growing a tunneling layer, a p++/n++ doped nanocrystalline compound and a mask layer on one side of the monocrystalline silicon wafer, and marking the tunneling layer as the front side, wherein the tunneling layer is one of ultrathin oxide, nitride and alumina;
(3) Backside texture: forming a polished surface/acid etched surface on the back surface by adopting a chain type alkali polishing/acid etching mode, and then cleaning the back surface;
(4) A tunneling layer, an n++/p++ doped nanocrystalline compound and a mask layer are deposited on the back surface: sequentially growing a tunneling layer, an n++/p++ doped nanocrystalline compound and a mask layer on the back surface of the monocrystalline silicon wafer, wherein the tunneling layer is one of ultrathin oxide, nitride and aluminum oxide;
(5) High-temperature annealing: introducing inert gas to perform high-temperature annealing on the monocrystalline silicon piece, and forming full-passivation contact structures on the front surface and the back surface of the monocrystalline silicon piece respectively;
(6) Laser film opening and light expansion region formation: opening the mask layers on the front side and the back side, wherein the opening width is 0.5-1.5 mm; then thinning the doped nanocrystalline compound in the film opening area, forming light expansion areas on the front and back surfaces respectively, and removing borosilicate glass and phosphosilicate glass by adopting an acid washing and efficient cleaning mode to obtain a clean and efficient surface;
(7) And (3) passivation layer generation: passivating aluminum oxide on the front side and the back side of the monocrystalline silicon piece at the same time, wherein the thickness of the aluminum oxide is 2-20 nm; then, simultaneously passivating silicon nitride on the front surface and the back surface of the monocrystalline silicon piece, wherein the thickness of the silicon nitride is 70-90 nm, and the refractive index is 1.8-2.1;
(8) Screen printing: using non-burn-through pure silver paste, and adopting screen printing to form p++ finger and n++ finger; and (5) completing the manufacture of a finished product through a sintering process at 700-850 ℃.
2. The method for preparing the efficient selective emitter crystalline silicon battery with double-sided power generation according to claim 1 is characterized in that: the battery takes an N/P type monocrystalline silicon wafer as a matrix, and the front side of the battery is sequentially provided with a tunneling layer, a heavily doped p++ nanocrystalline compound layer, a lightly doped p+ nanocrystalline compound layer, an aluminum oxide/silicon nitride passivation layer and a p++ finger; the back is provided with a tunneling layer, a heavily doped n++ nanocrystalline compound layer, a lightly doped n+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and an n++ finger in sequence.
3. The method for preparing the efficient selective emitter crystalline silicon battery with double-sided power generation according to claim 1 is characterized in that: the battery takes an N/P type monocrystalline silicon wafer as a matrix, and the front side of the battery is sequentially provided with a tunneling layer, a heavily doped n++ nanocrystalline compound layer, a lightly doped n+ nanocrystalline compound layer, an aluminum oxide/silicon nitride passivation layer and an n++ finger; the back is provided with a tunneling layer, a heavily doped p++ nanocrystalline compound layer, a lightly doped p+ nanocrystalline compound layer, an alumina/silicon nitride passivation layer and a p++ finger in sequence.
4. The method for preparing the efficient selective emitter crystalline silicon battery with double-sided power generation according to claim 1 is characterized in that: in the step (1), the minority carrier lifetime of the N/P type monocrystalline silicon piece is more than 1ms, and the resistivity is 0.5-2.1 Ω cm; in the pre-cleaning process, the volume ratio of alkali to hydrogen peroxide is 1: 2-5, wherein the temperature is 65-85 ℃ and the time is 1.5-4 min; and then placing the substrate into an alkali texturing solution for alkali texturing, wherein the gram weight is 0.4-0.6 g, and the reflectivity is 8-10%.
5. The method for preparing the efficient selective emitter crystalline silicon battery with double-sided power generation according to claim 1 is characterized in that: in the step (2), when the p++ doped nanocrystalline compound is deposited on the front surface, the nanocrystalline compound is doped in situ by adopting a III group element, the thickness of the tunneling layer is 1-2 nm, the thickness of the doped nanocrystalline compound is 100-500 nm, and the thickness of the mask layer is 20-100 nm;
when the n++ doped nanocrystalline compound is deposited on the front surface, the nanocrystalline compound is doped in situ by adopting a V group element, the thickness of the tunneling layer is 1-2 nm, the thickness of the doped nanocrystalline compound is 50-200 nm, and the thickness of the mask layer is 20-50 nm.
6. The method for preparing the efficient selective emitter crystalline silicon battery with double-sided power generation according to claim 1 is characterized in that: in the step (3), 5-6% by mass of hydrochloric acid is used for cleaning.
7. The method for preparing the efficient selective emitter crystalline silicon battery with double-sided power generation according to claim 1 is characterized in that: in the step (4), when the p++ doped nanocrystalline compound is deposited on the front surface, the n++ doped nanocrystalline compound is deposited on the back surface, the nanocrystalline compound is doped in situ by adopting V group elements, the thickness of the tunneling layer is 1-2 nm, the thickness of the doped nanocrystalline compound is 50-200 nm, and the thickness of the mask layer is 20-50 nm;
when the n++ doped nanocrystalline compound is deposited on the front surface, the p++ doped nanocrystalline compound is deposited on the back surface, the nanocrystalline compound is doped in situ by adopting III group elements, the thickness of the tunneling layer is 1-2 nm, the thickness of the doped nanocrystalline compound is 100-500 nm, and the thickness of the mask layer is 20-100 nm.
8. The method for preparing the efficient selective emitter crystalline silicon battery with double-sided power generation according to claim 1 is characterized in that: in the step (5), the high-temperature annealing temperature is 850-900 ℃ and the time is 30-60 min, and full passivation contact structures are formed on the front surface and the back surface of the battery respectively; wherein the surface concentration of the p++ region is 5-10×10 19 atom/cm 3 The junction depth is 0.12-0.52 mu m, and the sheet resistance is 50-150 ohm; the surface concentration of the n++ region is 1 to 10×10 20 atom/cm 3 The junction depth is 0.07-0.22 mu m; the sheet resistance is 35-150 ohm.
9. The method for preparing the efficient selective emitter crystalline silicon battery with double-sided power generation according to claim 1 is characterized in that: in the step (6), a mask layer of an n++ region is opened by utilizing light with the laser power of 25-50W and the wavelength of 532nm, and then the doped nanocrystalline compound of the opened region is thinned in a groove type alkali polishing groove to form an n+ region, wherein the junction depth is 0.03-0.1 mu m; the sheet resistance is 150-250 ohm;
opening a mask layer of the p++ region by using light with the laser power of 25-50W and the wavelength of 532nm, and then thinning the doped nanocrystalline compound of the opening region in a groove type alkali polishing groove to form a p+ region, wherein the junction depth is 0.05-0.15 mu m; the sheet resistance is 200-300 ohm.
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