CN116314471A - Preparation method of rear SE structure - Google Patents
Preparation method of rear SE structure Download PDFInfo
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- CN116314471A CN116314471A CN202310425114.XA CN202310425114A CN116314471A CN 116314471 A CN116314471 A CN 116314471A CN 202310425114 A CN202310425114 A CN 202310425114A CN 116314471 A CN116314471 A CN 116314471A
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- 239000000758 substrate Substances 0.000 claims abstract description 79
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 65
- 239000012535 impurity Substances 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 35
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 18
- 239000001301 oxygen Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 39
- 239000010703 silicon Substances 0.000 claims description 39
- 238000002161 passivation Methods 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 13
- 239000005388 borosilicate glass Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 13
- 230000005641 tunneling Effects 0.000 claims description 11
- 239000003513 alkali Substances 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 8
- 239000005360 phosphosilicate glass Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 125000004437 phosphorous atom Chemical group 0.000 claims description 3
- 238000005253 cladding Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 94
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 8
- 238000001465 metallisation Methods 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
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- 238000010521 absorption reaction Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
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- 239000011574 phosphorus Substances 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
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Abstract
The application discloses a preparation method of a back SE structure, which belongs to the field of solar cells and comprises the following steps: diffusing the polysilicon layer on the back of the substrate to enable impurities in the impurity source to enter the polysilicon layer to form a polysilicon doped layer; introducing oxygen while performing laser irradiation, pushing impurities into the polysilicon doped layer in the region of the printed electrode grid line to form a heavily doped region, and forming an oxide layer on the surface of the heavily doped region, which is away from the substrate, while pushing the impurities; the region of the polysilicon doped layer, which is not doped with the pushing impurity, is a shallow doped region; after an oxide layer is formed in the heavily doped region, removing the polysilicon layer and the impurity source which are plated around on the front surface of the substrate by adopting an etching solution; after removing the wrap-around polysilicon layer and the impurity source, a SE structure is formed on the back side of the substrate. The method and the device can protect the back selectively doped region from being corroded by the corrosive solution when the front polysilicon is removed for plating, so that the efficiency and the yield of the battery are improved.
Description
Technical Field
The application relates to the field of solar cells, in particular to a preparation method of a back surface SE structure.
Background
The core of the tunneling oxide layer passivation contact battery (Tunnel Oxide Passivated Contact, TOPCon) is a passivation structure of ultrathin silicon oxide and doped polysilicon, so that the photons can pass through the tunneling oxide layer selectively, the electrons can be blocked, the separation of the electrons and the photons on the back surface can be realized, and the recombination is greatly reduced; the high doped polysilicon is also beneficial to back metallization, so TOPCon batteries have obvious advantages in the aspect of opening pressure, and are one of the hot researches of the current high-efficiency batteries. However, because the back surface needs to be metallized by a high doped polysilicon matching screen, the parasitic absorption of long waves is serious, and short-circuit current is seriously affected, so that compared with an N-type passivated emitter back surface full-diffusion cell (PERT), the short-circuit current is reduced.
In the current preparation scheme of the selective emitter passivation contact solar cell, the N+ polysilicon doped layer on the back is locally doped to form an N++ heavy doped region; and when electrode metallization is respectively carried out on the front side and the back side of the N-type silicon wafer, the back side electrode is overprinted on the N++ heavily doped region. Although this scheme is simple, after the selective emitter (Selective Emitter, SE) is formed on the back surface, the phosphosilicate glass (Phosphorosilicate glass, PSG) layer is damaged, resulting in the n++ heavily doped region being directly exposed. When the N++ heavy doped region is formed, the front polysilicon is directly removed by alkali solution, so that the back N++ heavy doped region is corroded by the alkali solution to be destroyed, thereby seriously affecting the efficiency and yield of the battery. Therefore, how to improve the efficiency and yield of the battery is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The purpose of the application is to provide a preparation method of a back SE structure, so that the efficiency and the yield of a battery are improved.
In order to achieve the above object, the present application provides a method for preparing a backside SE structure, including:
diffusing the polysilicon layer on the back of the substrate to enable impurities in the impurity source to enter the polysilicon layer to form a polysilicon doping layer;
introducing oxygen while performing laser irradiation, pushing the impurity into the polysilicon doped layer in the area of the printed electrode grid line to form a heavily doped area, and forming an oxide layer on the surface of the heavily doped area, which is away from the substrate, while pushing the impurity; the region of the polysilicon doped layer, which is not pushed by the impurity, is a shallow doped region;
after the oxide layer is formed in the heavily doped region, removing the polysilicon layer and the impurity source which are plated around on the front surface of the substrate by adopting an etching solution;
and forming an SE structure on the back surface of the substrate after removing the polysilicon layer and the impurity source which are plated around.
Optionally, before the diffusing the polysilicon layer on the back surface of the substrate, the method includes:
depositing a tunneling oxide layer on the back surface of the substrate;
and depositing intrinsic amorphous silicon on the surface of the tunneling oxide layer, which is away from the substrate, and crystallizing the intrinsic amorphous silicon to form the polycrystalline silicon layer.
Optionally, before depositing the tunneling oxide layer on the back surface of the substrate, the method further includes:
and polishing the back surface of the substrate.
Optionally, the removing the polysilicon layer and the impurity source of the front side cladding of the substrate with an etching solution includes:
removing the polysilicon layer which is plated around on the front surface of the substrate by adopting an alkali system solution;
and removing the impurity source by adopting an HF/HCL solution.
Optionally, forming an SE structure on a back surface of the substrate, including:
depositing passivation layers and antireflection layers on the front and back surfaces of the substrate;
and after the passivation layer and the anti-reflection layer are deposited, printing an electrode grid line on the heavily doped region so as to enable the electrode grid line to be in contact with the heavily doped region, and forming an SE structure.
Optionally, depositing passivation layers and anti-reflection layers on the front and back surfaces of the substrate, including:
depositing an alumina passivation layer on the front side of the substrate using an ALD apparatus;
after the aluminum oxide passivation layer is deposited, a PEVCD device is used to deposit silicon nitride anti-reflective films on the front and back sides of the substrate.
Optionally, the flow rate of the oxygen is 300sccm-1000sccm, and includes values at both ends.
Optionally, the laser is in a green nanosecond mode; the wavelength of the laser is 450nm-600nm, and the laser comprises values at two ends; the doping frequency of the laser is 100kHz-500kHz, and the doping frequency of the laser comprises values at two ends; the power of the laser is 30% -100% and includes values at both ends.
Optionally, when the substrate is an N-type silicon wafer, the impurity source is phosphosilicate glass; the impurity is a phosphorus atom; when the substrate is a P-type silicon wafer, the impurity source is borosilicate glass; the impurity is a boron atom.
Optionally, when the substrate is an N-type silicon wafer, before diffusing the polysilicon layer on the back surface of the substrate, the method includes:
texturing the front surface of the N-type silicon wafer;
and performing boron diffusion on the front surface of the N-type silicon wafer after texturing to enable boron atoms in borosilicate glass to enter the N-type silicon wafer.
The preparation method of the back SE structure provided by the application comprises the following steps: diffusing the polysilicon layer on the back of the substrate to enable impurities in the impurity source to enter the polysilicon layer to form a polysilicon doping layer; introducing oxygen while performing laser irradiation, pushing the impurity into the polysilicon doped layer in the area of the printed electrode grid line to form a heavily doped area, and forming an oxide layer on the surface of the heavily doped area, which is away from the substrate, while pushing the impurity; the region of the polysilicon doped layer, which is not pushed by the impurity, is a shallow doped region; after the oxide layer is formed in the heavily doped region, removing the polysilicon layer and the impurity source which are plated around on the front surface of the substrate by adopting an etching solution; and forming an SE structure on the back surface of the substrate after removing the polysilicon layer and the impurity source which are plated around.
Obviously, oxygen is introduced while the back surface is selectively doped, laser is irradiated under the atmosphere of the oxygen, an oxide layer is generated on the surface of a laser area as a protective layer while doping is performed by utilizing the instant high temperature of the laser, and the oxide layer can protect the back surface selectively doped area from being corroded by a corrosion solution when the front surface polysilicon is removed for coiling plating, so that the efficiency and the yield of the battery are improved; and because no other working procedure equipment (such as chain type thermal oxygen) is needed to be added for independently manufacturing the oxide layer protection film, the efficiency is improved, and the cost is saved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
Fig. 1 is a flowchart of a method for preparing a back SE structure according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a method for preparing a back SE structure according to an embodiment of the present application;
fig. 3 is a structural diagram of a solar cell according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, fig. 1 is a flowchart of a method for preparing a back side SE structure according to an embodiment of the present application, where the method may include:
s101: and diffusing the polysilicon layer on the back surface of the substrate to enable impurities in the impurity source to enter the polysilicon layer to form a polysilicon doped layer.
The embodiment is not limited to a specific kind of substrate, and for example, the substrate may be an N-type silicon wafer or a P-type silicon wafer. Correspondingly, when the substrate is an N-type silicon wafer, the impurity source is phosphosilicate glass; the impurity is phosphorus atom; when the substrate is a P-type silicon wafer, the impurity source is borosilicate glass; the impurity is boron atoms.
When the substrate is an N-type silicon wafer, the specific temperature at the time of diffusion is not limited, and may be determined according to practical conditions, for example, the temperature at the time of diffusion may be 850 ℃ to 900 ℃ and include values at both ends.
When the substrate is an N-type silicon wafer, before diffusing the polysilicon layer on the back side of the substrate, boron diffusion is required on the front side of the N-type silicon wafer, and the embodiment is not limited to a specific way of performing boron diffusion, so long as boron atoms can be doped into the N-type silicon wafer, for example, texturing can be performed on the front side of the N-type silicon wafer; and performing boron diffusion on the front surface of the N-type silicon wafer after texturing to enable boron atoms in borosilicate glass to enter the N-type silicon wafer. When boron diffusion is performed on the front surface of the N-type silicon wafer, some borosilicate glass diffuses to the back surface of the N-type silicon wafer, and therefore, after boron diffusion is performed on the front surface of the N-type silicon wafer, the borosilicate glass diffused to the back surface of the N-type silicon wafer needs to be removed by etching.
Before diffusing the polysilicon layer on the back surface of the substrate, the polysilicon layer needs to be deposited on the back surface of the substrate, and the embodiment is not limited to a specific manner of depositing the polysilicon layer, so long as the polysilicon layer can be formed on the back surface of the substrate, for example, a tunneling oxide layer can be deposited on the back surface of the substrate; and depositing intrinsic amorphous silicon on the surface of the tunneling oxide layer, which is away from the substrate, and crystallizing the intrinsic amorphous silicon to form a polycrystalline silicon layer. The specific thickness of the tunnel oxide layer is not limited, and may be determined according to practical situations, for example, the thickness of the tunnel oxide layer may be 1.5nm-2.0nm, and includes values of both ends. The embodiment is not limited to a specific thickness of the intrinsic amorphous silicon, and the specific thickness of the intrinsic amorphous silicon may be determined according to practical situations, for example, the thickness of the intrinsic amorphous silicon may be 100nm to 160nm, and include values of both ends.
Further, in order to improve the reflectivity of the back surface of the solar cell, the embodiment may polish the back surface of the substrate before depositing the tunnel oxide layer on the back surface of the substrate. The present embodiment is not limited to the specific manner of polishing, and for example, the back surface of the substrate may be polished with an alkali solution; the back side of the substrate may also be polished with an acid solution.
S102: introducing oxygen while performing laser irradiation, pushing impurities into the polysilicon doped layer in the region of the printed electrode grid line to form a heavily doped region, and forming an oxide layer on the surface of the heavily doped region, which is away from the substrate, while pushing the impurities; the region of the polysilicon doped layer which is not doped with the driving impurity is a shallow doped region.
It should be noted that, in this embodiment, the heavily doped region and the lightly doped region are only used to distinguish between two regions with different doping concentrations, where the doping concentration of the heavily doped region is greater than that of the lightly doped region. The oxide layer is used for blocking the corrosive solution.
The embodiment is not limited to the specific flow rate of the introduced oxygen, and the specific flow rate of the oxygen may be determined according to practical situations, for example, the flow rate of the oxygen may be 300sccm-1000sccm, and the flow rate includes values of two ends. The embodiment is not limited to the specific kind of laser, as long as the impurity can be pushed into the polysilicon doped layer, for example, the laser may be in a green nanosecond mode. The embodiment is not limited to the specific wavelength of the laser, and the specific wavelength of the laser may be determined according to practical situations, for example, the wavelength of the laser may be 450nm to 600nm, and include values of both ends. The specific doping frequency of the laser is not limited to this embodiment, and may be determined according to practical situations, for example, the doping frequency of the laser may be 100kHz-500kHz and include values of both ends. The embodiment is not limited to the specific power of the laser, and the specific power of the laser may be determined according to practical situations, for example, the power of the laser is 30% -100%, and the values of both ends are included.
The specific sheet resistance of the heavily doped region is not limited, and the specific sheet resistance of the heavily doped region may be determined according to a specific doping process, for example, the sheet resistance of the heavily doped region may be 25Ω -55Ω, and includes values of two ends. The specific sheet resistance of the shallow doped region is not limited, and the specific sheet resistance of the formed heavy doped region may be determined according to a specific doping process, for example, the sheet resistance of the shallow doped region may be 70Ω -130Ω, and includes values at both ends.
In the embodiment, the heavy doping is performed in the screen metallization region by selective doping of the laser, so that the overlarge contact resistance of the back electrode caused by low doping concentration of the metallization region is reduced; the shallow doping of the non-metallized region reduces the doping concentration and parasitic absorption, so that the short-circuit current is improved;
s103: and after the oxide layer is formed in the heavily doped region, removing the polysilicon layer and the impurity source which are plated around the front surface of the substrate by adopting an etching solution.
The embodiment is not limited to a specific manner of removing the around-plated polysilicon layer and the impurity source, as long as the around-plated polysilicon layer and the impurity source can be removed, for example, an alkali system solution may be used to remove the front-side around-plated polysilicon layer of the substrate; and removing an impurity source by adopting an HF/HCL solution. The present embodiment is not limited to the specific type of alkali system solution, and for example, naOH/koh+ additive may be used, or other alkali solutions may be used. Wherein HF is hydrofluoric acid; HCL is hydrogen chloride; naOH is sodium hydroxide; KOH is potassium hydroxide.
When the substrate is an N-type silicon wafer, the impurity source is phosphosilicate glass, and besides the polysilicon layer and the impurity source which are plated around the front surface of the substrate are removed by adopting an etching solution, the borosilicate glass is also required to be removed by adopting the etching solution; when the substrate is a P-type silicon wafer, the impurity source is borosilicate glass, and besides the polysilicon layer and the impurity source which are plated around the front surface of the substrate are removed by adopting an etching solution, the borosilicate glass is also required to be removed by adopting the etching solution.
S104: after removing the wrap-around polysilicon layer and the impurity source, a SE structure is formed on the back side of the substrate.
The embodiment is not limited to a specific manner of forming the SE structure on the back surface of the substrate, so long as the SE structure can be formed, for example, a passivation layer and an anti-reflection layer may be deposited on the front surface and the back surface of the substrate; after the passivation layer and the anti-reflection layer are deposited, the electrode grid line is printed on the heavily doped region so that the electrode grid line contacts with the heavily doped region, and a SE structure is formed. It should be noted that, the deposition of the antireflection layer can improve the absorption of sunlight by the battery piece and increase the photo-generated current, thereby improving the conversion efficiency; the passivation layer is deposited to reduce the surface recombination rate of the emitter junction and improve the open-circuit voltage, so that the conversion efficiency is improved.
The embodiment is not limited to a specific manner of depositing the passivation layer and the anti-reflection layer on the front surface and the back surface of the substrate, as long as the passivation layer and the anti-reflection layer can be formed, for example, an ALD apparatus may be used to deposit an alumina passivation layer on the front surface of the substrate; after the aluminum oxide passivation layer is deposited, a PEVCD device is used to deposit silicon nitride anti-reflective films on the front and back sides of the substrate. The embodiment is not limited to a specific thickness of the alumina passivation layer, and the specific thickness of the alumina passivation layer may be determined according to practical situations, for example, the thickness of the alumina passivation layer may be 4nm to 6nm, and includes values of both ends. The specific thickness of the silicon nitride anti-reflection film is not limited, and may be determined according to practical situations, for example, the thickness of the silicon nitride anti-reflection film may be 65nm to 80nm, and includes values of both ends. Wherein the ALD (Atomic Layer Deposition) device is an atomic layer deposition device; PEVCD (Plasma Enhanced Chemical Vapor Deposition) the apparatus is a plasma chemical vapor deposition apparatus.
It should be noted that, in this embodiment, by preparing the selective emitter on the back, on the premise of ensuring passivation effect and high filling factor, the thickness of the polysilicon doped layer is reduced as much as possible, and the overall doping concentration is reduced, so that the short-circuit current can be improved, and the conversion efficiency of the solar cell is further improved.
Based on the embodiment, oxygen is introduced while the back surface is selectively doped, laser is irradiated under the atmosphere of the oxygen, an oxide layer is generated on the surface of a laser area as a protective layer while doping is performed by utilizing the instant high temperature of the laser, and the oxide layer can protect the back surface selectively doped area from being corroded by a corrosion solution when the front surface polysilicon is removed for winding plating, so that the efficiency and the yield of the battery are improved; and because no other working procedure equipment (such as chain type thermal oxygen) is needed to be added for independently manufacturing the oxide layer protection film, the efficiency is improved, and the cost is saved.
The process of preparing the back side SE structure is described below with reference to fig. 2 and 3, and fig. 2 is a schematic flow chart of a method of preparing a back side SE structure according to an embodiment of the present application; fig. 3 is a schematic diagram of a solar cell according to an embodiment of the present application, where the substrate in this embodiment is an N-type silicon wafer, and the process specifically includes:
1. texturing and boron diffusion are carried out on the front surface of the N-type silicon wafer; etching to remove borosilicate glass (Borosilicate glass, BSG) diffused to the back surface of the N-type silicon wafer, and performing alkali polishing on the back surface of the N-type battery;
2. sequentially manufacturing a tunneling oxide layer and intrinsic amorphous silicon on the back surface of the N-type silicon wafer; the thickness of the prepared tunneling oxide layer is 1.5nm-2.0nm, and the thickness of the intrinsic amorphous silicon is 100nm-160nm;
3. crystallizing the intrinsic amorphous silicon, and performing phosphorus diffusion on the back surface of the N-type silicon wafer to form an N+ polysilicon layer (shallow doping); the temperature during phosphorus diffusion is controlled between 850 ℃ and 900 ℃; the sheet resistance of the shallow doped region after phosphorus expansion is 70 omega-130 omega;
4. forming an N++ heavy doping region (heavy doping) by utilizing laser to carry out selective heavy doping, introducing oxygen while carrying out laser irradiation, wherein the oxygen flow is 300sccm-1000sccm, and generating a layer of oxide layer SiO on the surface while carrying out selective doping 2 (silicon dioxide) as a protective layer in the subsequent removal of the front side amorphous silicon. When the laser is doped, the laser is in a green nanosecond mode, the wavelength is 450nm-600nm, the doping frequency is 100kHz-500kHz, and the power is 30% -100%. The sheet resistance of the heavily doped region is 25 omega-55Ω after doping, and the selectively heavily doped region is a back metal electrode overprinting region;
5. removing front polysilicon coiling plating by using an alkali system solution (NaOH/KOH+ additive), and removing BSG on the front side and PSG on the back side of the N-type silicon wafer by using an HF/HCL solution;
6. manufacturing an alumina passivation layer on the front side of the N-type silicon wafer by using ALD equipment, wherein the thickness of the alumina passivation layer is 4-6nm; then PEVCD equipment is used for manufacturing a silicon nitride antireflection film on the two sides of the N-type silicon wafer, and the thickness is 65-80nm;
7. respectively metallizing the front side and the back side of the N-type silicon wafer, wherein a back electrode is overprinted in the selective heavily doped region; the structure of the resulting finished battery sheet is shown in fig. 3.
Referring to table 1, table 1 is a comparison of sheet resistance of the battery prepared in the present application and the battery prepared in the conventional production line. The normal sheet resistance of the back of the battery prepared by the traditional production line is 45 omega-47 omega, the shallow doping sheet resistance of the battery prepared by the application in the non-SE area of the back is higher, the sheet resistance is 92 omega-96 omega, the heavy doping sheet resistance of the SE area is lower, and the sheet resistance is 40 omega-42 omega.
Table 1 comparison of the sheet resistance of the batteries prepared in the present application and the batteries prepared in the conventional production line
Referring to table 2, table 2 compares the performance of the cells prepared herein with those prepared in a conventional production line, where Eta is the conversion efficiency; voc is the open circuit voltage; isc is short circuit current; FF is the fill factor. The efficiency of the battery prepared by the method reaches 25.15%, wherein the Isc is obviously improved, and is 0.133A higher than that of the battery prepared by the traditional production line, because the method is used for carrying out heavy doping in the wire mesh metallization region, the overlarge contact resistance of the back electrode caused by low doping concentration of the metallization region is reduced, the shallow doping of the non-metallization region is reduced, the doping concentration is reduced, and the parasitic absorption is reduced, so that the short-circuit current is improved.
Table 2 comparison of battery performance of the battery prepared in the present application and that prepared in a conventional production line
| Group of | Eta/％ | Voc/mV | Isc/A | FF/％ |
| Traditional production line | 24.94 | 715.91 | 13.613 | 84.4 |
| The application | 25.15 | 715.95 | 13.726 | 84.3 |
| Gap | 0.21 | 0.04 | 0.113 | -0.1 |
The principles and embodiments of the present application are described herein by applying specific examples, and the examples are in progressive relationship, and each example mainly illustrates differences from other examples, where the same similar parts of the examples are mutually referred to. The above description of embodiments is only for aiding in the understanding of the method of the present application and its core ideas. It will be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the principles of the application, which are intended to be covered by the appended claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Claims (10)
1. A method for preparing a backside SE structure, comprising:
diffusing the polysilicon layer on the back of the substrate to enable impurities in the impurity source to enter the polysilicon layer to form a polysilicon doping layer;
introducing oxygen while performing laser irradiation, pushing the impurity into the polysilicon doped layer in the area of the printed electrode grid line to form a heavily doped area, and forming an oxide layer on the surface of the heavily doped area, which is away from the substrate, while pushing the impurity; the region of the polysilicon doped layer, which is not pushed by the impurity, is a shallow doped region;
after the oxide layer is formed in the heavily doped region, removing the polysilicon layer and the impurity source which are plated around on the front surface of the substrate by adopting an etching solution;
and forming an SE structure on the back surface of the substrate after removing the polysilicon layer and the impurity source which are plated around.
2. The method of claim 1, wherein before diffusing the polysilicon layer on the back side of the substrate, the method comprises:
depositing a tunneling oxide layer on the back surface of the substrate;
and depositing intrinsic amorphous silicon on the surface of the tunneling oxide layer, which is away from the substrate, and crystallizing the intrinsic amorphous silicon to form the polycrystalline silicon layer.
3. The method of claim 2, further comprising, prior to depositing the tunnel oxide layer on the back side of the substrate:
and polishing the back surface of the substrate.
4. The method of claim 1, wherein said removing said polysilicon layer and said impurity source of said front side cladding of said substrate with an etching solution comprises:
removing the polysilicon layer which is plated around on the front surface of the substrate by adopting an alkali system solution;
and removing the impurity source by adopting an HF/HCL solution.
5. The method of claim 1, wherein forming the SE structure on the back side of the substrate comprises:
depositing passivation layers and antireflection layers on the front and back surfaces of the substrate;
and after the passivation layer and the anti-reflection layer are deposited, printing an electrode grid line on the heavily doped region so as to enable the electrode grid line to be in contact with the heavily doped region, and forming an SE structure.
6. The method of claim 1, wherein depositing passivation and anti-reflection layers on the front and back sides of the substrate comprises:
depositing an alumina passivation layer on the front side of the substrate using an ALD apparatus;
after the aluminum oxide passivation layer is deposited, a PEVCD device is used to deposit silicon nitride anti-reflective films on the front and back sides of the substrate.
7. The method of claim 1, wherein the oxygen flow is 300sccm-1000sccm and includes values at both ends.
8. The method of fabricating a backside SE structure according to claim 1, wherein the laser is in green nanosecond mode; the wavelength of the laser is 450nm-600nm, and the laser comprises values at two ends; the doping frequency of the laser is 100kHz-500kHz, and the doping frequency of the laser comprises values at two ends; the power of the laser is 30% -100% and includes values at both ends.
9. The method of manufacturing a back side SE structure according to any one of claims 1 to 8, wherein when the substrate is an N-type silicon wafer, the impurity source is phosphosilicate glass; the impurity is a phosphorus atom; when the substrate is a P-type silicon wafer, the impurity source is borosilicate glass; the impurity is a boron atom.
10. The method for preparing a back SE structure according to claim 9, wherein when the substrate is an N-type silicon wafer, before the diffusing the polysilicon layer on the back of the substrate, the method comprises:
texturing the front surface of the N-type silicon wafer;
and performing boron diffusion on the front surface of the N-type silicon wafer after texturing to enable boron atoms in borosilicate glass to enter the N-type silicon wafer.
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