CN117457797A - Preparation method and application of TOPCON battery structure - Google Patents
Preparation method and application of TOPCON battery structure Download PDFInfo
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- CN117457797A CN117457797A CN202311449156.3A CN202311449156A CN117457797A CN 117457797 A CN117457797 A CN 117457797A CN 202311449156 A CN202311449156 A CN 202311449156A CN 117457797 A CN117457797 A CN 117457797A
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- 238000000034 method Methods 0.000 claims abstract description 85
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000002161 passivation Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims description 39
- 230000005641 tunneling Effects 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 21
- 238000009792 diffusion process Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 11
- 229910052755 nonmetal Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 3
- ORUIBWPALBXDOA-UHFFFAOYSA-L magnesium fluoride Chemical compound [F-].[F-].[Mg+2] ORUIBWPALBXDOA-UHFFFAOYSA-L 0.000 claims description 3
- 229910001635 magnesium fluoride Inorganic materials 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052796 boron Inorganic materials 0.000 abstract description 13
- 239000000969 carrier Substances 0.000 abstract description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 41
- 238000010586 diagram Methods 0.000 description 17
- 238000004140 cleaning Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 230000002209 hydrophobic effect Effects 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
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- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000003344 environmental pollutant Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 231100000719 pollutant Toxicity 0.000 description 2
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- 239000004332 silver Substances 0.000 description 2
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 1
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a preparation method and application of a TOPCON battery structure, which utilizes a boron expansion co-pushing process to simultaneously push and form a front emission region n-poly and a back p-poly, thereby reducing one-step high-temperature process and simplifying process flow. And in the subsequent process, a TOPCon structure of a metal contact area and a front emitter of the battery is reserved by utilizing a laser large-area film opening process, so that the passivation performance of the emitter area and the collection efficiency of carriers are improved. The invention optimizes the preparation method of the TOPCON battery structure, simplifies the process flow, greatly shortens the process flow time and reduces the preparation cost of the battery.
Description
Technical Field
The invention relates to the field of solar cells, in particular to a preparation method and application of a TOPCON cell structure.
Background
Since photovoltaic technology became a viable renewable energy source, crystalline silicon (c-Si) solar cells have been dominant in the Photovoltaic (PV) market due to its mature fabrication technology, low fabrication cost, and high market acceptance. In recent years, batteries with a TOPCon battery structure have received attention from market and research institutions by virtue of excellent battery characteristics, low power attenuation, and compatibility with the last-generation mass-production PERC battery production line.
Patent CN114497241a devised a novel all-back junction cell, by reducing carrier recombination in the two-sided contact region and placing the emitter on the back, carrier recombination in the front non-contact region can be reduced, resulting in higher open circuit voltage and conversion efficiency than conventional TOPCon. However, the process method of the related battery structure needs to be subjected to two high-temperature processes (a phosphorus expansion process and a boron expansion process) in the battery preparation process, the process is complex, the process time is long, and the introduction of a mass production process is not facilitated.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a preparation method and application of a TOPCON battery structure.
The first aspect of the invention provides a method for preparing a TOPCON battery structure, which comprises the following steps:
(1) Providing a substrate;
(2) Sequentially depositing a tunneling layer and an i-poly layer on the front surface and the back surface of the substrate;
(3) Depositing a PSG layer on the surface of the front i-poly layer;
(4) Depositing BSG layers on the front side and the back side of the device obtained in the step (3), then performing boron-phosphorus one-step co-diffusion, forming an n-poly layer between the PSG layer on the front side and the tunneling layer, and forming a p-poly layer between the BSG layer on the back side of the device and the tunneling layer;
(5) Performing laser patterning treatment on the front surface of the device obtained in the step (4), reserving a BSG layer and a PSG layer of a front metal contact area, and removing the BSG layer and the PSG layer of a front non-metal contact area;
(6) Texturing the front non-metal contact area of the device obtained in the step (5);
(7) Removing the BSG layer and the PSG layer of the device obtained in the step (6);
(8) Depositing passivation antireflection films on the front and back surfaces of the device obtained in the step (7);
(9) And (3) arranging a front metal electrode and a back metal electrode on the device obtained in the step (8), wherein the front metal electrode is arranged in a metal contact area, and the TOPCO battery structure is obtained.
The method according to the first aspect of the present invention, wherein in step (1), the substrate material is crystalline silicon.
The method according to the first aspect of the present invention, wherein, in step (2), the i-poly layer has a thickness of 50 to 600nm, preferably 300 to 500nm, more preferably 300 to 400nm; and/or
The thickness of the tunneling layer is 0-10 nm, preferably 1-8 nm, more preferably 1-5 nm;
preferably, the method of depositing the i-poly layer is CVD, preferably LPCVD and/or PECVD.
The method according to the first aspect of the present invention, wherein, in the step (3), the method of depositing the PSG layer is APCVD; and/or
In the step (4), the method for depositing the BSG layer is APCVD.
The method according to the first aspect of the present invention, wherein in step (6), the bottom surface of the pile structure of the pyramid is located below the tunneling layer.
The method according to the first aspect of the present invention, wherein in step (8), the material of the passivation anti-reflection film is selected from one or more of the following: silicon oxide, silicon nitride, aluminum oxide, magnesium fluoride; and/or
The passivation anti-reflection film comprises one or more passivation anti-reflection layers.
The method according to the first aspect of the invention, wherein in step (9), the electrode material is selected from Ag and/or Al, preferably Ag.
A second aspect of the invention provides the use of the method of manufacturing a TOPCon cell structure of the first aspect in the manufacture of a solar cell.
A third aspect of the invention provides a TOPCon battery structure prepared according to the method of the first aspect.
A fourth aspect of the invention provides a solar cell comprising the TOPCon cell structure of the third aspect.
The preparation method of the invention can have the following beneficial effects but is not limited to:
the invention utilizes the boron-diffusion co-diffusion (boron-phosphorus one-step co-diffusion) process to simultaneously push and form the front emission region n-poly and the back p-poly, thereby reducing one-step high-temperature process and simplifying process flow. And in the subsequent process, a TOPCon structure of a metal contact area and a front emitter of the battery is reserved by utilizing a laser large-area film opening process, so that the passivation performance of the emitter area and the collection efficiency of carriers are improved. The invention optimizes the preparation method of the TOPCON battery structure, simplifies the process flow, greatly shortens the process flow time and reduces the preparation cost of the battery.
Drawings
Fig. 1 shows a schematic process flow diagram of the fabrication process of the TOPCon battery structure of the present invention.
Fig. 2 shows a schematic structure obtained after polishing the substrate in step 1 of example 1.
FIG. 3 shows a schematic representation of the structure obtained after deposition of i-poly on the substrate surface in step 2 of example 1.
Fig. 4 shows a schematic structure obtained after front and side deposition of PSG in step 3 of example 1.
Fig. 5 shows a schematic structure obtained by cleaning and removing the side PSG in step 4 of example 1.
Fig. 6 shows a schematic diagram of the structure obtained after boron expansion co-pushing in step 5 of example 1.
Fig. 7 shows a schematic diagram of the structure obtained after laser large-area film opening in step 6 of example 1.
Fig. 8 shows a schematic structural diagram obtained after the texturing in step 7 of example 1.
FIG. 9 shows a schematic structure obtained after HF hydrophobic and RCA cleaning in step 8 of example 1.
Fig. 10 shows a schematic structural diagram obtained after the oxidation step in step 9 of example 1.
Fig. 11 shows a schematic structural diagram obtained after the passivation step in step 10 of example 1.
Fig. 12 shows a schematic structural diagram obtained after the metallization step in step 11 of example 1.
Fig. 13 shows the electrochemical test results of the TOPCon battery prepared in test example 1.
Reference numerals illustrate:
1. a substrate; 2. a tunneling layer; 21. a front tunneling layer; 22. a back tunneling layer; 3. an i-poly layer; 4. a PSG layer; 5. a BSG layer; 51. a front side BSG layer; 52. a backside BSG layer; 61. an n-poly layer; 62. a p-poly layer; 71. a front side silicon oxide layer; 72. a back side silicon oxide layer; 81. a front side dielectric layer; 82. a back side dielectric layer; 91. a front metal electrode; 92. and a back metal electrode.
Detailed Description
The present application is further described in detail below by way of the accompanying drawings and examples. The features and advantages of the present application will become more apparent from the description.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Before describing the technical scheme of the present invention, the terms used herein are defined as follows:
the term "TOPCon battery" refers to: tunnel Oxide Passivated Contact Cell the tunnel oxide passivates the contact cell.
The term "i-poly" refers to: intrinsic polysilicon.
The term "CVD" refers to: chemical vapor deposition.
The term "LPCVD" refers to: low pressure chemical vapor deposition.
The term "PECVD" refers to: plasma enhanced chemical vapor deposition.
The term "APCVD" refers to: atmospheric pressure chemical vapor deposition.
The term "PSG" refers to: and (3) phosphosilicate glass.
The term "BSG" refers to: borosilicate glass.
The term "n-poly" refers to: n-type doped polysilicon.
The term "p-poly" refers to: p-type doped polysilicon.
The term "RCA clean" refers to: RCA standard cleaning method.
The invention provides a preparation method of a TOPCON battery structure, which comprises the following steps:
(1) Providing a substrate;
(2) Depositing an i-poly layer on the front side and the back side of the substrate, and forming a tunneling layer between the substrate and the i-poly layer while depositing;
(3) Depositing a PSG layer on the surface of the front i-poly layer;
(4) Depositing BSG layers on the front side and the back side of the device obtained in the step (3), then performing boron-phosphorus one-step co-diffusion, forming an n-poly layer between the PSG layer on the front side and the tunneling layer, and forming a p-poly layer between the BSG layer on the back side of the device and the tunneling layer;
(5) Performing laser patterning treatment on the front surface of the device obtained in the step (4), reserving a BSG layer and a PSG layer of a front metal contact area, and removing the BSG layer and the PSG layer of a front non-metal contact area;
(6) Texturing the front non-metal contact area of the device obtained in the step (5);
(7) Removing the BSG layer and the PSG layer of the device obtained in the step (6);
(8) Depositing passivation antireflection films on the front and back surfaces of the device obtained in the step (7);
(9) And (3) arranging a front metal electrode and a back metal electrode on the device obtained in the step (8), wherein the front metal electrode is arranged in a metal contact area, and the TOPCO battery structure is obtained.
The invention utilizes the boron expansion co-pushing technology to simultaneously push and form the front emission region n-poly and the back p-poly, thereby reducing one-step high-temperature technology and simplifying the technological process. And in the subsequent process, a TOPCon structure of a metal contact area and a front emitter of the battery is reserved by utilizing a laser large-area film opening process, so that the passivation performance of the emitter area and the collection efficiency of carriers are improved.
In the prior art, the preparation process of the TOPCON battery needs to be subjected to two high-temperature processes (a phosphorus expansion process and a boron expansion process), so that the process is complicated, the process time is long, and the introduction of a mass production process is not facilitated. The invention optimizes the preparation method of the TOPCON battery structure, simplifies the process flow, greatly shortens the process flow time for preparing the battery, and reduces the preparation cost of the battery.
According to one embodiment of the invention, in step (1), the substrate material is selected from crystalline silicon.
Before preparation, the substrate can be cleaned, polished and nursed so as to facilitate the subsequent work.
In the step (2), the thickness of the i-poly layer is 50 to 600nm, preferably 300 to 500nm, more preferably 300 to 400nm; and/or
The thickness of the tunneling layer is 0-10 nm, preferably 1-8 nm, more preferably 1-5 nm; preferably, the method of depositing the i-poly layer is CVD, preferably LPCVE or PECVD.
Alternatively, the tunneling layer may have a thickness of 0.1nm,0.5nm,1nm,2nm,3nm,4nm,5nm.
The preparation of the tunneling layer and the i-poly layer is completed in one step in the deposition process of the i-poly, and the preparation process of the tunneling layer and the i-poly process are combined into one, so that the capacity can be greatly improved, the equipment cost is reduced, the process flow time is saved, the ultra-thin tunneling layer can be protected, and on one hand, the tunneling layer can not be further oxidized in the process of leaving a boat, and the tunneling effect is lost; on the other hand, the tunneling layer is not polluted in the air.
According to one embodiment of the present invention, in step (3), the method of depositing the PSG layer is APCVE; and/or
In the step (4), the method for depositing the BSG layer is APCVD.
In one embodiment, the PSG layer has a thickness of 10 to 300nm, preferably 30 to 100nm; and/or
The thickness of the BSG layer is 10 to 300nm, preferably 30 to 100nm.
In one embodiment, the method of depositing the BSG layer is a tube deposition.
The invention uses APCVD method to deposit PSG layer on the surface of i-poly layer, the process is carried out under normal pressure, the reaction speed is fast, the CVD system is simple, and the process flow time is saved. And cleaning to remove PSG on the side surface, and providing conditions for the subsequent BSG deposition and boron diffusion co-promotion.
In the conventional battery preparation process, two different doped regions are required to be subjected to boron diffusion and phosphorus diffusion respectively, and in order to achieve the purpose, two diffusion barrier layer preparation and two wet chemical processes are required to be performed to remove the barrier layer, so that the process flow is complicated. Although some boron-phosphorus doping co-advancing methods have been proposed in the prior art, the preparation process of the battery is still very complicated because of the need of either two-step diffusion of boron, wet spin coating and very strict requirements on diffusion conditions, or the need of providing a barrier layer and further removing the barrier layer after advancing. According to the method, after PSG and BSG are respectively deposited, the front surface of the device is sequentially covered with the PSG and the BSG, so that in the high-temperature diffusion process, the front surface of the device is simultaneously covered with the PSG and the BSG by the i-poly layer of the area only subjected to phosphorus diffusion to form n-poly, and the side surface and the bottom surface of the device are only covered with the i-poly of the area only subjected to boron diffusion to form p-poly, so that the selective doping of the one-step high-temperature process is realized. The invention utilizes the boron expansion co-pushing technology to directly push and form the front emission region n-poly and the back p-poly in one step, thereby greatly simplifying the technological process.
According to one embodiment of the invention, in the step (5), the laser large-area film opening process is utilized, the TOPCon structure of the contact area between the front emitter and the metal of the battery is reserved, and the passivation performance of the emitter area and the collection efficiency of carriers are improved.
According to one embodiment of the present invention, in step (6), the bottom surface of the pile structure of the pile is located below the tunneling layer.
The n-poly layer has strong parasitic absorption effect on light, so that the current density of the cell can be reduced, and the photoelectric conversion efficiency of the solar cell is further affected. According to the invention, the non-metal contact area is textured, so that the manufactured pyramid textured structure is respectively made of the substrate, the tunneling layer and the n-poly layer from bottom to top, and passivation contact of the tunneling layer is formed, thereby reducing parasitic absorption effect of the n-poly layer and improving conversion efficiency of the battery.
According to one embodiment of the invention, step (7) uses an HF hydrophobic treatment to remove the BSG layer and the PSG layer.
According to one embodiment of the invention, after removing the BSG layer and the PSG layer using HF, the device is subjected to RCA standard cleaning.
The invention uses HF hydrophobic stripping treatment to remove the BSG layer and PSG layer on the surface of the device, and then carries out RCA standard cleaning on the device to remove the pollutant on the surface of the device, thereby facilitating the subsequent oxidation passivation.
According to an embodiment of the present invention, in step (8), the material of the passivation anti-reflection film is selected from one or more of the following: silicon oxide, silicon nitride, aluminum oxide, magnesium fluoride; and/or
The passivation anti-reflection film comprises one or more passivation anti-reflection layers.
According to one embodiment of the invention, in step (9), the electrode material is selected from Ag and/or Al, preferably Ag.
The invention also provides an application of the TOPCON battery structure preparation method in the preparation of solar batteries.
The invention provides a TOPCO battery structure, which is prepared according to the method.
The invention also provides a solar cell, which comprises the TOPCO cell structure.
The following examples will further illustrate the invention but should not be construed as limiting the invention. The reagents used in these examples, unless specifically indicated, are all chemically pure reagents and are commercially available.
Example 1
This example is used to illustrate the preparation method of the TOPCON battery structure of the present invention.
Fig. 1 shows a schematic process flow diagram of the fabrication process of the TOPCon battery structure of the present invention, and next, the TOPCon battery structure of the present invention will be described in steps.
Step 1: the substrate 1 is polished, the substrate material being crystalline silicon. Fig. 2 shows a schematic structure obtained after polishing a substrate.
Step 2: a tunneling layer 2 of 0nm to 10nm and an i-poly layer 3 of 50 nm to 600nm are sequentially deposited on the surface of a substrate 1 by a CVD method. Fig. 3 shows a schematic diagram of the resulting structure after deposition of a tunneling layer and an i-poly layer on the substrate surface.
It is noted that here, the tunneling layer may not be provided, but only the i-poly layer, i.e., the tunneling layer 2 may be provided with a thickness of 0.
In one embodiment, tunneling layer 2 of 1-8 nm and i-poly layer 3 of 300-500 nm are sequentially deposited by LPCVD or PECVD. Step 3: and (3) depositing a 10-300 nm PSG layer 4 on the front side and the side of the device obtained in the step (2) by an APCVD method. Fig. 4 shows a schematic diagram of the structure obtained after front and side deposition of PSG.
Step 4: and (3) cleaning and removing the PSG layer on the side surface of the device obtained in the step (3) by using an acid solution, and reserving the PSG layer 4 on the front surface of the device. Fig. 5 shows a schematic structural diagram obtained after washing off the PSG on both sides.
Step 5: and (3) depositing a BSG layer 5 of 10-300 nm on the surface of the device obtained in the step (4) by using an APCVD method, and performing one-step high-temperature diffusion to enable the PSG layer 4 and the BSG layer 5 to respectively dope the i-poly layer 3. Due to the blocking effect of the PSG layer on the BSG layer, only phosphorus diffusion occurs in the i-poly layer between the PSG layer 4 and the tunneling layer 2 on the front side of the device to form an n-poly layer 61, and only boron diffusion occurs in the i-poly layer between the BSG layer 5 and the tunneling layer 2 on the side and bottom of the device to form a p-poly layer 62. Fig. 6 shows a schematic diagram of the structure obtained after boron diffusion co-pushing.
In one embodiment, the method of depositing the BSG layer is a tube deposition.
Step 6: and (5) performing laser film opening on the front surface of the device obtained in the step (5), reserving the BSG layer (5) and the PSG layer (4) of the metal contact area on the front surface of the device, and removing the BSG layer and the PSG layer of the non-metal contact area on the front surface of the device. Fig. 7 shows a schematic diagram of the structure obtained after laser large-area film opening.
Step 7: and (3) texturing the front surface of the device obtained in the step (6), and forming a pyramid suede structure in the non-metal contact area, wherein the bottom surface of the pyramid suede structure is positioned below the tunneling layer. Fig. 8 shows a schematic structural diagram obtained after texturing.
Step 8: performing HF hydrophobic stripping treatment on the device obtained in the step (7), removing the BSG layer 5 and the PSG layer 4 on the surface of the device by using hydrofluoric acid, and performing RCA standard cleaning on the device to remove surface pollutants. Fig. 9 shows a schematic structure obtained after HF hydrophobic stripping treatment and RCA cleaning.
Step 9: the surface oxide deposition of the device obtained in step 8 comprises a front side silicon oxide layer 71 and a back side silicon oxide layer 72. Fig. 10 shows a schematic structural diagram obtained after the oxidation step.
Step 10: and (3) passivating and depositing dielectric layers on the surface of the device obtained in the step 9, wherein the dielectric layers comprise a front surface dielectric layer 81 and a back surface dielectric layer 82. Fig. 11 shows a schematic structural diagram obtained after the passivation step.
Step 11: and (3) arranging a front metal electrode 91 and a back metal electrode 92 on the device obtained in the step (10), wherein the front metal electrode 91 is arranged in a metal contact area, and the metal electrode is preferably a silver electrode, so that the TOPCO battery structure is obtained. Fig. 12 shows a schematic structural diagram obtained after the metallization step.
Test example 1
This test example is used to illustrate the preparation method and effect of the TOPCON battery structure of the present invention.
TOPCon cell structures were prepared according to the method of example 1, by sequentially depositing a tunneling layer 2 of 1-5 nm and an i-poly layer 3 of 300-400 nm on a crystalline silicon substrate by LPCVD or PECVD, and then depositing a PSG layer 4 of 30-100 nm on the i-poly layer surfaces on the front and side by APCVD. And depositing a BSG layer of 30-100 nm on the front and back of the device, and then performing one-step high-temperature boron-phosphorus diffusion. After boron and phosphorus are pushed together, an n-poly layer with the thickness of 30-100 nm is formed between the PSG layer on the front side and the tunneling layer, and a p-poly layer with the thickness of 30-100 nm is formed between the BSG layer on the back side of the device and the tunneling layer. And (3) performing laser film opening on the front surface of the device, removing the BSG layer and the PSG layer of the non-metal contact area, and texturing. Performing HF hydrophobic stripping treatment on the device, removing the BSG layer and the PSG layer on the surface of the device, and depositing passivation antireflection films on the front and back surfaces of the device. And arranging front and back silver electrodes in the metal contact area to obtain the TOPCO battery structure.
Battery performance tests were performed on the TOPCon battery structure obtained above by the IEC standard method, and the test results are shown in fig. 13.
As can be seen from FIG. 13, TOPCon cells prepared in this test example were prepared at 226.62cm 2 At the test area of (1) its short-circuit current I sc 9500mA, open circuit voltage V oc 723.6mV, fill factor FF 83.16% and maximum operating power P mpp The cell efficiency η was 25.23% at 5717 mW.
From the above results, it can be seen that the TOPCon battery structure prepared by the method of the present invention improves passivation performance of the emitter region and collection efficiency of carriers, and obtains higher open circuit voltage and conversion efficiency than conventional TOPCon. Meanwhile, the method reduces one-step high-temperature process, simplifies the process flow, greatly shortens the process flow time, facilitates the introduction of mass production process, reduces the preparation cost of the battery and has good application prospect.
The present application has been described in connection with the preferred embodiments, but these embodiments are merely exemplary and serve only as illustrations. On the basis of this, many alternatives and improvements can be made to the present application, which fall within the scope of protection of the present application.
Claims (10)
1. A method for preparing a TOPCon battery structure, the method comprising the steps of:
(1) Providing a substrate;
(2) Sequentially depositing a tunneling layer and an i-poly layer on the front surface and the back surface of the substrate;
(3) Depositing a PSG layer on the surface of the front i-poly layer;
(4) Depositing BSG layers on the front side and the back side of the device obtained in the step (3), then performing boron-phosphorus one-step co-diffusion, forming an n-poly layer between the PSG layer on the front side and the tunneling layer, and forming a p-poly layer between the BSG layer on the back side of the device and the tunneling layer;
(5) Performing laser patterning treatment on the front surface of the device obtained in the step (4), reserving a BSG layer and a PSG layer of a front metal contact area, and removing the BSG layer and the PSG layer of a front non-metal contact area;
(6) Texturing the front non-metal contact area of the device obtained in the step (5);
(7) Removing the BSG layer and the PSG layer of the device obtained in the step (6);
(8) Depositing passivation antireflection films on the front and back surfaces of the device obtained in the step (7);
(9) And (3) arranging a front metal electrode and a back metal electrode on the device obtained in the step (8), wherein the front metal electrode is arranged in a metal contact area, and the TOPCO battery structure is obtained.
2. The method of claim 1, wherein in step (1), the substrate material is crystalline silicon.
3. The method according to claim 1 or 2, wherein in step (2) the i-poly layer has a thickness of 50-600 nm, preferably 300-500 nm, more preferably 300-400 nm; and/or
The thickness of the tunneling layer is 0-10 nm, preferably 1-8 nm, more preferably 1-5 nm;
preferably, the method of depositing the i-poly layer is CVD, preferably LPCVD and/or PECVD.
4. A method according to any one of claims 1 to 3, wherein in step (3) the method of depositing the PSG layer is APCVD; and/or
In the step (4), the method for depositing the BSG layer is APCVD.
5. The method of any one of claims 1 to 4, wherein in step (6), the bottom surface of the resulting pyramidal pile structure is located below the tunneling layer.
6. The method according to any one of claims 1 to 5, wherein in step (8), the material of the passivation anti-reflection film is selected from one or more of the following: silicon oxide, silicon nitride, aluminum oxide, magnesium fluoride; and/or
The passivation anti-reflection film comprises one or more passivation anti-reflection layers.
7. A method according to any one of claims 1 to 6, wherein in step (9) the electrode material is selected from Ag and/or Al, preferably Ag.
8. Use of the method of manufacturing a TOPCon cell structure of any one of claims 1 to 7 for manufacturing a solar cell.
9. A TOPCon battery structure, characterized in that it is prepared according to the method of any one of claims 1 to 7.
10. A solar cell characterized in that it comprises a TOPCon cell structure according to claim 9.
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| CN117673208B (en) * | 2024-02-01 | 2024-05-07 | 通威太阳能(眉山)有限公司 | Preparation method of solar cell, solar cell and photovoltaic module |
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