NL2023003B1 - Method for preparing full back-contact electrode cell with efficient light trapping and selective doping - Google Patents

Abstract

The present invention relates to the technical field of solar cell manufacturing, and more particularly to a method for preparing a full back-contact electrode cell with 5 efficient light trapping and selective doping. A micro-nano structure is adopted in combination with the atomic layer deposition technique to prepare an ultra-thin silicon oxide passivation film to reduce the light reflection of the front surface and the parasitic light absorption of the passivation film while ensuring passivation of the front surface. To solve the problem of large recombination in the metal region 10 on the back face, selective doping is adopted. A picosecond laser is utilized to ensure heavy doping in the n+ skin layer on the phosphorus doped layer, and the depth of the heavily doped layer is strictly controlled. In this way, not only good ohmic contact is ensured between the phosphorus doped layer and the metal contact region, but also severe carrier recombination due to heavy doping is 15 avoided. By means of passivation of the ultra-thin silicon oxide, the subsequent low-temperature annealing under hydrogen atmosphere further provides bulk passivation for the crystalline silicon. An Al metal electrode is prepared through thermal evaporation, and Al penetrates the silicon oxide to make good ohmic contact with the p+ and n++ regions under laser irradiation. 20

Description

METHOD FOR PREPARIING FULL BACK-CONTACT ELECTRODE CELL WITH EFFICIENT LIGHT TRAPPING AND SELECTIVE DOPING

FIELD OF THE PRESENT INVENTION

The present invention relates to the technical field of solar cell manufacturing, and more particularly to a method for preparing a full back-contact electrode cell with efficient light trapping and selective doping.

DESCRIPTION OF THE RELATED ART

Solar power generation technology is an important field in the development of new energy. It is an ultimate goal of advancement in the solar ceiling technology to increase the output power per unit area or solar cells. In interdigitated back-contact (IBC) solar cells, positive and negative metal electrodes are arranged in an interdigitated pattern on the non-light receiving surface of the cell. Absence of a metal electrode on the light receiving surface of a cell can eliminate the optical loss arisen from light shading by the metal electrode and increase the short circuit current. All the electrodes are distributed in an interdigitated pattern on the back face of the cell, and the large metallization area increases the fill factor of the cell.

In this way, solar cell conversion efficiency can be improved.

For crystalline silicon solar cells, the optical properties and recombination of the front surface are critical. For IBC high-efficiency cells, a better optical anti-reflective design is especially important. Electrically, the performance of IBC cells is influenced by the front surface to a greater extent compared to conventional cells, because most of the photogenerated carriers are generated on the incident surface, and these carriers need to flow from the front surface to the back face of the cell and finally the contact electrodes. Therefore, better surface passivation is needed for reducing the recombination of carriers. The light trapping structure in existing IBC cells mainly uses a pyramidal suede to improve the tight absorption and uses a SiNx laminated anti-reflective passivation film. The optical losses in such a structure include front surface reflection, anti-reflective film parasitic absorption, imperfect long-wavelength light trapping, and free carrier absorption and the like.

In addition, since there is no shading by metal grid lines on the front surface of the IBC cell, the current density is large. The coverage area of the p-region and n-region contact electrodes arranged in an interdigitated pattern on the back face of the cell is up to almost 1/2 of the area of the back surface. Recombination in the metal contact areas is generally significant.

SUMMARY OF THE PRESENT INVENTION

In order to overcome the problems of optical losses and electric losses in the existing IBC cell technology, the present invention provides a method for preparing a full back-contact electrode cell with efficient light trapping and selective doping, including steps or: (A) polishing an n-type monocrystalline silicon wafer having a resistivity of 1-7 Ω cm to remove surface damage and cleaning the silicon wafer; (B) performing boron doping on the surface of the polished and cleaned monocrystalline silicon wafer with a BBr3 source, form a p-type region, forming a pn junction with the n-type silicon substrate, pre-deposition of the boron source is performed at 750-850 ° C for 10-30 minutes at an N2 flow rate or 10-15 slm, an 02 flow rate or 1000-2000 seem, and a BBr3 flow rate or 50-300 seem, and a high -temperature drive-in is performed at a temperature of 900-1050 ° C for 10-30 minutes;

The following reaction is carried out firstly: 4BBr3 + 3O2 ^ 2B2O3 + 63Br2j, and the resulting B2O3 is deposited on the surface of the silicon wafer. Then B2O3 is reacted with Si to produce SiO2 and boron atoms: 2B2O3 + 3Si »3SiO2 + 4B |, boron atoms on the surface of the silicon wafer during the high temperature drive-in to form a p + region through doping. Meanwhile, a layer of SiO2 containing boron element, that is, borosilicate glass (BSG), is formed over the surface of the silicon wafer. (C) removing the BSG and the p-type layer from the surface of the region to be phosphorus doped in the back face of the monocrystalline silicon wafer after boron doping by using a laser, and removing damage caused by laser irradiation with lye and deionized water; (D) performing phosphorus doping on the monocrystalline silicon wafer after laser irradiation in step (3) with POCI3 to form an n + region which forms a parallel interdigitated structure with the p + region, the cell can be configured to a full back-contact electrode structure after the electrodes are prepared, the predeposition of the phosphorus source is performed at 700-800 ° C for 30-60 minutes at an N2 flow or 10-15 slm, an 02 flow or 1000-2000 seem, and a POCI3 flow rate or 300-500 seem, and a high-temperature drive-in is performed at 800-950 ° C for 5-20 min. An n + region is formed, meanwhile, a layer or SiO2 containing phosphorus element, that is, phosphosilicate glass ( PSG), is formed over the surface of the silicon wafer;

Since boron and phosphorus atoms are different in sizes and diffusion rates, a desired doping profile cannot be achieved for boron and phosphorus doping at the same time, if boron and phosphorus sources are deposited firstly and boron and phosphorus doping are formed simultaneously by one-step high temperature drive-in. The present invention adopts a doping method in which boron doping is performed before phosphorus doping. In this way, boron and phosphorus doping can be controlled independently in terms of the concentration and depth, allowing allowing better controllability. (E) scanning the surface of the phosphosilicate glass covering the n + region by using a picosecond laser to form an ultra-thin n ++ layer or a depth of 20-50 nm over the n + region, the picosecond laser has a wavelength or 800 nm , a power density or 1-15 W / cm 2, a pulse interval or 7-10 ps, and a scanning rate of 6-10 m / s; Severe carrier recombination occurs due to the high doping concentration and high defect density in the heavily doped region. However, heavy doping is necessary in order to achieve good ohmic contact with the metal electrodes. Therefore, the thickness of the heavily doped layer should be reduced as much as possible. The method of the present invention utilizes a picosecond laser to scan the heavily doped region to form an ultra-thin n ++ layer which has a depth controlled axis 20-50 nm, this can ensure good ohmic contact between the surface and the metal without significantly increasing carrier recombination inside the crystalline silicon; (F) placing the silicon wafer from step (5) on a single-sided wet etching machine with the front face facing downward to remove the PSG and BSG from the front face, where the etching solution is an aqueous HF solution, and the volume ratio of HFto H 2 O is 1: 6; (G) treating the front face of the silicon wafer obtained in step (6) with a low concentration (1 wt%) NaOH solution in ethanol at a temperature of 80 ± 5 ° C for 20 minutes to prepare a pyramid structure having a size or 3-6 pm; pickling the silicon wafer with a 10 wt% aqueous hydrochloric acid solution for 10 min; and then rinsing it with an 8 wt% aqueous HF solution; and preparing nano-pits or 100-300 nm on the pyramid micro-structure using a mixture of AgNO3 and HF (containing 5 mol L-1 or HF and 0.02 mol L-1 or AgNO3) to form a micro-nano light trapping structure ; This micro-nano composite structure can significantly improve the light absorption compared to the micro-structure and allow easier surface passivation compared to the nano-structure. Therefore, the micro-nano structure has the advantages of both. The mixture of AgNO3 and HF is used such that a template is not necessary during preparation of the micro-nano tight trapping structure. The mixture of AgNO3 and HF allows Ag nanoparticles to be formed autonomously on the surface of the silicon wafer. Due to the catalytic effect of the Ag nanoparticles, the silicon under the Ag nanoparticles can be etched at a greater rate to form the nano-pits. (H) performing phosphorus doping on the front face with POCI3 to form an n + layer, ie, front surface field (FSF) passivation, the pre-deposition or the phosphorus source is performed at 700-800 ° C for 10-30 min at an N2 flow rate or 10-15 slm, an 02 flow rate or 1000-2000 seem, and a POCI3 flow rate or 300-500 seem, the high-temperature drive-in is performed at 800-950 ° C for 5- 20 min. An n + region is formed, meanwhile, a layer of SiO2 containing phosphorus element, that is, phosphosilicate glass (PSG), is formed over the surface of the silicon wafer; (I) removing all PSG and BSG from the front and back faces of the silicon wafer using an aqueous HF solution, the volume ratio or HF to H2O is 1: 6; (J) preparing an ultra-thin silicon oxide layer with a depth of 2 to 10 nm simultaneously on the front and back faces by atomic layer deposition (ALD), Trimethylsilane has been introduced to the deposition chamber for 10-20 s, and then N2 is introduced for purging for 10-30 s. Then ozone 03 is introduced into the chamber for 10-20 s, and then N2 is introduced for purging for 10-30 s, and the deposition temperature is 300-400 ° C, with a cycle being completed. The film thickness created from one cycle is around 0.1 nm. This cycle is repeated 100-300 times;

The silicon oxide film prepared by the ALD method of the present invention is advantageous in that, a desirable surface passivation effect can be achieved with a dense and thin film. The narrower the thickness is, the lower the cost is. Meanwhile, the ALD process features a low temperature, and the hydrogen atoms in the silicon bulk will not overflow under subsequent low temperature annealing to cause failure or bulk passivation. (K) annealing the entire silicon wafer under hydrogen atmosphere at a low temperature of 300-450 ° C for 20-30 minutes, hydrogen atoms diffusing through the ultra-thin silicon oxide layer for bulk passivation of the crystalline silicon; (L) thermally evaporating metal aluminum on the entire back face to protect the ultra-thin silicon oxide passivation layer and reflect long waves that are not absorbed by the crystalline silicon, further improving the light utilization efficiency; (M) scanning the aluminum layer above the n ++ and p + regions on the back face using a picosecond laser, such that the aluminum atoms penetrate the silicon oxide layer under irradiation or the laser to reach the positions of n ++ and p + to achieve electrical contact, if by means of picosecond laser scanning, Al can pass through the silicon oxide layer to reach the electrodes since the silicon oxide layer is ultra-thin; (N) splitting electrodes in the p and n region through laser grooving.

Due to the micro-structure such as the pyramids, the light trapping effect is not ideal, and a passivation anti-reflective film needs to be further prepared to reduce the light reflection of the front surface. However, the anti-reflective film needs a certain thickness to provide anti-reflection. The thicker the anti-reflective film is, the stronger its light absorption is, however, the light absorption from the anti-reflective film cannot produce photo-generated carriers. For power generation of crystal silicon cells, the light absorption or the crystalline silicon needs to be maximized. To this end, the present invention uses a micro-nano structure combined with the atomic layer deposition (ALD) technique to prepare an ultra-thin silicon oxide passivation film to reduce the light reflection of the front surface and the parasitic light absorption of the passivation film while ensuring the passivation of the front surface.

To solve the problem of large recombination in the metal region on the back face, selective doping has been adopted. Specifically, the characteristic of a short pulse duration or the picosecond laser is utilized to ensure heavy doping in the skin + layer on the phosphorus doped layer, that is, the depth of the heavily doped layer is strictly controlled. In this way, not only good ohmic contact is ensured between the phosphorus doped layer and the metal contact region, but also severe carrier recombination due to heavy doping is avoided. Low-temperature annealing is performed under hydrogen atmosphere to provide bulk passivation for the crystalline silicon.

Beneficial effects:

The present invention takes advantage of the superior matching between silicon oxide and silicon and the principle of deposition specific to the atom layer deposition technique (atom adsorption, denseness, and conformity) to deposit a dense ultra-thin silicon oxide passivation film on the micro- nano light trapping structure. A superior light trapping structure of the micro-nano structure is ensured while surface passivation or the micro-nano structure is ensured, not reducing parasitic light absorption or the passivation layer. An ultra-thin n ++ region is formed on the n-region doping layer using the picosecond laser. By means of low-temperature annealing under the hydrogen atmosphere, hydrogen atoms diffuse into the bulk for bulk passivation. An aluminum layer is deposited over the ultra-thin silicon oxide layer on the back face. Upon scanning by the picosecond laser, the aluminum penetrates through the ultra-thin silicon oxide layer and diffuses to the n ++ and p + regions to achieve effective contact. Such a dense and uitra-thin silicon oxide layer on the back face can desirably passivate the back surface. The silicon oxide film prepared by the ALD method is compact and can achieve a desirable surface passivation effect with a small thickness. The narrower the thickness is, the lower the cost will be. Meanwhile, the ALD process is performed at a low temperature, and the hydrogen atoms in the silicon bulk will not overflow under subsequent low temperature annealing and not cause failure or bulk passivation.

LETTER DESCRIPTION OF THE DRAWINGS FIG.1 illustrates a flow chart or a method for preparing an IBC cell according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Example 1 (1) An n-type monocrystalline silicon wafer having a resistivity of 2.5 Qcm was polished with a high concentration (20%) NaOH etching solution at a temperature of 90 ° C for 1 minute, and then was cleaned with a mixture or HF and HCl for 2 min. (2) Boron doping was performed using a BBr3 source. The pre-deposition parameters included: 800 ° C, 20 min, an N2 flow rate or 13 slm, an 02 flow rate or 1500 seem, and a BBr3 flow rate or 150 seem. A p + layer was formed over the entire surface of the silicon wafer, and meanwhile, a medium layer or borosilicate glass (BSG) was formed over the surface of the silicon wafer. The high-temperature drive-in was performed at a temperature of 1000 ° C for 15 minutes. (3) The BSG and p-type layer were removed from the surface of the regions to be phosphorus doped on the back face using a picosecond laser, and the back face was cleaned with deionized water to remove some floating dusts resulting from the laser irradiation. (4) Phosphorus doping was performed with POCI3,: the pre-deposition was performed at 700 ° C for 40 minutes, at an N2 flow rate of 15 slm, an 02 flow of 1800 seem, and a POCI3 flow rate of 400 seem. Then the drive-in was performed at a temperature of 850 ° C for 10 minutes. An n + region was formed, and meanwhile a medium layer of phosphosilicate glass (PSG) was formed over the surface. (5) The n + region was scanned by a picosecond laser to form an ultra-thin n ++ layer with a depth of 40 nm. The picosecond laser had a wavelength or 800 nm, a power density of 5 W / cm 2, a pulse interval of 7 ps, and a scanning rate of 10 m / s. (6) The silicon wafer was placed on a single-sided wet-etching machine, and the PSG and BSG were removed from the front face with an aqueous HF solution, and the volume ratio of HF to H2O was 1: 6. (7) The front face was treated with a low concentration (1 wt%) NaOH solution in ethanol at a temperature of 85 ± 5 ° C for 20 minutes to prepare a pyramid structure or a size of 3-6 pm. Thereafter, it was pickled with a 10 wt% aqueous hydrochloric acid solution for 10 min, and then rinsed with an 8 wt% aqueous HF solution. Subsequently, the silicon wafer with a pyramid microstructure on the surface was etched in an aqueous HF / AgNO3 solution (containing 5 moles of L-1 or HF and 0.02 moles of L-1 or AgNO3) for 10 minutes to prepare nano pits or 100-300 nm. (8) Phosphorus doping was performed on the front face with POCI3 to form an n + layer, ie, front surface field (FSF) passivation, meaning the pre-deposition was performed at 700 ° C for 20 minutes at an N2 flow rate of 15 slm, an 02 flow rate of 1800 seem, and a POCI3 flow rate of 400 seem. Then drive-in was performed at a temperature of 850 ° C for 10 minutes. An n + region was formed, and meanwhile a medium layer of phosphosilicate glass (PSG) was formed over the surface. (9) All the PSG and BSG were removed from the front and back faces of the wafer using an aqueous HF solution, the volume ratio or HF to H2O was 1: 6. (10) The entire silicon wafer was annealed for 20 minutes at a low temperature or 300 ° C under the hydrogen atmosphere. Hydrogen atoms diffused through the ultra-thin silicon oxide layer for bulk passivation or the crystalline silicon. (11) An ultra-thin silicon oxide layer was prepared simultaneously on the front and back faces by atomic layer deposition (ALD). Specifically, trimethylsilane was introduced into the deposition chamber for 10s, and then N2 was introduced for purging for 10s. Then ozone 03 was introduced into the chamber for 10s, and then N2 was introduced for purging for 10s, the deposition temperature was 300-400 ° C, according to a cycle was completed. This cycle was repeated 150 times. (12) A layer of metal aluminum with a depth of 100 nm was thermally evaporated on the entire back face to protect the ultra-thin silicon oxide passivation layer and reflect long waves that were not absorbed by the crystalline silicon, further improving the light utilization efficiency. (13) The ultra-thin silicon oxide layer above the n ++ and p + regions on the back face was scanned using a picosecond laser. The aluminum atoms diffused under irradiation or the laser to reach the positions of n-n- and p + to achieve electrical contact. (14) Electrodes were split in the p and n region through laser grooving.

Example 2

The method of preparation comprises the following steps.

Step (2), boron doping was performed with a BBr3 source. The pre-deposition parameters included: 750 ° C, 25 min, an N2 flow rate or 13 slm, an 02 flow rate or 1500 seem, and a BBr3 flow rate or 150 seem. Then high temperature drive-in was performed at a temperature of 1000 ° C for 15 minutes.

Step (4), phosphorus doping was performed with POOI3, pre-deposition was performed at 800 ° C for 40 minutes at an N2 flow rate of 15 slm, an 02 flow rate of 1800 seem, and a POCI3 flow rate of 400 seem. Then the drive-in was performed at a temperature of 950Ό for 10 min.

Other details were the same as in Example 1.

Example 3

The method of preparation comprises the following step.

Step (11), an ultra-thin silicon oxide layer was prepared simultaneously on the front and back faces by atomic layer deposition (ALD). Specifically, trimethylsilane was introduced into the deposition chamber for 10s, and then N2 was introduced for purging for 10s. Thereafter, ozone 03 was introduced into the chamber for 10 s, and then N2 was introduced for 10 s for purging, the deposition temperature was 300 ° C, the cycle was completed. This cycle was repeated 300 times.

Other details were the same as in Example 1.

Example 4

The method of preparation comprises the following step.

Step (5), the n + region was scanned by a picosecond laser to form an ultra-thin n ++ layer with a depth of 40 nm. The picosecond laser had a wavelength of 800 nm, a power density of 10 W / cm 2, a pulse interval of 10 ps, and a scanning rate of 10 m / s.

Other details were the same as in Example 1.

The performance data or electrodes according to various examples of the present invention is shown in Table 1.

Table 1

Open-circuit voltage Voc (mV) Short-circuit current Jsc (mA / cm2) Fill factor FF (%) Efficiency Eft (%)

Example 1 695.3 42.85 81.56 24.32

Example 2 688.5 42.58 81.25 23.82

Example 3 682.4 42.56 81.12 23.55

Example 4 682.1 42.42 81.21 22.47

Claims (6)

Conclusions A method for manufacturing a full rear-contact electrode cell with efficient light collection and selective doping, comprising the steps of: (A) polishing an n-type monocrystalline silicon wafer with a specific resistance of 1-7 Ocm, to remove surface damage, and to clean the silicon wafer; (B) performing a boron doping on the surface of the monocrystalline silicon wafer with a source of BBr3, comprising performing a pre-desposition of the well and a high temperature insertion, wherein during the high temperature insertion, boron atoms on the surface of the silicon wafer diffusing into the silicon wafer to form a p + region by doping, and a layer of SiO2-containing drilling element is formed on the surface of the silicon wafer, which is borosilicate glass (BSG); (C) removing the BSF and the p-type layer from the surface of a region to be doped with phosphorus on the back surface of the monocrystalline silicon wafer after doping with boron using a laser, and removing damage caused by laser radiation with lye and deionized water; (D) performing a phosphorus dorination on the monocrystalline silicon wafer after laser irradiation in step (C) with POCl 3, including performing a pre-deposition of a phosphorus source at 700-800 ° C for 30-60 minutes, a high temperature introduction at 800-950 ° C for 5-20 minutes to form an n + region, and forming a layer of SiO 2 containing a phosphor element, which is a phosphosilicate glass (FSG), on the surface of the silicon wafer; (E) scanning the surface of the phosphosilicate glass covering the n + region, using a picosecond laser to form an ultra-thin, heavily doped n ++ layer over the n + region in the bulk silicon; (F) placing the silicon water of step (E) on a single-sided wet-etching machine with the front side facing down to remove the FSG and BSG from the front; (G) manufacturing a micro-nano light-receiving structure on the face of the silicon wafer from step (F) by chemical wet etching, and by catalyzed etching with metal nanoparticles; (H) performing a doping of phosphorus on the silicon wafer from step (G) with POCl 3 to form an n + layer on the front, i.e. a front field (VZV) passivation, comprising: performing a pre-deposition of the phosphorus source at 700-800 ° C for 10-30 minutes, a high temperature insertion at 800-950 ° C for 5-20 minutes to an n + region forming, and forming a layer of SIO 2 containing a phosphor element, which is a phosphosilicate glass (FSG), over the surface of the silicon wafer; (I) removing all FSG and BSG from the front and back sides of the silicon wafer from step (H); (J) simultaneously fabricating an ultra-thin silicon oxide layer on the front and back sides by atomic layer deposition, to achieve a passivation of the surface on the front and back sides, wherein the silicon oxide layer has a depth of 2 to 10 nm ; (K) annealing the entire silicon wafer under an atmosphere of hydrogen at a temperature of 300-450 ° C for 20-30 minutes, wherein hydrogen atoms diffuse through the ultra-thin silicon oxide layer to passivate the crystalline silicon; (L) thermally vaporizing the metal aluminum on the entire backside to protect the ultra-thin silica passivation layer and to reflect long waves that are not absorbed by the crystalline silicon, thereby further improving the efficiency of light use; (M) scanning the aluminum layer over the n ++ and p + regions on the backside with a picosecond laser, so that aluminum atoms penetrate the silicon oxide layer under laser radiation to reach the positions n ++ and p + to effect electrical contact; and (N) splitting the electrodes in the p and n regions by laser grooves. The method of claim 1, wherein in step (B), the pre-deposition of the well is performed at a temperature of 750-800 ° C for 10-30 minutes, at an N 2 flow rate of 10-15 sim, flow rate of 1000-2000 sccm, and a BBr3 flow rate of 50-300 sccm, and the high temperature insertion is performed at a temperature of 900-1050 ° C for 10-30 minutes. The method of claim 1, wherein in step (D), the phosphor source preposition is performed at an N2 stream of 10-15 sim, an O2 stream of 1000-2000 sccm, and a POCI3 flow rate of 300-500 sccm. The method of claim 1, wherein in step (E), the picosecond laser has a wavelength of 800 nm, a specific power of 1-15 W / cm 2, a pulse interval of 7-10 / sec, and a scanning speed of 6- 10 m / s, and the n ++ layer has a depth of 20-50 nm. The method of claim 1, wherein in step (H), the phosphor source preposition is performed at an N2 flow rate of 10-15 sim, an O2 flow rate of 1000-2000 sccm, and a POCI3 flow rate of 300-500 sccm. A full rear-contact electrode cell made according to the method of any one of claims 1-5, wherein on a front side of the silicon wafer, an ultra-thin silicon oxide layer is deposited over the n + surface doped with phosphorus, and on a reverse side of the silicon wafer, an interlocking structure of p + / p ++ and n + / n ++ is provided, and an ultra-thin silicon oxide layer is deposited on the surface. 1/1

101 Silicon wafer 105 Phosphosilicate glass

103 Borosilicate glass 101 Silicon wafer 103 Borosilicate glass 104 Phosphorus diffusion layer n + 105 Phosphosilicate glass 102 Boron diffusion layer p + 102 Boron diffusion layer p +

102 Boron diffusion layer p + 101 Silicon wafer 103 103 Borosilicate glass 102 Boron diffusion layer p + 101 Silicon wafer 102

102 103 Borosilicate glass

108 Phosphorus diffusion layer n ++ 111 Aluminum electrode