CN113948611B - P-type IBC battery, preparation method thereof, assembly and photovoltaic system - Google Patents
P-type IBC battery, preparation method thereof, assembly and photovoltaic system Download PDFInfo
- Publication number
- CN113948611B CN113948611B CN202111202591.7A CN202111202591A CN113948611B CN 113948611 B CN113948611 B CN 113948611B CN 202111202591 A CN202111202591 A CN 202111202591A CN 113948611 B CN113948611 B CN 113948611B
- Authority
- CN
- China
- Prior art keywords
- silicon wafer
- layer
- silicon
- front side
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 207
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 207
- 239000010703 silicon Substances 0.000 claims abstract description 207
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 92
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 92
- 239000011574 phosphorus Substances 0.000 claims abstract description 92
- 238000009792 diffusion process Methods 0.000 claims abstract description 78
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 42
- 238000007667 floating Methods 0.000 claims abstract description 41
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims description 68
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 44
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 44
- 230000005641 tunneling Effects 0.000 claims description 41
- 230000008021 deposition Effects 0.000 claims description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 239000005360 phosphosilicate glass Substances 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 10
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 8
- 238000000608 laser ablation Methods 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 abstract description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000003513 alkali Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000002310 reflectometry Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Sustainable Energy (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention is suitable for the technical field of solar cells, and provides a P-type IBC solar cell, a preparation method, a component and a system thereof. The amorphous silicon layer deposited on the front side of the silicon wafer plays a role in blocking when carrying out severe phosphorus diffusion on the front side of the silicon wafer, so that the front side phosphorus diffusion amount is small and controllable, the FFE floating junction structure with excellent performance is obtained, and the conversion efficiency of the P-type IBC solar cell is greatly improved. The back of the silicon wafer is not required to be made with a mask, so that the pollution of the process is avoided, the floating junction can be formed on the front side by one-time double-sided phosphorus diffusion, the process is simple, and the performance is excellent.
Description
Technical Field
The invention belongs to the field of solar cells, and particularly relates to a P-type IBC cell, a preparation method and a module thereof, and a photovoltaic system.
Background
In order to improve efficiency of the P-type IBC battery, the front floating junction FFE of the silicon wafer is a hot spot technology studied at present, and can passivate the front surface of the silicon wafer, namely, the front floating junction injects a certain amount of minority electrons into the P-type substrate, so that the concentration of the minority electrons in the substrate is increased to a certain extent, the short circuit current of the P-type IBC battery is higher than that of other passivation technologies, and the battery conversion efficiency is improved.
Current FFE is typically prepared by single P diffusion, since the front and back sides of the wafer are subjected to different levels of P diffusion, the front side of the wafer only needs to be lightly diffused, while the back side of the wafer needs to be re-diffused. Therefore, the front and back sides of the wafer need to be separated for P diffusion. When the FFE floating junction is prepared on the front surface, the back surface of the silicon wafer needs to be separately subjected to P diffusion and a mask needs to be prepared for protecting the back surface, the process steps are complex, and the steps are easy to bring about process pollution, so that the passivation effect of the FFE is affected, the performance of the P-type IBC battery is poor, and the cost and the efficiency of the P-type IBC battery are both unfavorable.
Disclosure of Invention
The embodiment of the invention aims to provide a preparation method of a P-type IBC solar cell, which aims to solve the problems of process pollution and higher cost caused by complex working procedures of the existing preparation method.
The embodiment of the invention is realized in such a way that a preparation method of a P-type IBC solar cell is provided, and the preparation method comprises the following steps: the preparation method comprises the following steps:
texturing the silicon wafer;
preparing tunneling oxide layers on the front and back surfaces of the silicon wafer;
depositing an amorphous silicon layer on the tunneling oxide layer on the front side and the back side of the silicon wafer;
simultaneously performing phosphorus diffusion on the front side and the back side of the silicon wafer, forming a phosphorus inner diffusion layer on the front side and the back side of the silicon wafer, and forming a floating junction on the front side of the silicon wafer;
performing laser ablation etching on the back surface of the silicon wafer, wherein an etched region forms a P region, and an unetched region forms an N region;
removing the amorphous silicon layer and the tunneling oxide layer on the front surface of the silicon wafer;
depositing a first silicon nitride layer on a floating junction on the front surface of the silicon wafer;
depositing a second silicon nitride layer on the amorphous silicon layer on the back surface of the silicon wafer;
and preparing a metal electrode on the second silicon nitride layer.
Further, the simultaneous phosphorus diffusion on the front and back surfaces of the silicon wafer comprises the following steps:
and placing the silicon wafer into a diffusion furnace, introducing a phosphorus source into the diffusion furnace, and diffusing for 20-30 minutes under the condition that the temperature is 750-800 ℃, wherein the front and the back of the silicon wafer face the phosphorus source.
Further, the amorphous silicon layer on the front and back of the silicon wafer forms an N+ polysilicon layer after phosphorus diffusion, and the phosphorus concentration on the surface of the polysilicon layer is 1-8 x 10 20 Individual/cm 3 The phosphorus concentration of the surface of the silicon wafer is 1-5 x 10 19 Individual/cm 3 。
Further, the step of removing the amorphous silicon layer and the tunneling oxide layer on the front surface of the silicon wafer includes:
immersing the front surface of the silicon wafer into KOH, and removing a polysilicon layer on the front surface of the silicon wafer, wherein the mass concentration of the KOH is 5-15%, and the reaction temperature is 55-70 ℃;
and then removing the tunneling oxide layer on the front side of the silicon wafer by using HF.
Furthermore, the laser ablation etching is performed on the back surface of the silicon wafer, the etched region forms a P region, and the non-etched region forms an N region, and then the method further comprises the following steps:
cleaning the etched laser damage layer by adopting KOH;
and removing the phosphosilicate glass PSG on the front surface of the silicon wafer by using HF.
Further, the depositing a first silicon nitride layer on the floating junction on the front side of the silicon wafer and depositing a second silicon nitride layer on the amorphous silicon layer on the back side of the silicon wafer comprises:
and depositing the first silicon nitride layer in a deposition furnace tube to prepare the first silicon nitride layer with the deposition thickness of 70-80nm and the refractive index of 2.05-2.15.
And (3) depositing the second silicon nitride layer in a deposition furnace tube to prepare the second silicon nitride layer with the deposition thickness of 70-100nm and the refractive index of 2.15-2.25.
Further, the depositing the amorphous silicon layer on the front and back surfaces of the silicon wafer comprises:
and introducing silane into a deposition furnace tube to deposit the amorphous silicon layer, and preparing the amorphous silicon layer with the deposition thickness of 80-300nm on the front and back surfaces of the silicon wafer.
Further, the depositing the amorphous silicon layer on the front and back surfaces of the silicon wafer comprises:
and when the front and back surfaces of the silicon wafer are subjected to amorphous silicon layer deposition, phosphine is introduced into a deposition furnace tube so as to form an N+ amorphous silicon layer on the front and back surfaces of the silicon wafer.
Still further, after the removing the amorphous silicon layer and the tunneling oxide layer on the front surface of the silicon wafer and before depositing the first silicon nitride layer on the floating junction on the front surface of the silicon wafer, the method further comprises:
and a high-temperature annealing treatment process, wherein a silicon oxide layer with the thickness of 2-10nm is formed on the front and back surfaces of the silicon wafer, the annealing temperature is 550-750 ℃, and the annealing time is 15-30min.
The invention also provides a P-type IBC solar cell, which is prepared according to the preparation method; the P-type IBC solar cell includes: a silicon wafer; the front surface of the silicon wafer is sequentially provided with a floating junction and a first silicon nitride layer; the back of the silicon chip is provided with an N-type region and a P-type region; the N-type region comprises a tunneling oxide layer, an N+ polysilicon layer and a second silicon nitride layer which are sequentially arranged, and the P-type region comprises a silicon nitride layer; the semiconductor device further comprises an N-type electrode and a P-type electrode, wherein the N-type electrode is in conductive connection with the N+ polysilicon layer, and the P-type electrode is in conductive connection with the silicon wafer.
The invention also provides a solar cell module, which is manufactured by sorting, testing and packaging the P-type IBC solar cells respectively.
Another embodiment of the present invention also provides a photovoltaic system comprising a solar cell module as described above.
According to the preparation method of the P-type IBC solar cell, the tunneling oxide layer and the amorphous silicon layer are simultaneously deposited on the front side and the back side of the silicon wafer, phosphorus diffusion is simultaneously carried out on the front side and the back side of the silicon wafer, the amorphous silicon layer is converted into the N+ polycrystalline silicon layer by means of double-sided phosphorus diffusion, meanwhile, phosphorus continues to diffuse into the silicon wafer through the tunneling oxide layer, a phosphorus inner expansion layer is formed on the front side and the back side of the silicon wafer, and a floating junction FFE is formed on the front side of the silicon wafer. The amorphous silicon layer deposited on the front side of the silicon wafer plays a role in blocking when carrying out severe phosphorus diffusion on the front side of the silicon wafer, so that the front side phosphorus diffusion amount is small and controllable, the FFE floating junction structure with excellent performance is obtained, and the conversion efficiency of the P-type IBC solar cell is greatly improved. Compared with the prior art, the method has the advantages that the front side and the back side of the silicon wafer are required to be subjected to phosphorus diffusion for two times, the mask is not required to be made on the back side of the silicon wafer, the process pollution is avoided, the floating junction can be formed on the front side through one-time double-sided phosphorus diffusion, and meanwhile, the back side phosphorus diffusion is completed.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a P-type IBC solar cell according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a P-type IBC solar cell according to an embodiment of the present invention.
Reference numerals illustrate:
10. an N-type electrode; 20. a P-type electrode; s1, a silicon wafer; s2, a floating junction; s3, a first silicon nitride layer; s4, tunneling oxide layers on the back surface of the silicon wafer; s5, an N+ polycrystalline silicon layer on the back surface of the silicon wafer; s6, a second silicon nitride layer.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
According to the invention, the tunneling oxide layer and the amorphous silicon layer are simultaneously deposited on the front side and the back side of the silicon wafer, then phosphorus diffusion is simultaneously carried out on the front side and the back side of the silicon wafer, then the amorphous silicon layer is converted into the N+ polycrystalline silicon layer by means of double-sided phosphorus diffusion, meanwhile, phosphorus continues to diffuse into the silicon wafer through the tunneling oxide layer, a phosphorus inner diffusion layer is formed on the front side and the back side of the silicon wafer, and a floating junction FFE is formed on the front side of the silicon wafer. The amorphous silicon layer deposited on the front side of the silicon wafer plays a role in blocking when carrying out severe phosphorus diffusion on the front side of the silicon wafer, so that the front side phosphorus diffusion amount is small and controllable, the FFE floating junction structure with excellent performance is obtained, and the conversion efficiency of the P-type IBC solar cell is greatly improved. Compared with the prior art, P diffusion is required to be carried out on the front surface and the back surface of the silicon wafer at the same time, and the invention does not need to carry out mask on the back surface of the silicon wafer, avoids the pollution of the process, can form a floating junction on the front surface by one-time double-sided phosphorus diffusion, and simultaneously completes the phosphorus diffusion on the back surface.
Example 1
Referring to fig. 1, a flow chart of a method for preparing a P-type IBC solar cell according to a first embodiment of the present invention is shown, for convenience of explanation, only a portion related to the embodiment of the present invention, and specifically, the method includes:
step S11, texturing is carried out on the silicon wafer S1;
in the embodiment of the invention, a P-type monocrystalline silicon piece S1 with the resistivity of 0.5-3 omega cm is selected, alkali texturing is carried out on the front surface and the back surface of the silicon piece S1, a texturing agent is a KOH aqueous solution with the volume ratio of 2%, a texturing additive with the volume ratio of 0.5-0.7%, the temperature is 80 ℃, the texturing time is 300S, and the front surface and the back surface of a substrate of the P-type monocrystalline silicon piece S1 form pyramid-shaped antireflection textured surfaces, so that the reflectivity of the antireflection textured surfaces in the whole wave band of 300-1200nm is 9-15%.
Since the resistivity is different for the same silicon wafer at different test positions, the resistivity of the silicon wafer S1 is a range value and is not a fixed value.
Further, polishing the back of the silicon wafer S1 is further included after the front and back of the silicon wafer S1 is textured;
in the embodiment of the invention, the back surface of the silicon wafer S1 after texturing is polished by acid polishing or alkali polishing to obtain the back surface of the silicon wafer S1 with light reflection. Specifically, after acid polishing, the reflectivity of the back surface of the silicon wafer S1 is 25-35%; after alkali polishing, the reflectivity of the back surface of the silicon wafer S1 is 35-45%.
Step S21: preparing tunneling oxide layers on the front and back surfaces of a silicon wafer S1;
in the embodiment of the invention, the silicon wafer S1 is placed in an oxidation furnace, and meanwhile, the front surface and the back surface of the silicon wafer S1 are subjected to oxide layer deposition. And preparing tunneling oxide layers on the front surface and the back surface of the silicon wafer S1 respectively to obtain tunneling oxide layers on the front surface and the back surface of the silicon wafer S4 with deposition thicknesses of 1-3 nm.
Wherein the process conditions for depositing the oxide layer by using the oxidation furnace are as follows: the oxidation temperature is 550-650 ℃; oxygen flow/nitrogen flow = 1-5:10; the oxidation time is 3-10min; oxygen is not introduced before oxidation, and the temperature rising speed is 10-20 ℃/min.
It will be appreciated that in other embodiments, LPCVD (low pressure chemical vapor deposition) equipment may be used to complete the deposition of tunnel oxide layers on the front and back sides of the wafer.
Step S31: depositing an amorphous silicon layer on the tunneling oxide layer on the front side and the back side of the silicon wafer S1;
in the embodiment of the invention, firstly, a silicon wafer S1 is put into a graphite boat or a quartz boat and is sent into a deposition tube, the front and back surfaces of the silicon wafer S1 are deposited by adopting a PECVD (plasma enhanced chemical vapor deposition) method or an LPCVD (low pressure chemical vapor deposition) method, and a silicon wafer front amorphous silicon layer and a silicon wafer back amorphous silicon layer with deposition thickness of 80-300nm are respectively prepared on the front and back surfaces of the silicon wafer S1. Preferably, the LPCVD equipment is used for depositing the amorphous silicon layer on the front side and the back side of the silicon wafer S1, and compared with the PECVD equipment, the LPCVD equipment is used for depositing the amorphous silicon layer on the front side and the back side of the silicon wafer S1 more uniformly, so that the deposition effect is better.
Step S41: simultaneously performing phosphorus diffusion on the front side and the back side of the silicon wafer S1, forming a phosphorus inner diffusion layer on the front side and the back side of the silicon wafer S1, and forming a floating junction S2 on the front side of the silicon wafer S1;
in the embodiment of the invention, a silicon wafer S1 is placed in a diffusion furnace, a phosphorus source is introduced into the diffusion furnace, and the front and the back of the silicon wafer S1 face the phosphorus source. The reaction gas is POCl 3 And oxygen, wherein the diffusion temperature is 750-800 ℃, the diffusion time is 20-30 minutes, phosphorus is diffused into the amorphous silicon layers on the front side and the back side of the silicon wafer at high temperature, and the amorphous silicon layers are converted into N+ polycrystalline silicon layers, so that the phosphorus concentration of the surfaces of the N+ polycrystalline silicon layers S5 on the front side and the back side of the silicon wafer reaches 1-8 x 10 20 Individual/cm 3 。
Meanwhile, phosphorus passes through tunneling oxide layers on the front side and the back side of the silicon wafer S1 at high temperature and diffuses into a substrate of the silicon wafer S1, a phosphorus inner diffusion layer is formed on the front side and the back side of the silicon wafer S1, and a floating junction S2 is further formed on the front side of the silicon wafer S1. Wherein the phosphorus diffusion depth is 80-200nm, and the phosphorus concentration on the surface of the silicon wafer S1 is 1-5 x 10 19 Individual/cm 3 。
According to the embodiment of the invention, the phosphorus re-expansion is carried out on the front side and the back side of the silicon wafer, the amorphous silicon layer deposited on the front side of the silicon wafer plays a role in blocking the heavy phosphorus diffusion on the front side, so that the front side phosphorus diffusion amount is small and controllable, the FFE floating junction structure with excellent performance is obtained, and the conversion efficiency of the P-type IBC solar cell is greatly improved. In addition, the phosphorus re-expansion of the back surface of the silicon wafer is completed, and a phosphorus diffusion layer is formed on the back surface of the silicon wafer. The back of the silicon wafer is not required to be made with a mask, so that the process pollution is avoided, the floating junction can be formed on the front of the silicon wafer by one-time double-sided phosphorus diffusion, and meanwhile, the phosphorus diffusion on the back of the silicon wafer is completed.
Step S51: performing laser ablation etching on the back surface of the silicon wafer S1, wherein an etched region forms a P region, and an unetched region forms an N region;
in the embodiment of the invention, the n+ polysilicon layer and the tunneling oxide layer are removed by a laser ablation method to form a P-type region, wherein the P-type region is used for forming a P-type structure, and the region from which the n+ polysilicon layer and the tunneling oxide layer are not removed is an N-type region used for forming an N-type structure. Wherein the P-type regions and the N-type regions are alternately arranged.
In order to form the N-type region and the P-type region, the existing preparation method needs to be realized by adopting a plurality of masks, and the method can be realized by adopting the phosphosilicate glass PSG formed by phosphorus diffusion in the steps as the masks through a laser ablation method, thereby effectively simplifying the production process and improving the production efficiency.
Further, laser ablation etching is performed on the back surface of the silicon wafer S1 to form a P region, and after the non-etched region forms an N region, the method further comprises the steps of:
step 1: cleaning the etched laser damage layer by adopting KOH;
in the embodiment of the invention, the KOH mass concentration is controlled to be 1.5-2%, the reaction time is 4-10min, and the patterned P region is corroded to a depth of 4-8 microns; the addition of the cleaning additive can control the phosphosilicate glass PSG formed by the front and back surfaces of the silicon wafer S1 after the double-sided phosphorus diffusion not to be corroded by alkali liquor basically.
Step 2: and removing phosphosilicate glass PSG on the front surface of the silicon wafer S1 by using HF.
In the embodiment of the invention, a groove type cleaning machine is adopted to remove phosphosilicate glass PSG on the front surface of the silicon wafer S1. Wherein the mass concentration of HF is 2-4%; after removal, washing with water and then drying.
Step S61: removing the amorphous silicon layer and the tunneling oxide layer on the front surface of the silicon wafer S1;
in the embodiment of the invention, the step of removing the amorphous silicon layer and the tunneling oxide layer on the front surface of the silicon wafer S1 includes:
step 1: removing the amorphous silicon layer on the front surface of the silicon wafer S1 by utilizing KOH; immersing the front side of the silicon wafer into KOH, and removing the N+ polysilicon layer on the front side; after phosphorus diffusion is performed on the front and back surfaces of the silicon wafer S1, the amorphous silicon layer on the front surface of the silicon wafer is crystallized into an n+ polysilicon layer, and at this time, the crystallized n+ polysilicon layer needs to be removed. Specifically, the mass concentration of KOH is 5-15%, and the reaction temperature is 55-70 ℃; specifically, a chain type cleaning machine is adopted to remove the N+ polysilicon layer on the front side of the silicon wafer S1.
Step 2: and then removing the tunneling oxide layer on the front surface of the silicon wafer S1 by using HF. After the tunneling oxide layer is removed, washing is performed, and then drying is performed, so that the front amorphous silicon layer and the tunneling oxide layer of the silicon wafer S1 are removed.
In the embodiment of the invention, HF is utilized to remove the phosphosilicate glass PSG on the back surface of the silicon wafer S1, water washing is carried out after the removal, and then drying is carried out, so that the removal of the phosphosilicate glass PSG on the back surface of the silicon wafer S1 is completed.
Step S71: depositing a first silicon nitride layer S3 on a floating junction S2 on the front surface of the silicon wafer S1;
in an embodiment of the present invention, the step of forming the first silicon nitride layer S3 on the floating junction S2 includes:
and (3) depositing the first silicon nitride layer S3 in a deposition furnace tube by adopting a PECVD method to prepare the first silicon nitride layer S3 with the deposition thickness of 70-80nm and the refractive index of 2.05-2.15.
Specifically, the deposition temperature for preparing the first silicon nitride layer S3 is 350-500 ℃, the deposition pressure is 1500-1800mTorr, and the deposition duty ratio is 5:50-5:90; the deposition power is 9000-15500W, the deposition time is 500-600S, the silane flow rate in the deposition gas for preparing the first silicon nitride layer S3 is 800-1200sccm, and the ammonia flow rate is 4000-9000sccm.
Step S81: depositing a second silicon nitride layer S6 on the N+ polycrystalline silicon layer S5 on the back surface of the silicon wafer;
in the embodiment of the present invention, the step of forming the second silicon nitride layer S6 on the n+ polysilicon layer S5 on the back surface of the silicon wafer includes:
and (3) depositing the second silicon nitride layer S6 in a deposition furnace tube by adopting a PECVD method to prepare the second silicon nitride layer S6 with the deposition thickness of 70-100nm and the refractive index of 2.15-2.25.
Specifically, the deposition temperature for preparing the second silicon nitride layer S6 is 350-500 ℃, the deposition pressure is 1500-1800mTorr, and the deposition duty ratio is 5:50-5:90; the deposition power is 9000-15500W, the deposition time is 500-600S, the silane flow rate in the deposition gas for preparing the second silicon nitride layer S6 is 800-1200sccm, and the ammonia flow rate is 4000-9000sccm
Step S91: a metal electrode is prepared on the second silicon nitride layer S6.
In the embodiment of the invention, the preparation of the metal electrode on the second silicon nitride layer S6 on the back surface of the silicon wafer S1 comprises the following two steps:
step 1: a first slot is formed in the P region by adopting a laser slotting method, the second silicon nitride layer S6 is etched into the silicon wafer S1, and a P-type electrode 20 is formed in the first slot in the P region.
Step 2: and printing by using aluminum paste in the first slot by adopting a screen printing process, and forming the P-type electrode 20 by ohmic contact with the silicon wafer S1. And (3) forming an N-type electrode 10 by directly using silver paste to burn through a second silicon oxynitride layer S6 of the N region to contact an N+ polysilicon layer S5 on the back surface of the silicon wafer without slotting in the N region. After the electrode is printed, the electrode needs to be sintered and dried so as to form effective combination between the electrode and the battery piece. In the embodiment of the invention, the sintering temperature is 700-850 ℃. Preferably, the sintering temperature is 750 to 810 ℃.
In the embodiment of the invention, the tunneling oxide layer and the amorphous silicon layer are simultaneously deposited on the front side and the back side of the silicon wafer, then phosphorus diffusion is simultaneously carried out on the front side and the back side of the silicon wafer, then the amorphous silicon layer is converted into the N+ polycrystalline silicon layer by means of double-sided phosphorus diffusion, meanwhile, phosphorus continues to diffuse into the silicon wafer through the tunneling oxide layer, a phosphorus inner expansion layer is formed on the front side and the back side of the silicon wafer, and a floating junction FFE is formed on the front side of the silicon wafer. The amorphous silicon layer deposited on the front side of the silicon wafer plays a role in blocking when carrying out severe phosphorus diffusion on the front side of the silicon wafer, so that the front side phosphorus diffusion amount is small and controllable, the FFE floating junction structure with excellent performance is obtained, and the conversion efficiency of the P-type IBC solar cell is greatly improved. In addition, the back of the silicon wafer is not required to be made with a mask, so that the process pollution is avoided, a floating junction can be formed on the front side by one-time double-sided phosphorus diffusion, and meanwhile, the phosphorus diffusion on the back side is completed.
Example two
On the basis of the first embodiment, the second embodiment of the present invention further provides a method for preparing a P-type IBC solar cell, which further includes, after step S61 and before step S71: and a high-temperature annealing treatment process, and forming a silicon oxide layer with the thickness of 2-10nm on the front and back surfaces of the silicon wafer S1, wherein the annealing temperature is 550-750 ℃ and the annealing time is 15-30min.
In the embodiment of the invention, the amorphous silicon layer and the tunneling oxide layer on the front surface of the silicon wafer are removed, and the high-temperature annealing process is further included before the first silicon nitride layer is deposited on the floating junction on the front surface of the silicon wafer, so that the silicon oxide layers are formed on the front surface and the back surface of the silicon wafer, and the passivation effect of the P-type IBC solar cell is improved.
Example III
On the basis of any one of the above embodiments, a third embodiment of the present invention provides a method for manufacturing a P-type IBC solar cell, where depositing an amorphous silicon layer on the front and back surfaces of a silicon wafer S1 includes: phosphine PH in deposition furnace tube 3 An n+ amorphous silicon layer is formed.
In the embodiment of the invention, an in-situ doping mode can be adopted, namely, PH is adopted when amorphous silicon layers are deposited on the front side and the back side of the silicon wafer S1 3 Directly forming an N+ amorphous silicon layer on the tunneling oxide layers on the front side and the back side of the silicon wafer S1; the subsequent double-sided phosphorus diffusion step is continued so that the phosphorus concentration on the surface of the n+ polysilicon layer and the phosphorus concentration on the surface of the silicon wafer are both greater than those of the first embodiment. Wherein the phosphorus concentration on the surface of the N+ polysilicon layer is 5-10 x 10 20 Individual/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the The phosphorus concentration of the surface of the silicon slice S1 is 3-8 x 10 19 Individual/cm 3 。
According to the P-type IBC solar energy preparation method provided by the embodiment of the invention, phosphine is introduced when amorphous silicon is deposited on the front side and the back side of the silicon wafer, and an N+ amorphous silicon layer is directly formed on the tunneling oxide layers on the front side and the back side of the silicon wafer, so that the phosphorus concentration of the N+ polycrystalline silicon layer and the surface of the silicon wafer after the subsequent double-sided phosphorus diffusion is improved.
Example IV
The fourth embodiment of the invention provides a P-type IBC solar cell, which is manufactured by the manufacturing method.
The P-type IBC solar cell includes: the front surface of the silicon wafer S1 is sequentially provided with a floating junction S2 and a first silicon nitride layer S3, the back surface of the silicon wafer S1 is provided with an N-type region and a P-type region, the N-type region comprises a tunneling oxide layer S4 on the back surface of the silicon wafer, an N+ polycrystalline silicon layer S5 on the back surface of the silicon wafer and a second silicon nitride layer S6 which are sequentially arranged, and the P-type region comprises a second silicon nitride layer S6;
the solar cell also comprises an N-type electrode 10 and a P-type electrode 20, wherein the N-type electrode 10 is in conductive connection with an N+ polysilicon layer S5 on the back surface of the silicon wafer, the P-type electrode 20 is in conductive connection with a silicon wafer S1, the P-type electrode 20 is a metal positive electrode, and the N-type electrode 10 is a metal negative electrode.
The embodiment provides a high-performance and high-reliability P-type IBC solar cell, which is characterized in that a tunneling oxide layer and an amorphous silicon layer are simultaneously deposited on the front side and the back side of a silicon wafer, then phosphorus diffusion is simultaneously carried out on the front side and the back side of the silicon wafer, then the amorphous silicon layer is converted into an N+ polycrystalline silicon layer by means of double-sided phosphorus diffusion, meanwhile, phosphorus continues to diffuse into the silicon wafer through the tunneling oxide layer, and a phosphorus inner diffusion layer is formed on the front side and the back side of the silicon wafer, so that a floating junction FFE is formed on the front side of the silicon wafer. The amorphous silicon layer deposited on the front side of the silicon wafer plays a role in blocking when carrying out severe phosphorus diffusion on the front side of the silicon wafer, so that the front side phosphorus diffusion amount is small and controllable, the FFE floating junction structure with excellent performance is obtained, and the conversion efficiency of the P-type IBC solar cell is greatly improved. In addition, the back of the silicon wafer is not required to be made with a mask, so that the process pollution is avoided, a floating junction can be formed on the front side by one-time double-sided phosphorus diffusion, and meanwhile, the phosphorus diffusion on the back side is completed.
Example five
The fifth embodiment of the present invention further provides a solar cell module, which is manufactured by sorting, testing, and packaging the P-type IBC solar cells according to the foregoing embodiments.
In the solar cell module in this embodiment, the tunneling oxide layer and the amorphous silicon layer are simultaneously deposited on the front side and the back side of the silicon wafer, then phosphorus diffusion is simultaneously performed on the front side and the back side of the silicon wafer, then the amorphous silicon layer is converted into the n+ polysilicon layer by means of double-sided phosphorus diffusion, meanwhile, phosphorus continues to diffuse into the silicon wafer through the tunneling oxide layer, and phosphorus inner diffusion layers are formed on the front side and the back side surfaces of the silicon wafer, so that a floating junction FFE is formed on the front side of the silicon wafer. The amorphous silicon layer deposited on the front side of the silicon wafer plays a role in blocking when carrying out severe phosphorus diffusion on the front side of the silicon wafer, so that the front side phosphorus diffusion amount is small and controllable, the FFE floating junction structure with excellent performance is obtained, and the conversion efficiency of the P-type IBC solar cell is greatly improved. In addition, the back of the silicon wafer is not required to be made with a mask, so that the process pollution is avoided, a floating junction can be formed on the front side by one-time double-sided phosphorus diffusion, and meanwhile, the phosphorus diffusion on the back side is completed.
Example six
The sixth embodiment of the present invention also provides a photovoltaic system comprising the solar cell module as in the previous embodiment.
In the photovoltaic system in this embodiment, the tunneling oxide layer and the amorphous silicon layer are simultaneously deposited on the front side and the back side of the silicon wafer, then phosphorus diffusion is simultaneously performed on the front side and the back side of the silicon wafer, then the amorphous silicon layer is converted into the n+ polysilicon layer by means of double-sided phosphorus diffusion, meanwhile, phosphorus continues to diffuse into the silicon wafer through the tunneling oxide layer, and a phosphorus inner diffusion layer is formed on the front side and the back side surface of the silicon wafer, so that a floating junction FFE is formed on the front side of the silicon wafer. The amorphous silicon layer deposited on the front side of the silicon wafer plays a role in blocking when carrying out severe phosphorus diffusion on the front side of the silicon wafer, so that the front side phosphorus diffusion amount is small and controllable, the FFE floating junction structure with excellent performance is obtained, and the conversion efficiency of the P-type IBC solar cell is greatly improved. In addition, the back of the silicon wafer is not required to be made with a mask, so that the process pollution is avoided, a floating junction can be formed on the front side by one-time double-sided phosphorus diffusion, and meanwhile, the phosphorus diffusion on the back side is completed.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (8)
1. The preparation method of the P-type IBC battery is characterized by comprising the following steps of:
texturing the silicon wafer;
preparing tunneling oxide layers on the front and back surfaces of the silicon wafer;
depositing an amorphous silicon layer on the tunneling oxide layer on the front side and the back side of the silicon wafer;
simultaneously performing phosphorus diffusion on the front side and the back side of the silicon wafer, forming a phosphorus inner diffusion layer on the front side and the back side of the silicon wafer, and forming a floating junction on the front side of the silicon wafer;
performing laser ablation etching on the back surface of the silicon wafer, wherein an etched region forms a P region, and an unetched region forms an N region;
removing the amorphous silicon layer and the tunneling oxide layer on the front surface of the silicon wafer;
depositing a first silicon nitride layer on a floating junction on the front surface of the silicon wafer;
depositing a second silicon nitride layer on the amorphous silicon layer on the back surface of the silicon wafer;
and preparing a metal electrode on the second silicon nitride layer.
2. The method for preparing the P-type IBC cell according to claim 1, wherein the simultaneous phosphorus diffusion on the front and back surfaces of the silicon wafer comprises the following steps:
and placing the silicon wafer into a diffusion furnace, introducing a phosphorus source into the diffusion furnace, and diffusing for 20-30 minutes under the condition that the temperature is 750-800 ℃, wherein the front and the back of the silicon wafer face the phosphorus source.
3. The method for preparing the P-type IBC cell according to claim 1, wherein the step of removing the amorphous silicon layer and the tunneling oxide layer on the front surface of the silicon wafer comprises:
immersing the front surface of the silicon wafer into KOH, and removing a polysilicon layer on the front surface of the silicon wafer, wherein the mass concentration of the KOH is 5-15%, and the reaction temperature is 55-70 ℃;
and then removing the tunneling oxide layer on the front side of the silicon wafer by using HF.
4. The method for preparing the P-type IBC battery according to claim 1, wherein the laser ablation etching is performed on the back surface of the silicon wafer, the etched region forms a P region, and the non-etched region forms an N region, and then the method further comprises:
cleaning the etched laser damage layer by adopting KOH;
and removing the phosphosilicate glass PSG on the front surface of the silicon wafer by using HF.
5. The method of claim 1, wherein depositing a first silicon nitride layer on the floating junction on the front side of the silicon wafer and depositing a second silicon nitride layer on the amorphous silicon layer on the back side of the silicon wafer comprises:
depositing the first silicon nitride layer in a deposition furnace tube to prepare a first silicon nitride layer with a deposition thickness of 70-80nm and a refractive index of 2.05-2.15;
and (3) depositing the second silicon nitride layer in a deposition furnace tube to prepare the second silicon nitride layer with the deposition thickness of 70-100nm and the refractive index of 2.15-2.25.
6. The method for preparing the P-type IBC cell according to claim 1, wherein depositing the amorphous silicon layer on the front and back surfaces of the silicon wafer comprises:
and introducing silane into a deposition furnace tube to deposit the amorphous silicon layer, and preparing the amorphous silicon layer with the deposition thickness of 80-300nm on the front and back surfaces of the silicon wafer.
7. The method of fabricating a P-type IBC cell according to claim 6, wherein depositing an amorphous silicon layer on the front and back surfaces of the silicon wafer comprises:
and when the front and back surfaces of the silicon wafer are subjected to amorphous silicon layer deposition, phosphine is introduced into a deposition furnace tube so as to form an N+ amorphous silicon layer on the front and back surfaces of the silicon wafer.
8. The method of claim 1, wherein the removing the amorphous silicon layer and the tunnel oxide layer on the front side of the silicon wafer and before depositing the first silicon nitride layer on the floating junction on the front side of the silicon wafer further comprises:
and a high-temperature annealing treatment process, wherein a silicon oxide layer with the thickness of 2-10nm is formed on the front and back surfaces of the silicon wafer, the annealing temperature is 550-750 ℃, and the annealing time is 15-30min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111202591.7A CN113948611B (en) | 2021-10-15 | 2021-10-15 | P-type IBC battery, preparation method thereof, assembly and photovoltaic system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111202591.7A CN113948611B (en) | 2021-10-15 | 2021-10-15 | P-type IBC battery, preparation method thereof, assembly and photovoltaic system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113948611A CN113948611A (en) | 2022-01-18 |
| CN113948611B true CN113948611B (en) | 2023-12-01 |
Family
ID=79330179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111202591.7A Active CN113948611B (en) | 2021-10-15 | 2021-10-15 | P-type IBC battery, preparation method thereof, assembly and photovoltaic system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113948611B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114784140B (en) * | 2022-04-02 | 2024-04-05 | 西安隆基乐叶光伏科技有限公司 | Topcon battery preparation method, topcon battery and winding-removing plating tank type cleaning machine |
| CN115020534A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of back-side graphical N region of IBC battery |
| CN115207169B (en) * | 2022-06-23 | 2024-05-17 | 浙江爱旭太阳能科技有限公司 | P-type IBC solar cell, preparation method thereof, cell assembly and photovoltaic system |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011160819A2 (en) * | 2010-06-23 | 2011-12-29 | International Solar Energy Research Center Konstanz E.V. | Method for fabrication of a back side contact solar cell |
| CN102800738A (en) * | 2011-05-24 | 2012-11-28 | 中国科学院微电子研究所 | Interdigital back contact type solar battery and preparation method thereof |
| WO2013087458A1 (en) * | 2011-12-16 | 2013-06-20 | International Solar Energy Research Center Konstanz E.V. | Back-contact solar cell and method for producing a back-contact solar cell |
| CN103337561A (en) * | 2013-07-12 | 2013-10-02 | 苏州润阳光伏科技有限公司 | Fabrication method of surface fields of full-back-contact solar cell |
| CN109244194A (en) * | 2018-11-06 | 2019-01-18 | 东方日升（常州）新能源有限公司 | A kind of preparation method of low cost p-type all back-contact electrodes crystal silicon solar battery |
| CN110289319A (en) * | 2019-05-14 | 2019-09-27 | 江苏顺风光电科技有限公司 | In conjunction with the preparation method of the selective emitter monocrystalline PERC battery of tunnel oxide |
| CN111584685A (en) * | 2020-05-28 | 2020-08-25 | 江西展宇新能科技有限公司 | Novel solar cell and preparation method thereof |
| CN111864008A (en) * | 2019-04-15 | 2020-10-30 | 江苏顺风光电科技有限公司 | Preparation method of P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell |
| CN112490325A (en) * | 2020-11-27 | 2021-03-12 | 泰州中来光电科技有限公司 | Preparation method of solar cell |
| CN113224202A (en) * | 2021-03-15 | 2021-08-06 | 浙江爱旭太阳能科技有限公司 | POLO-IBC solar cell and preparation method thereof |
| CN113363354A (en) * | 2021-06-04 | 2021-09-07 | 浙江爱旭太阳能科技有限公司 | Preparation method of P-type back contact crystalline silicon solar cell |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102009011305A1 (en) * | 2009-03-02 | 2010-09-09 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Back contacting solar cells and methods of making same |
| CN103811591B (en) * | 2014-02-27 | 2016-10-05 | 友达光电股份有限公司 | The preparation method of back contact solar battery |
-
2021
- 2021-10-15 CN CN202111202591.7A patent/CN113948611B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011160819A2 (en) * | 2010-06-23 | 2011-12-29 | International Solar Energy Research Center Konstanz E.V. | Method for fabrication of a back side contact solar cell |
| CN102800738A (en) * | 2011-05-24 | 2012-11-28 | 中国科学院微电子研究所 | Interdigital back contact type solar battery and preparation method thereof |
| WO2013087458A1 (en) * | 2011-12-16 | 2013-06-20 | International Solar Energy Research Center Konstanz E.V. | Back-contact solar cell and method for producing a back-contact solar cell |
| CN103337561A (en) * | 2013-07-12 | 2013-10-02 | 苏州润阳光伏科技有限公司 | Fabrication method of surface fields of full-back-contact solar cell |
| CN109244194A (en) * | 2018-11-06 | 2019-01-18 | 东方日升（常州）新能源有限公司 | A kind of preparation method of low cost p-type all back-contact electrodes crystal silicon solar battery |
| CN111864008A (en) * | 2019-04-15 | 2020-10-30 | 江苏顺风光电科技有限公司 | Preparation method of P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell |
| CN110289319A (en) * | 2019-05-14 | 2019-09-27 | 江苏顺风光电科技有限公司 | In conjunction with the preparation method of the selective emitter monocrystalline PERC battery of tunnel oxide |
| CN111584685A (en) * | 2020-05-28 | 2020-08-25 | 江西展宇新能科技有限公司 | Novel solar cell and preparation method thereof |
| CN112490325A (en) * | 2020-11-27 | 2021-03-12 | 泰州中来光电科技有限公司 | Preparation method of solar cell |
| CN113224202A (en) * | 2021-03-15 | 2021-08-06 | 浙江爱旭太阳能科技有限公司 | POLO-IBC solar cell and preparation method thereof |
| CN113363354A (en) * | 2021-06-04 | 2021-09-07 | 浙江爱旭太阳能科技有限公司 | Preparation method of P-type back contact crystalline silicon solar cell |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113948611A (en) | 2022-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113948611B (en) | P-type IBC battery, preparation method thereof, assembly and photovoltaic system | |
| CN115312633B (en) | Mask-layer-free combined passivation back contact battery and preparation method thereof | |
| JP4767110B2 (en) | Solar cell and method for manufacturing solar cell | |
| JP5058184B2 (en) | Method for manufacturing photovoltaic device | |
| CN110880541A (en) | Novel-structure n-type crystalline silicon PERT double-sided battery and preparation method thereof | |
| WO2010064303A1 (en) | Method for manufacturing solar battery cell | |
| NL2023003B1 (en) | Method for preparing full back-contact electrode cell with efficient light trapping and selective doping | |
| CN102403369A (en) | Passivation dielectric film for solar cell | |
| CN111816727A (en) | Interdigital back contact heterojunction solar cell based on LPCVD (low pressure chemical vapor deposition) high-efficiency amorphous silicon doping technology | |
| CN110571302A (en) | preparation method of N-type crystalline silicon battery | |
| CN112820793A (en) | Solar cell and preparation method thereof | |
| JP5826380B2 (en) | SOLAR CELL, SOLAR CELL MANUFACTURING METHOD, SOLAR CELL MODULE | |
| WO2024066207A1 (en) | New solar cell and fabrication method therefor | |
| CN114497288A (en) | Manufacturing method of heterojunction solar cell with grid line embedded into selective heavily doped region | |
| CN111477695A (en) | Solar cell with electrode-free front surface and preparation method thereof | |
| CN116741877A (en) | TBC battery preparation method and TBC battery | |
| CN115274913B (en) | Preparation method of IBC solar cell with passivation contact structure, and cell, component and system | |
| CN114220882A (en) | Preparation method of solar crystalline silicon cell and solar crystalline silicon cell | |
| CN110571303A (en) | Preparation method of P-type crystalline silicon cell | |
| CN110534614B (en) | Preparation method of P-type crystalline silicon cell | |
| CN116130558B (en) | Preparation method of novel all-back electrode passivation contact battery and product thereof | |
| CN115101621B (en) | P-topcon battery and preparation method thereof | |
| CN115312627A (en) | Preparation method of solar cell and solar cell | |
| CN114864740A (en) | Double-sided local passivation contact solar cell and manufacturing method thereof | |
| CN113659033A (en) | Preparation method of P-type back contact solar cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |