CN111864008A - Preparation method of P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell - Google Patents
Preparation method of P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell Download PDFInfo
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- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 15
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
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- 238000007639 printing Methods 0.000 claims abstract description 25
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- 238000000034 method Methods 0.000 claims abstract description 21
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- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
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- 238000007650 screen-printing Methods 0.000 claims abstract description 9
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
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Abstract
The invention relates to a preparation method of a P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell, which comprises the following steps: carrying out double-sided texturing to form a textured structure; performing double-sided oxidation and intrinsic polysilicon, and then performing phosphorus diffusion to form a tunneling oxidation passivation layer; forming a mask layer on the back by using a high-temperature oxidation process; carrying out laser film opening and cleaning on the back surface, and removing intrinsic polycrystalline silicon on the front surface by using an alkali polishing process; b slurry printing is carried out on the back surface, and a P + layer is formed after drying; doping the front surface with a boron source to form a P + layer; removing the BSG and PSG mask layer by using HF; removing the redundant polysilicon layer in an alkali polishing mode; forming a passivation layer by using double-sided aluminum oxide, front silicon oxynitride and back silicon nitride; screen printing to form P + finger and N + finger; and (5) finishing the manufacturing of the battery piece by a low-temperature sintering process. According to the invention, the structure of the IBC battery is introduced on the basis of the existing PERC technology, and the structure of intrinsic amorphous silicon is introduced at the same time, so that VOC and ISC can be effectively improved, and further, the efficiency is greatly improved.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell.
Background
Ibc (indirect back contact) cells appeared in the 70 s of the 20 th century, were the first back junction cells studied, and were primarily used in light-concentrating systems. The cell is made of an n-type substrate material, and the front surface and the rear surface of the cell are covered with a layer of thermal oxidation film to reduce surface recombination. And (3) respectively carrying out partial diffusion of phosphorus and boron on the back surface of the cell by utilizing a photoetching technology to form P regions and N regions which are arranged in an interdigital way, and P + regions and N + regions which are positioned above the P regions and the N regions. The P + and N + regions formed by re-expansion can effectively eliminate the voltage saturation effect under the condition of high light concentration. In addition, the coverage area of the P + and N + region contact electrodes almost reaches 1/2 of the back surface, greatly reducing the series resistance. But the IBC heterojunction structure for P-type materials is still blank.
PERC (passivated Emitter and reader cell), the technology of passivated Emitter and back cell, was first proposed by Australian scientist Martin Green in 1983 and is now becoming the conventional technology of the next generation of solar cells. Adopt Al2O3 membrane to carry out the passivation to the back surface, can effectually reduce the back surface and compound, improve open circuit voltage, increase the back surface reflection, improve short-circuit current to improve battery efficiency. The PERC battery is the biggest difference from the conventional battery in the passivation of a back surface dielectric film and the adoption of local metal contact, thereby greatly reducing the speed of surface recombination and simultaneously improving the light reflection of the back surface. The current is conducted by performing aluminum oxide passivation on the back surface and utilizing a back surface slotting technology. And finally, completing the preparation of the battery. Its technique has the following disadvantages: 1. the battery has a simpler structure, and if the efficiency needs to be improved continuously, the existing equipment has no too large space; 2. LID light induced degradation is still severe.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method for preparing the P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell introduces the structure of the IBC cell and the structure of intrinsic amorphous silicon on the basis of the existing PERC technology, so that VOC and ISC can be effectively improved, and further efficiency is greatly improved.
The technical scheme adopted by the invention is as follows: a preparation method of a P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell comprises the following steps:
A. carrying out double-sided texturing to form a textured structure;
B. performing double-sided oxidation and intrinsic polysilicon, and then performing phosphorus diffusion to form a tunneling oxidation passivation layer;
C. forming a mask layer on the back by using a high-temperature oxidation process;
D. carrying out laser film opening and cleaning on the back surface, and removing intrinsic polycrystalline silicon on the front surface by using an alkali polishing process;
E. b slurry printing is carried out on the back surface, and a P + layer is formed after drying;
F. doping the front surface with a boron source to form a P + layer;
G. removing the BSG and PSG mask layer by using HF; removing the redundant polysilicon layer in an alkali polishing mode;
H. forming a passivation layer by using double-sided aluminum oxide, front silicon oxynitride and back silicon nitride;
I. screen printing to form P + finger and N + finger;
J. and (5) finishing the manufacturing of the battery piece by a low-temperature sintering process.
Furthermore, the tunneling oxidation passivation layer is prepared by maintaining the double-sided oxidation temperature at 500-600 ℃ in a tubular diffusion furnace, wherein the temperature of N2: o2 ═ 2: 1-3: 1, the time is about 10-20min, and the thickness is 2-3 nm.
Still further, the intrinsic polysilicon of the present invention is formed by LPCVD equipment, SiH 4: the flow ratio of N2 is 1: 2-1: 3; the time is 15-30min, and the thickness is 80-150 nm; and then carrying out high-temperature annealing, wherein the temperature is maintained at 800-900 ℃, and the temperature is maintained at LN 2: n2 flow rate 1: 2-1: 3; at low pressure for 20-40 min; the sheet resistance is controlled to be 20-40 omega/□.
And further, in the step E, the back printing is carried out by utilizing a boron paste printing mode, the pattern is consistent with the laser grooving pattern, and the sheet resistance is controlled at 40-80ohm by advancing at the high temperature of 900-1000 ℃ for 40-80 min.
In step H, performing double-sided passivation on aluminum oxide by using an atomic layer deposition technology, wherein the thickness is controlled to be 3-10 nm; then the front surface is plated with silicon oxynitride with the thickness of 75-85nm and the refractive index of 1.9-2.1, and the back surface is plated with silicon nitride with the thickness of 80-90nm and the refractive index of 2-2.2.
In step I, fine grid lines are printed, P + slurry is printed at the grooved positions, and N + slurry is printed at the non-grooved positions; and (3) respectively connecting the N + region and the P + region by the main grid line printing in an insulating glue mode, alternately printing to form a loop, and finally completing the battery manufacturing at the low-temperature sintering process temperature of 400-600 ℃.
The invention has the beneficial effects that:
1. the existing PERC equipment is fully utilized, and the investment amount is less;
2. the added equipment such as B expanding equipment, B paste printing equipment, tunnel oxidation passivation layer equipment and the like are mature in manufacturing;
3. compared with PERC, the efficiency of the structure can be improved by 1.5-2.5%, and the efficiency improvement space is larger.
Drawings
FIG. 1 is a schematic diagram of a cell according to the present invention;
FIGS. 2-10 are exploded views of the cell structure at process steps of the invention;
in the figure: 1. p-type high minority carrier lifetime silicon wafer; 2. tunneling an ultrathin oxide layer; 3. an N + layer formed by intrinsic polysilicon; 4. b, printing the boron paste to form a P + layer; 5. doping boron to form a front P + layer; 6. a double-sided aluminum oxide passivation layer; 7. a front-side silicon oxynitride passivation layer; 8. a back SiNx passivation layer; 9. n + finger obtained by means of screen printing; 10. p + finger obtained by means of screen printing.
Detailed Description
The invention will now be described in further detail with reference to the drawings and preferred embodiments. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
The all-back-electrode contact crystalline silicon photovoltaic cell (IBC cell) is a technology that metal contacts of a positive electrode and a negative electrode are moved to the back of a cell piece, so that the front of the cell piece facing the sun is all black, and metal wires on the front of most photovoltaic cells cannot be seen completely. The power generation device not only brings more effective power generation area for users, but also is beneficial to improving the power generation efficiency, and is more attractive in appearance.
The invention fully utilizes the existing PERC equipment to manufacture the P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell, as shown in figure 1, the P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell mainly comprises the following structures:
1. p-type high minority carrier lifetime silicon wafer;
2. the tunneling ultrathin oxide layer can enable multi-electron tunneling to enter the polycrystalline silicon layer, simultaneously prevent minority hole recombination, and further enable electrons to be transversely transmitted in the polycrystalline silicon layer and collected by metal, so that metal contact recombination current is greatly reduced, and open-circuit voltage and short-circuit current of the battery are improved;
3. forming an N + layer by intrinsic polycrystalline silicon, growing intrinsic amorphous silicon on the thin oxide layer, and forming an intrinsic polycrystalline silicon structure in a phosphorus-doped high-temperature annealing mode, wherein the intrinsic polycrystalline silicon structure has good passivation characteristics;
4. the boron paste is printed to form a P + layer, a lower sheet resistance can be formed in a printing mode and is easily obtained in a mask mode, and the lower sheet resistance is beneficial to contact of electrodes;
5. the front P + layer is formed by doping boron, and a higher sheet resistance can be obtained by using a boron diffusion mode, so that the open-circuit Voltage (VOC) can be improved;
6. the double-sided aluminum oxide passivation layer has an effective passivation effect on the front surface and the back surface of the silicon substrate;
7. the front silicon oxynitride (SiONx) passivation layer can improve the reflectivity, thereby effectively improving the short-circuit current (ISC);
8. A back SiNx passivation layer;
9. n + finger, obtained by means of screen printing;
10. p + finger, also obtained by means of screen printing.
The manufacturing process mainly comprises the following steps: A. carrying out double-sided texturing to form a smaller textured structure; B. performing double-sided oxidation and intrinsic polycrystalline silicon, and then performing P-diffusion to form a tunneling oxidation passivation layer; C. forming a mask layer on the back by using a high-temperature oxidation process, and avoiding the influence of the high-temperature advance of the front-side B diffusion on the structure of polycrystalline silicon (Poly); D. carrying out laser film opening and cleaning on the back surface, and removing intrinsic polycrystalline silicon on the front surface by using an alkali polishing process; E. b slurry printing is carried out on the back surface, and a P + layer is formed by drying; F. doping the front surface by adopting a B source to form a P + layer; G. removing the BSG and PSG mask layer by using HF; removing the redundant polysilicon layer in an alkali polishing mode; H. forming a passivation layer by using double-sided aluminum oxide, front silicon oxynitride and back silicon nitride; I. screen printing to form P + and N + finger; J. and (5) finishing the manufacturing of the battery piece by a low-temperature sintering process.
The advantages are mainly as follows: 1. the front side has no grid line structure, so that the ISC is greatly improved; 2. the front surface adopts a silicon oxynitride process, so that the requirements of a black component are met; 3. the back N + layer is of a tunneling oxidation polycrystalline silicon structure, so that VOC is improved; 4. the back P + layer is printed by the B paste, so that the P + layer is formed more accurately.
The specific battery manufacturing steps are as follows:
the P-type silicon chip with high minority carrier lifetime is adopted, the resistivity is 1-3 omega-cm, and the minority carrier lifetime is more than 10 ms.
1) Double-sided texturing-polishing in a groove type machine to a thickness of about 5-7 μm; KOH and additives are added in a ratio of 6:1 to 10:1, preferably 7:1 and 9:1, and the mixture is rapidly subjected to texturing at a temperature of 75 to 85 ℃, preferably 80 ℃ for about 6 to 7 minutes. The thinning amount is controlled to be 0.35-0.45g, preferably about 0.42 g; as shown in FIG. 2;
2) tunneling oxidation-in a tubular diffusion furnace, the temperature of double-sided oxidation is maintained at 500 ℃ and 600 ℃, and N2 (nitrogen gas): o2 (oxygen) ═ 2: 1-3: 1 (2.5: 1), time about 10-20min (15min), thickness about 2-3 nm; as shown in FIG. 3;
3) intrinsic polysilicon — with LPCVD equipment, SiH4 (silane): the flow ratio of N2 is 1: 2-1: 3; the time is about 15-30min, and the thickness is controlled to be 80-150 nm; and then carrying out high-temperature annealing, wherein the temperature is maintained at 800-900 ℃, and the temperature is maintained at LN 2: n2 flow rate 1: 2-1: 3, preferably 1: 2.5; under low pressure atmosphere, the time is about 20-40min, preferably about 25 min; the sheet resistance is controlled to be 20-40 omega/□; as shown in FIG. 4;
4) oxidizing a mask layer, namely adopting high temperature 900-1000O2 flow 2000-3000slm for about 40-60min to form a thick oxide layer as a barrier layer on the back surface; as shown in the black area of fig. 5;
5) Laser grooving on the back, namely performing laser grooving on the back by using a PS (picosecond) laser, wherein the grooving depth is 3-5 μm, the preferable use is 3 μm, the width is 40-70 μm, the test is preferably 45 μm, and the number of the grooves is 96-110, and is conventionally 104. As shown in FIG. 6;
6) back P + layer-back printing is carried out by B paste printing, the pattern of the back P + layer is consistent with that of the laser grooving pattern, the high temperature is used for 900-1000 ℃ for 40-80min, preferably 950 ℃ for 60min, the sheet resistance is controlled at 40-80ohm, and the existing sheet resistance is 50 ohm; as shown in FIG. 7;
7) removing borosilicate glass (BSG), phosphosilicate glass (PSG) and front polysilicon (Poly) on the front and back surfaces, removing the front PSG and the BSG on one side by using hydrofluoric acid (HF) with the concentration of 5%, then performing Poly removal by using an alkali polishing process potassium hydroxide (KOH) polishing additive (2: 1-4: 1, preferably 3: 1), maintaining the temperature at 75-85 ℃, preferably 80 ℃, for about 5-10min, preferably for 7min, and finally performing HF cleaning on the front and back PSG. As shown in FIG. 8;
8) front-side P + layer — doped with a B source, boron trichloride (BCl3) O2 ═ 2: 3-3: 4, preferably using 2:3.5, and controlling the high-temperature diffusion time to be 20-30min, preferably 22min, and the sheet resistance to be 160-200ohm, preferably 180 ohm; as in FIG. 9;
9) Front and back passivation layers-aluminum oxide (AlOx) is passivated on both sides by utilizing an Atomic Layer Deposition (ALD) technology, and the thickness is controlled to be 3-10nm, preferably 7 nm; then plating silicon oxynitride on the front surface, wherein the thickness is about 75-85nm, preferably 82nm, the refractive index is 1.9-2.1, and the test is preferably 2.0; back-side silicon nitride plating with a thickness of about 80-90nm, preferably tentatively 85nm, and a refractive index of 2-2.2, preferably 2.1; as shown in FIG. 10;
10) screen printing, namely printing a fine grid, printing P + slurry at a groove, and printing N + slurry at a non-groove; the main grid line printing respectively connects the N + region and the P + region in an insulating glue mode, and the circuits are formed by alternative printing. Finally, the finished product is manufactured by a low-temperature sintering process at the temperature of 400-600 ℃, and the use temperature is usually 500 ℃, as shown in figure 1.
While particular embodiments of the present invention have been described in the foregoing specification, the various illustrations do not limit the spirit of the invention, and one of ordinary skill in the art, after reading the description, can make modifications and alterations to the particular embodiments described above without departing from the spirit and scope of the invention.
Claims (6)
1. A preparation method of a P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell is characterized by comprising the following steps: the method comprises the following steps:
A. Carrying out double-sided texturing to form a textured structure;
B. performing double-sided oxidation and intrinsic polysilicon, and then performing phosphorus diffusion to form a tunneling oxidation passivation layer;
C. forming a mask layer on the back by using a high-temperature oxidation process;
D. carrying out laser film opening and cleaning on the back surface, and removing intrinsic polycrystalline silicon on the front surface by using an alkali polishing process;
E. b slurry printing is carried out on the back surface, and a P + layer is formed after drying;
F. doping the front surface with a boron source to form a P + layer;
G. removing the BSG and PSG mask layer by using HF; removing the redundant polysilicon layer in an alkali polishing mode;
H. forming a passivation layer by using double-sided aluminum oxide, front silicon oxynitride and back silicon nitride;
I. screen printing to form P + finger and N + finger;
J. and (5) finishing the manufacturing of the battery piece by a low-temperature sintering process.
2. The method for preparing the P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell of claim 1, wherein: the tunneling oxidation passivation layer is formed by maintaining the double-sided oxidation temperature at 500-600 ℃ in a tubular diffusion furnace, wherein the temperature of N2: o2 ═ 2: 1-3: 1, the time is about 10-20min, and the thickness is 2-3 nm.
3. The method for preparing the P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell of claim 1, wherein: the intrinsic polysilicon is prepared by LPCVD equipment, SiH 4: the flow ratio of N2 is 1: 2-1: 3; the time is 15-30min, and the thickness is 80-150 nm; and then carrying out high-temperature annealing, wherein the temperature is maintained at 800-900 ℃, and the temperature is maintained at LN 2: n2 flow rate 1: 2-1: 3; at low pressure for 20-40 min; the sheet resistance is controlled to be 20-40 omega/□.
4. The method for preparing the P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell of claim 1, wherein: and E, performing back printing by using a boron paste printing mode, wherein the pattern is consistent with the laser grooving pattern, and the sheet resistance is controlled at 40-80ohm by advancing at the high temperature of 900 ℃ for 1000 ℃ for 40-80 min.
5. The method for preparing the P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell of claim 1, wherein: in the step H, performing double-sided passivation on aluminum oxide by using an atomic layer deposition technology, wherein the thickness is controlled to be 3-10 nm; then the front surface is plated with silicon oxynitride with the thickness of 75-85nm and the refractive index of 1.9-2.1, and the back surface is plated with silicon nitride with the thickness of 80-90nm and the refractive index of 2-2.2.
6. The method for preparing the P-type heterojunction full back electrode contact crystalline silicon photovoltaic cell of claim 1, wherein: in the step I, printing a fine grid line, printing P + slurry at a slotted position, and printing N + slurry at a non-slotted position; and (3) respectively connecting the N + region and the P + region by the main grid line printing in an insulating glue mode, alternately printing to form a loop, and finally completing the battery manufacturing at the low-temperature sintering process temperature of 400-600 ℃.
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