CN114373807A - Passivation structure of crystalline silicon battery and preparation method thereof - Google Patents

Passivation structure of crystalline silicon battery and preparation method thereof Download PDF

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CN114373807A
CN114373807A CN202111419080.0A CN202111419080A CN114373807A CN 114373807 A CN114373807 A CN 114373807A CN 202111419080 A CN202111419080 A CN 202111419080A CN 114373807 A CN114373807 A CN 114373807A
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back side
phosphorus
deposition chamber
silicon
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朱英明
曹育娟
孟祥国
胡磊振
邱凯坤
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Jiangsu Clelo Material Technology Co ltd
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Abstract

The application discloses a passivation structure of a crystalline silicon battery, which relates to the technical field of crystalline silicon batteries and comprises a silicon wafer, wherein the back side surface of the silicon wafer is polished, a tunneling oxide layer is prepared on one side of the polished silicon wafer, a first I-Si/H intrinsic layer is prepared on the back side surface of the tunneling oxide layer, a first phosphorus-containing polycrystalline silicon layer is prepared on the back side surface of the I-Si/H intrinsic layer, and an antireflection film layer is prepared on the back side surface of the first phosphorus-containing polycrystalline silicon layer. By adding the first intrinsic layer between the tunneling oxide layer and the first phosphorus-containing polycrystalline silicon layer, the passivation effect of the back side surface of the crystalline silicon battery can be improved, and the comprehensive performance of the crystalline silicon battery is improved.

Description

Passivation structure of crystalline silicon battery and preparation method thereof
Technical Field
The application belongs to the technical field of crystalline silicon batteries, and particularly relates to a passivation structure of a crystalline silicon battery and a preparation method thereof.
Background
In the solar cell, a tunneling oxide layer is prepared on the back surface of the cell, a phosphorus-doped polycrystalline silicon layer film is formed to form a passivation contact structure, surface state defects on the back side surface of the cell can be compensated to a certain extent, minority carriers are blocked from carrying out hole recombination, and therefore the comprehensive performance of the cell is improved to a certain extent.
Although the addition of the tunnel oxide layer reduces the number of dangling bonds to a certain extent, the surface defects of the back side of the N-type substrate and the surface defects of the phosphorus-doped phosphorus-containing polycrystalline silicon layer in contact with the N-type substrate cannot be completely passivated, so that a certain space for improvement exists.
Disclosure of Invention
In order to further optimize the passivation structure of the back surface of the crystalline silicon battery, the application provides the passivation structure of the crystalline silicon battery and a preparation method thereof.
In a first aspect, the present application provides a passivation structure of a crystalline silicon cell, which adopts the following technical scheme:
a passivation structure of a crystalline silicon battery comprises a silicon wafer, wherein the back side surface of the silicon wafer is polished, a tunneling oxide layer is prepared on one side of the polished silicon wafer, a first I-Si/H intrinsic layer is prepared on the back side surface of the tunneling oxide layer, a first phosphorus-containing polycrystalline silicon layer is prepared on the back side surface of the I-Si/H intrinsic layer, and an antireflection film layer is prepared on the back side surface of the first phosphorus-containing polycrystalline silicon layer.
By adopting the technical scheme, the first I-Si/H intrinsic layer is introduced between the tunneling oxide layer and the first phosphorus-containing polycrystalline silicon layer, and because H bonds exist in the intrinsic layer and can be combined with only one chemical bond. Therefore, the H key is combined with the hanging key on the back side surface of the crystalline silicon battery, the surface state defect on the back side surface of the crystalline silicon battery is further made up, and the comprehensive performance of the crystalline silicon battery is optimized.
Optionally, a second I-Si, i.e., an H intrinsic layer, and a second phosphorus-containing polysilicon layer are sequentially prepared on the back side of the first phosphorus-containing polysilicon layer, and the antireflection film layer is disposed on the back side of the second phosphorus-containing polysilicon layer.
By adopting the technical scheme, the second I-Si, H intrinsic layer and the second phosphorus-containing polycrystalline silicon layer are further introduced on the back side surface of the crystalline silicon cell, and the diffusion speed of phosphorus atoms in the polycrystalline silicon layer is low, while the diffusion speed of phosphorus atoms in the intrinsic layer is high. On the basis that the thickness of the film structure on the back side surface of the crystalline silicon cell is the same, the intrinsic layer replaces a polycrystalline silicon layer with a certain thickness, so that the diffusion speed of phosphorus atoms on the back side surface of the crystalline silicon cell can be increased. On one hand, the time required by the crystalline silicon battery in the preparation process is shortened; on the other hand, the diffusion speed and the uniformity of the dispersion of phosphorus atoms on the back side of the crystalline silicon cell are also optimized.
Optionally, the antireflection film is a silicon nitride antireflection film, a film thickness of the silicon nitride antireflection film is 50-90 μm, and a refractive index of the silicon nitride antireflection film is 1.8-2.4.
Optionally, the resistivity range of the silicon wafer is 1-7 omega cm, the minority carrier lifetime is more than or equal to 1000 mus, and the interstitial oxygen content is less than or equal to 8E +17at/cm 3.
Through adopting above-mentioned technical scheme, through selecting for use silicon nitride antireflection coating and the silicon chip of reasonable parameter, can be limited the comprehensive properties that promotes crystal silicon battery, optimize the crystal silicon battery to the utilization ratio of light energy to and accelerate the motion transmission of electron in the mirror cabinet battery.
In a second aspect, the application provides a method for preparing the crystalline silicon cell passivation structure, which adopts the following technical scheme:
which comprises the following steps:
s1, cleaning a silicon wafer by using a cleaning agent, and then preparing a polishing agent to perform polishing treatment on the back side surface of the silicon wafer in a groove type machine;
s2, placing the silicon wafer obtained by the processing of S1 in a deposition chamber, pumping the deposition chamber to vacuum, controlling the temperature of the deposition chamber at 580-630 ℃ by a heating furnace, continuously introducing 2-4L of oxygen into the deposition chamber at a constant flow rate for 25-35min, reducing the temperature in the deposition chamber to 100 ℃, standing for 20min, and forming a tunneling oxide layer on the back side surface of the silicon wafer;
s3, raising the temperature in the deposition chamber to 600-650 ℃, and introducing SiH into the deposition chamber by 500-650sccm4Continuing for 2-8min, and forming a first I-Si-H intrinsic layer on the back side surface of the tunneling oxide layer;
s4, introducing phosphorus oxychloride into the deposition chamber by using the flow control method of 800sccm and introducing oxygen into the deposition chamber by using the flow control method of 500sccm for 5-10min so as to form a first phosphorus-containing polycrystalline silicon layer on the back side surface of the first I-Si-H intrinsic layer;
s5, repeating S3-S4 to form a second I-Si, H intrinsic layer and a second phosphorus-containing polycrystalline silicon layer on the back side surface of the first phosphorus-containing polycrystalline silicon layer in sequence, and heating the deposition chamber to 700-750 ℃ for 30min to obtain a crude crystalline silicon battery with a passivation structure.
By adopting the technical scheme, when the crystalline silicon battery passivation structure is prepared, the silicon wafer is cleaned by the cleaning agent firstly, so that the cleaning degree of the silicon wafer is ensured, and impurities are prevented from entering the silicon wafer in the subsequent preparation process. The polishing treatment of the back side surface of the silicon wafer is carried out by a polishing agent and a groove type machine, so that the back side surface of the silicon wafer has better lattice integrity, flatness and cleanness, and the subsequent passivation processing of the silicon wafer is facilitated. And then depositing the tunneling oxide layer, the first intrinsic layer, the first polycrystalline silicon layer, the second intrinsic layer and the second polycrystalline silicon layer in a deposition chamber. And after the deposition of the tunneling oxide layer, the first intrinsic layer, the first polysilicon layer, the second intrinsic layer and the second polysilicon layer is finished, the temperature of the deposition chamber is raised to 700-750 ℃ so that phosphorus elements can be diffused and rearranged, and the phosphorus elements can be rapidly and uniformly distributed in the first intrinsic layer, the first polysilicon layer, the second intrinsic layer and the second polysilicon layer.
Optionally, the cleaning agent is prepared from the following components in parts by mass:
5-15 parts of potassium hydroxide;
10-15 parts of sodium silicate;
1-2 parts of potassium hydrogen phosphate;
10-20 parts of dodecyl polyoxyethylene ether;
300 portions of deionized water and 500 portions of deionized water.
By adopting the technical scheme, the potassium hydroxide is added into the cleaning agent, and hydroxide ions provided by the potassium hydroxide can contact with and saponify the oil stains on the surface of the silicon wafer. The addition of the sodium silicate can buffer the alkalinity of the potassium hydroxide on one hand and avoid the damage to the surface of the silicon wafer caused by the over-strong alkalinity; on the other hand, the sodium silicate can also play a role in washing aid in the cleaning agent. And potassium hydrogen phosphate is added, so that the potassium hydrogen phosphate can be compounded with sodium silicate, and the uniformity of the dispersion of the sodium silicate in the cleaning agent is improved. The dodecyl polyoxyethylene ether is added to play a role of a surfactant, so that the cleaning effect of the silicon wafer is improved.
Optionally, the polishing agent is prepared from the following components in parts by mass:
1-3 parts of sodium hydroxide;
1-3 parts of fatty acid methyl ester polyoxyethylene ether;
2-7 parts of polyoxyethylene ether;
1-3 parts of vinyl bis stearamide;
1-3 parts of dodecyl polyglycoside;
40-50 parts of deionized water.
By adopting the technical scheme, the chips generated in the silicon wafer polishing process can be rapidly removed by adding sodium hydroxide and nonionic surfactants such as fatty acid methyl ester polyoxyethylene ether, polyoxyethylene ether and vinyl bis stearamide, and the polishing effect of the surface of the silicon wafer is prevented from being influenced by the friction between the chips and the silicon wafer. In addition, the dodecyl polyglycoside can generate a compounding effect with the nonionic surfactant, and the polishing effect is improved.
In summary, the present application includes at least one of the following benefits:
1. by adding the first intrinsic layer between the tunneling oxide layer and the first phosphorus-containing polycrystalline silicon layer, the passivation effect of the back side surface of the crystalline silicon battery can be improved, and the comprehensive performance of the crystalline silicon battery is improved.
2. The second intrinsic layer and the second phosphorus-containing polycrystalline silicon layer are further added, so that the diffusion speed and the dispersion uniformity of phosphorus on the back side surface of the crystalline silicon battery can be improved, and the comprehensive performance of the crystalline silicon battery is further improved.
3. The silicon wafer is treated by the specially-made cleaning agent and the special polishing agent, so that the cleanliness of the back side surface of the silicon wafer is improved, and the subsequent treatment of the silicon wafer is facilitated.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present application.
Preparation examples 1 to 2
Preparation example 1: the preparation example provides a cleaning agent, which is prepared by stirring and dissolving the following components in parts by mass:
potassium hydroxide: sodium silicate: potassium hydrogen phosphate: dodecyl polyoxyethylene ether: deionized water 10:12:1.5:15: 400.
Preparation example 2: the preparation example provides a polishing agent, which is prepared by stirring and dissolving the following components in percentage by mass:
sodium hydroxide: fatty acid methyl ester polyoxyethylene ether: polyoxyethylene ether: vinyl bis stearamide: dodecyl polyglycoside: deionized water 2: 2: 5: 2: 2: 50.
examples 1 to 6
Example 1: the embodiment provides a passivation structure of a crystalline silicon cell, which is prepared by the following steps:
a1-1, cleaning a silicon wafer for 30min by an RCA cleaning method from an N-type silicon wafer with the resistivity of 3 omega-cm, the minority carrier lifetime of 1000 mus and the interstitial oxygen content of 8E +17at/cm3, then polishing the back side surface of the silicon wafer in a groove type polishing agent by polycrystalline diamond polishing solution, controlling the polishing temperature at 80 ℃, the polishing time at 10min and the reduction thickness within 10 mu m;
a1-2, placing the silicon wafer prepared in the step A1-1 in a deposition chamber, and performing nitrogen filling and vacuum pumping in the deposition chamber for five times. And after the deposition chamber is vacuumized for the last time, controlling the temperature in the deposition chamber to rise to 600 ℃ through a heating furnace, and introducing 3L of oxygen into the deposition chamber at a constant flow rate within 30 min. And finally, reducing the temperature in the deposition chamber to 100 ℃ at the speed of 30 ℃/min, and standing for 20min to form a tunneling oxide layer on the back side of the silicon wafer.
A1-3, adjusting the temperature in the deposition chamber to 620 ℃ by a heating furnace, and introducing SiH into the deposition chamber at 580sccm4Continuing for 5min to form a first I-Si-H intrinsic layer on the back side surface of the tunneling oxide layer;
a1-4, then introducing phosphorus oxychloride into the deposition chamber at 600sccm, introducing oxygen into the deposition chamber at 400sccnm for 7min to form a first phosphorus-containing polysilicon layer on the back side of the first I-Si: H intrinsic layer, and then raising the temperature in the deposition chamber to 720 ℃ at 20 ℃/min for 30min to fully diffuse phosphorus elements in the first I-Si: H intrinsic layer and the first phosphorus-containing polysilicon layer.
A1-5, preparing a silicon nitride antireflection film on the back side of the first phosphorus-containing polycrystalline silicon layer, wherein the film thickness of the silicon nitride antireflection film is set to be 60 μm, and the reflectivity is 2.0.
Example 2: the difference between this example and example 1 is that the cleaning agent prepared in preparation example 1 was used to clean silicon wafers.
Example 3: this example is different from example 2 in that the polishing machine prepared in preparation example 2 was used for polishing silicon wafers.
Example 4: the embodiment provides a passivation structure of a crystalline silicon cell, which is prepared by the following steps:
a2-1, taking an N-type silicon wafer with the resistivity of 3 omega-cm, the minority carrier lifetime of 1000 mus and the interstitial oxygen content of 8E +17at/cm3, cleaning the silicon wafer for 30min by using the cleaning agent prepared in the preparation example 1, and then polishing the back side surface of the silicon wafer in a groove-type polishing agent by using the polishing solution prepared in the preparation example 2, wherein the polishing temperature is controlled at 80 ℃, the polishing time is 10min, and the reduction thickness is controlled within 10 mu m;
a2-2, placing the silicon wafer prepared in the step A2-1 in a deposition chamber, and performing nitrogen filling and vacuum pumping in the deposition chamber for five times. And after the deposition chamber is vacuumized for the last time, controlling the temperature in the deposition chamber to rise to 600 ℃ through a heating furnace, and introducing 3L of oxygen into the deposition chamber at a constant flow rate within 30 min. And finally, reducing the temperature in the deposition chamber to 100 ℃ at the speed of 30 ℃/min, and standing for 20min to form a tunneling oxide layer on the back side of the silicon wafer.
A2-3, adjusting the temperature in the deposition chamber to 620 ℃ by a heating furnace, and introducing SiH into the deposition chamber at 580sccm4Continuing for 5min to form a first I-Si-H intrinsic layer on the back side surface of the tunneling oxide layer;
a2-4, then introducing phosphorus oxychloride into the deposition chamber at 600sccm, introducing oxygen into the deposition chamber at 400sccnm for 7min, so that a first phosphorus-containing polysilicon layer is formed on the back side of the first I-Si: H intrinsic layer;
a2-5, repeating A2-3 to A2-4 once, so that a second I-Si: H intrinsic layer and a second phosphorus-containing polysilicon layer are sequentially formed on the back side of the first phosphorus-containing polysilicon layer. And raising the temperature in the deposition chamber to 720 ℃ at a speed of 20 ℃/min for 30min, so that phosphorus is fully diffused in the first I-Si: H intrinsic layer, the second I-Si: H intrinsic layer, the first phosphorus-containing polycrystalline silicon layer and the second phosphorus-containing polycrystalline silicon layer, and the passivation structure of the crystalline silicon cell is obtained.
Example 5: the preparation example provides a passivation structure of a crystalline silicon battery, which is prepared by the following steps:
a3-1, taking an N-type silicon wafer with the resistivity of 3 omega-cm, the minority carrier lifetime of 1000 mus and the interstitial oxygen content of 8E +17at/cm3, cleaning the silicon wafer for 30min by using the cleaning agent prepared in the preparation example 1, and then polishing the back side surface of the silicon wafer in a groove-type polishing agent by using the polishing solution prepared in the preparation example 2, wherein the polishing temperature is controlled at 80 ℃, the polishing time is 10min, and the reduction thickness is controlled within 10 mu m;
a3-2, placing the silicon wafer prepared in the step A3-1 in a deposition chamber, and performing nitrogen filling and vacuum pumping in the deposition chamber for five times. After the deposition chamber was evacuated for the last time, the temperature in the deposition chamber was controlled by a heating furnace to rise to 580 ℃ and 2L of oxygen was introduced into the deposition chamber at a constant flow rate over 25 min. And finally, reducing the temperature in the deposition chamber to 100 ℃ at the speed of 30 ℃/min, and standing for 20min to form a tunneling oxide layer on the back side of the silicon wafer.
A3-3, adjusting the temperature in the deposition chamber to 600 ℃ by a heating furnace, and introducing SiH into the deposition chamber at 650sccm4Continuing for 2min to form a first I-Si (H) intrinsic layer on the back side surface of the tunneling oxide layer;
a3-4, then introducing phosphorus oxychloride into the deposition chamber at 450sccm, introducing oxygen into the deposition chamber at 300sccnm for 10min, so that a first phosphorus-containing polysilicon layer is formed on the back side of the first I-Si: H intrinsic layer;
a3-5, repeating A3-3 to A3-4 once, so that a second I-Si: H intrinsic layer and a second phosphorus-containing polysilicon layer are sequentially formed on the back side of the first phosphorus-containing polysilicon layer. And raising the temperature in the deposition chamber to 750 ℃ at a speed of 20 ℃/min for 30min, so that phosphorus is fully diffused in the first I-Si: H intrinsic layer, the second I-Si: H intrinsic layer, the first phosphorus-containing polycrystalline silicon layer and the second phosphorus-containing polycrystalline silicon layer, and the passivation structure of the crystalline silicon cell is obtained.
Example 6: the embodiment provides a passivation structure of a crystalline silicon cell, which is prepared by the following steps:
a4-1, taking an N-type silicon wafer with the resistivity of 3 omega-cm, the minority carrier lifetime of 1000 mus and the interstitial oxygen content of 8E +17at/cm3, cleaning the silicon wafer for 30min by using the cleaning agent prepared in the preparation example 1, and then polishing the back side surface of the silicon wafer in a groove-type polishing agent by using the polishing solution prepared in the preparation example 2, wherein the polishing temperature is controlled at 80 ℃, the polishing time is 10min, and the reduction thickness is controlled within 10 mu m;
a4-2, placing the silicon wafer prepared in the step A4-1 in a deposition chamber, and performing nitrogen filling and vacuum pumping in the deposition chamber for five times. After the deposition chamber was evacuated for the last time, the temperature in the deposition chamber was controlled by a heating furnace to rise to 630 ℃ and 4L of oxygen was introduced into the deposition chamber at a constant flow rate over 35 min. And finally, reducing the temperature in the deposition chamber to 100 ℃ at the speed of 30 ℃/min, and standing for 20min to form a tunneling oxide layer on the back side of the silicon wafer.
A4-3, adjusting the temperature in the deposition chamber to 650 ℃ by a heating furnace, and introducing SiH into the deposition chamber at 650sccm4Continuing for 2min to form a first I-Si (H) intrinsic layer on the back side surface of the tunneling oxide layer;
a4-4, then introducing phosphorus oxychloride into the deposition chamber at 800sccm, introducing oxygen into the deposition chamber at 300sccnm for 5min, so that a first phosphorus-containing polysilicon layer is formed on the back side of the first I-Si: H intrinsic layer;
a4-5, repeating A4-3 to A4-4 once, so that a second I-Si: H intrinsic layer and a second phosphorus-containing polysilicon layer are sequentially formed on the back side of the first phosphorus-containing polysilicon layer. And raising the temperature in the deposition chamber to 750 ℃ at a speed of 20 ℃/min for 30min, so that phosphorus is fully diffused in the first I-Si: H intrinsic layer, the second I-Si: H intrinsic layer, the first phosphorus-containing polycrystalline silicon layer and the second phosphorus-containing polycrystalline silicon layer, and the passivation structure of the crystalline silicon cell is obtained.
Comparative example 1: the comparative example differs from example 1 in that an intrinsic layer is not provided between the tunnel oxide layer and the polysilicon layer in the passivation structure of the comparative example.
Performance testing of crystalline silicon cells
The above examples and comparative examples were subjected to comprehensive performance tests of a crystalline silicon cell, and the test results are shown in table 1:
TABLE 1 test results of comprehensive properties of crystalline silicon batteries
Figure BDA0003376517100000111
By analyzing the data in table 1, it can be found that the crystal silicon battery treated by the cleaning agent and the polishing agent provided by the application has obvious increase of appearance yield. Meanwhile, the performance parameters are improved to different degrees.
After the intrinsic layer is added between the tunneling oxide layer and the polycrystalline silicon layer, the open-circuit voltage and the short-circuit current of the battery are obviously improved, and the comprehensive performance of the battery is obviously improved.
And a second intrinsic layer and a second polycrystalline silicon layer are further added, so that the diffusion speed and the distribution uniformity of phosphorus in the battery can be improved, and the comprehensive performance of the battery is also improved.
The preferred embodiments of the present application have been described in detail, but the present application is not limited to the details of the foregoing embodiments, and various equivalent changes may be made to the technical solutions of the present application within the technical spirit of the present application, and these equivalent changes are all within the scope of the present application.

Claims (7)

1. A passivation structure of a crystalline silicon battery comprises a silicon wafer and is characterized in that the back side surface of the silicon wafer is polished, a tunneling oxide layer is prepared on one side of the polished silicon wafer, a first I-Si: H intrinsic layer is prepared on the back side surface of the tunneling oxide layer, a first phosphorus-containing polycrystalline silicon layer is prepared on the back side surface of the I-Si: H intrinsic layer, and an antireflection film layer is prepared on the back side surface of the first phosphorus-containing polycrystalline silicon layer.
2. The passivation structure of a crystalline silicon cell of claim 1, wherein a second I-Si: H intrinsic layer and a second phosphorus-containing polysilicon layer are sequentially formed on the back side of the first phosphorus-containing polysilicon layer, and the anti-reflection film layer is disposed on the back side of the second phosphorus-containing polysilicon layer.
3. The passivation structure of a crystalline silicon cell as claimed in claim 1, wherein the anti-reflective film is a silicon nitride anti-reflective film, the film thickness of the silicon nitride anti-reflective film is 50-90 μm, and the refractive index of the silicon nitride anti-reflective film is 1.8-2.4.
4. The passivation structure of the crystalline silicon cell as claimed in claim 1, wherein the silicon wafer has a resistivity range of 1-7 Ω -cm, a minority carrier lifetime of 1000 μ s or more, and an interstitial oxygen content of 8E +17at/cm3 or less.
5. The method for preparing the passivation structure of the crystalline silicon cell as claimed in claim 1, comprising the steps of:
s1, cleaning a silicon wafer by using a cleaning agent, and then preparing a polishing agent to perform polishing treatment on the back side surface of the silicon wafer in a groove type machine;
s2, placing the silicon wafer obtained by the processing of S1 in a deposition chamber, pumping the deposition chamber to vacuum, controlling the temperature of the deposition chamber at 580-630 ℃ by a heating furnace, continuously introducing 2-4L of oxygen into the deposition chamber at a constant flow rate for 25-35min, reducing the temperature in the deposition chamber to 100 ℃, standing for 20min, and forming a tunneling oxide layer on the back side surface of the silicon wafer;
s3, raising the temperature in the deposition chamber to 600-650 ℃, and introducing SiH into the deposition chamber by 500-650sccm4Continuing for 2-8min, and forming a first I-Si-H intrinsic layer on the back side surface of the tunneling oxide layer;
s4, introducing phosphorus oxychloride into the deposition chamber by using the flow control method of 800sccm and introducing oxygen into the deposition chamber by using the flow control method of 500sccm for 5-10min so as to form a first phosphorus-containing polycrystalline silicon layer on the back side surface of the first I-Si-H intrinsic layer;
s5, repeating S3-S4 to form a second I-Si, H intrinsic layer and a second phosphorus-containing polycrystalline silicon layer on the back side surface of the first phosphorus-containing polycrystalline silicon layer in sequence, and heating the deposition chamber to 700-750 ℃ for 30min to obtain a crude crystalline silicon battery with a passivation structure.
6. The method for preparing the passivation structure of the crystalline silicon battery as claimed in claim 3, wherein the cleaning agent comprises the following components in percentage by mass:
5-15 parts of potassium hydroxide;
10-15 parts of sodium silicate;
1-2 parts of potassium hydrogen phosphate;
10-20 parts of dodecyl polyoxyethylene ether;
300 portions of deionized water and 500 portions of deionized water.
7. The method for preparing the passivation structure of the crystalline silicon cell as claimed in claim 4, wherein the polishing agent comprises the following components in percentage by mass:
1-3 parts of sodium hydroxide;
1-3 parts of fatty acid methyl ester polyoxyethylene ether;
2-7 parts of polyoxyethylene ether;
1-3 parts of vinyl bis stearamide;
40-50 parts of deionized water.
CN202111419080.0A 2021-11-26 2021-11-26 Passivation structure of crystalline silicon battery and preparation method thereof Pending CN114373807A (en)

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