CN110739366A - method for repairing PERC solar cell back film laser grooving damage - Google Patents
method for repairing PERC solar cell back film laser grooving damage Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 34
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- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 title claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 138
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 138
- 239000010703 silicon Substances 0.000 claims abstract description 138
- 238000000137 annealing Methods 0.000 claims abstract description 51
- 238000010438 heat treatment Methods 0.000 claims abstract description 40
- 230000004913 activation Effects 0.000 claims abstract description 31
- 230000008439 repair process Effects 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000001816 cooling Methods 0.000 claims description 36
- 238000002161 passivation Methods 0.000 claims description 30
- 230000003647 oxidation Effects 0.000 claims description 25
- 238000007254 oxidation reaction Methods 0.000 claims description 25
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- 238000009792 diffusion process Methods 0.000 claims description 16
- 238000005245 sintering Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 11
- 229910004205 SiNX Inorganic materials 0.000 claims description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 8
- 229910052593 corundum Inorganic materials 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 8
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 3
- 230000006872 improvement Effects 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 230000006798 recombination Effects 0.000 description 6
- 238000005215 recombination Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
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- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
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- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000010583 slow cooling Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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Abstract
The invention discloses a method for repairing laser grooving damage of PERC solar cells, which comprises the steps of placing a silicon wafer into heat treatment equipment after grooving on the back side, wherein the heat treatment equipment comprises a high-temperature activation region and a low-temperature repair region, the silicon wafer is subjected to high-temperature thermal annealing treatment in the high-temperature activation region to increase the overall lattice thermal motion of a silicon substrate, and then is subjected to low-temperature thermal annealing treatment in the low-temperature repair region to recrystallize the silicon substrate.
Description
Technical Field
The invention relates to the field of solar cell manufacturing, in particular to methods for repairing PERC solar cell back film laser grooving damage.
Background
The PERC solar cell is which is the most popular high-efficiency cell in the current market, the back local contact back passivation technology (PERC) enables the recombination loss of the back of the solar cell to be obviously reduced, and the efficiency of the solar cell is greatly improved2O3/SiNxLamination of Al2O3/SiNxThe laminated layer is stable in property, conventional back aluminum paste cannot be etched through, so laser grooving treatment needs to be carried out on the aluminum paste to ensure contact of the aluminum paste and a silicon substrate, however, fixed damage is inevitably caused to the silicon substrate by the laser grooving, and lattice defects are formed on the surface of the silicon substrate due to high temperature generated by laser to cause extra recombination centers, so that the final cell conversion efficiency is reduced , the laser grooving area ratio of the back of the PERC solar cell is 0.5% -3%, and the copied _ Voc loss caused by the laser damage is about 2-5 mV, which is reflected in the solar cell efficiency, and the efficiency loss is 0.1% -0.25%.
The prior art with publication number CN109616556A discloses a method for annealing the back surface of a silicon wafer and making a plated film on the front surface and a method for preparing battery plates, wherein the method comprises performing laser grooving on the back surface after plating the film on the back surface and then performing film plating on the front surface, and repairing the damage generated during laser grooving by using the heating process required by the front surface film plating, which has the advantages that no additional process is required, but the temperature is low because the heat required by the front surface film deposition process is used, the heat treatment parameters cannot be adjusted because the properties of the front surface film are considered, the effect of thermal annealing repair is greatly limited, and simultaneously, the front surface of the battery plate is not plated, and the substrate silicon inevitably directly contacts with a conveyor belt and a grooving table top, so that the problems of scratching and dirt are easily caused.
The prior art with publication number CN105470347A discloses a method for manufacturing PERC cells, which uses an annealing step after depositing aluminum oxide on the back surface and before depositing silicon nitride on the back surface, and the annealing temperature is set to 400-.
Disclosure of Invention
The technical problem to be solved by the invention is to provide methods for repairing the laser grooving damage of the back film of the PERC solar cell, so that the lattice defect can be repaired without adding new equipment, the back recombination rate is reduced, and the photoelectric conversion efficiency is improved.
In order to solve the technical problem, the invention provides methods for repairing the laser grooving damage of the back film of the PERC solar cell, which comprises the following steps:
(1) forming a suede on the front side and the back side of a silicon wafer, wherein the silicon wafer is P-type silicon;
(2) diffusing on the front side of the silicon wafer to form an N-type emitter;
(3) removing phosphorosilicate glass and peripheral PN junctions formed in the diffusion process, and polishing the back of the silicon wafer;
(4) carrying out thermal oxidation treatment on the silicon wafer;
(5) depositing a passivation film on the back of the silicon wafer;
(6) depositing a passivation film on the front side of the silicon wafer;
(7) grooving the passivation film on the back of the silicon wafer;
(8) placing a silicon wafer into heat treatment equipment, wherein the heat treatment equipment comprises a high-temperature activation region and a low-temperature repair region, and the silicon wafer is subjected to high-temperature thermal annealing treatment in the high-temperature activation region so as to increase the overall lattice thermal motion of the silicon substrate; then, low-temperature thermal annealing treatment is carried out in the low-temperature repairing region to recrystallize the silicon substrate;
(9) printing a back electrode and a front electrode;
(10) and (4) sintering the silicon wafer at high temperature to obtain the P-type PERC double-sided solar cell.
As an improvement of the scheme, the temperature of the high-temperature activation area is 600-900 ℃, and the time of the high-temperature thermal annealing treatment is 20 s-3 min.
As an improvement of the scheme, the temperature of the low-temperature repairing area is 200-500 ℃, and the time of the low-temperature thermal annealing treatment is 40 s-5 min.
As an improvement of the scheme, the thermal annealing treatment curve of the silicon wafer comprises the following steps:
heating to 600-900 ℃ from room temperature within 1-4 min;
keeping the temperature at 600-900 ℃ for 20 s-2 min;
rapidly cooling from 600-900 ℃ within 40 s-8 min, and then slowly cooling to 200-500 ℃;
rapidly cooling from 200-500 ℃ to below 50 ℃ within 1-2 min.
As an improvement of the scheme, the silicon wafer is conveyed between the high-temperature activation area and the low-temperature repair area through a conveyor belt, the belt speed of the conveyor belt is 500-4000 mm/min, and the total annealing time is 1-12 min.
As an improvement of the above scheme, the high-temperature activation region comprises an upper high-temperature activation region and a lower high-temperature activation region, the low-temperature repair region comprises an upper low-temperature repair region and a lower low-temperature repair region, and the upper high-temperature activation region, the upper low-temperature repair region, the lower high-temperature activation region and the lower low-temperature repair region are symmetrically arranged on two sides of the conveyor belt.
As an improvement of the scheme, the heat treatment equipment is a crystalline silicon solar sintering furnace.
As an improvement of the scheme, the treatment temperature of the thermal oxidation treatment is 500-700 ℃, and the treatment time is 5-12 min.
As an improvement of the above, the temperature profile of the thermal oxidation process includes:
heating to 500-700 ℃ from room temperature within 2-6 min;
keeping the temperature at 500-700 ℃ for 2-4 min;
and cooling to room temperature from 500-700 ℃ within 3-7 min.
As an improvement of the proposal, the passivation film deposited on the back surface is Al2O3/SiNxFilm of, wherein Al2O3The film thickness is 5-10nm, SiNxHas a thickness of 70-140 nm.
The implementation of the invention has the following beneficial effects:
according to the invention, after thermal oxidation treatment is carried out on the cell piece by using the sintering furnace, thermal annealing treatment is carried out again, the annealing process is divided into two parts of high-temperature activation and low-temperature repair, high-temperature thermal annealing treatment is carried out in a high-temperature activation region, the integral crystal lattice thermal motion of the substrate silicon can be greatly increased, low-temperature thermal annealing treatment is carried out in a low-temperature repair region, and the silicon substrate is recrystallized through slow cooling to promote the irregularly arranged crystal lattice defects at the grooving position to be rearranged, so that the crystal lattice defects are repaired, and the back surface recombination rate is reduced.
After the semi-finished cell after the back film laser is subjected to thermal annealing repair, the amplified _ Voc is increased by 2-4 mV, the actual open-circuit voltage Voc is increased by 2-3 mV, and the conversion efficiency of the solar cell is increased by more than 0.1%.
Drawings
FIG. 1 is a flow chart of methods for repairing laser grooving damage to a backside film of a PERC solar cell.
FIG. 2 is a schematic representation of a thermal oxidation temperature profile of the present invention;
FIG. 3 is a schematic representation of the thermal annealing temperature profile of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail .
The invention provides methods for repairing PERC solar cell back film laser grooving damage, which comprise the following steps:
s101, forming textured surfaces on the front side and the back side of a silicon wafer, wherein the silicon wafer is P-type silicon.
And forming a suede surface on the surface of the silicon wafer by using a texturing device by selecting a wet etching technology or a dry etching technology.
And S102, diffusing on the front surface of the silicon wafer to form an N-type emitter.
The preparation method adopts a diffusion process that a silicon wafer is placed in a thermal diffusion furnace for diffusion, an N-type emitter is formed above P-type silicon, the temperature is controlled within the range of 800-900 ℃ during diffusion, and the target square resistance is 90-150 ohm/□.
Forming phosphorosilicate glass layers on the front and back of the silicon wafer in the diffusion process, wherein the phosphorosilicate glass layers are formed due to POCl in the diffusion process3And O2Reaction to form P2O5Depositing on the surface of the silicon chip. P2O5React with Si to form SiO2And phosphorus atoms, thereby forming layers of SiO containing phosphorus elements on the surface of the silicon wafer2The phosphosilicate glass layer can collect impurities in the silicon wafer during diffusion, and the impurity content of the solar cell can be further reduced .
S103, removing the phosphorosilicate glass and the peripheral PN junction formed in the diffusion process, and polishing the back of the silicon wafer.
Placing the diffused silicon wafer into HF (40-50 mass percent) and HNO with the volume ratio of 1:53(the mass fraction is 60% -70%) for 15s in an acid tank to remove the phosphorosilicate glass and the peripheral PN junction. The existence of the phosphorosilicate glass layer is easy to cause the chromatic aberration of PECVD and SixNyAnd the phosphosilicate glass layer contains a large amount of phosphorus and impurities migrating from the silicon wafer, and thus the phosphosilicate glass layer needs to be removed.
It should be noted that the step of polishing the back surface of the silicon wafer is performed or not depending on the actual situation.
And S104, performing thermal oxidation treatment on the silicon wafer.
The treatment temperature of the thermal oxidation treatment is 500-700 ℃, and the treatment time is 5-12 min.
As shown in fig. 2, the temperature profile of the thermal oxidation process includes: heating to 500-700 ℃ from room temperature within 2-6 min; keeping the temperature at 500-700 ℃ for 2-4 min; and cooling to room temperature from 500-700 ℃ within 3-7 min.
Preferably, the temperature profile of the thermal oxidation process includes: heating to 600-700 ℃ from room temperature within 3-5 min; keeping the temperature at 600-700 ℃ for 2-3 min; and cooling to room temperature from 600-700 ℃ within 4-6 min.
More preferably, the temperature profile of the thermal oxidation process includes: heating to 650 deg.C from room temperature within 4 min; maintaining at 650 deg.C for 2 min; and cooling from 650 ℃ to room temperature within 5 min.
The thermal oxidation after diffusion is divided into three steps of temperature rise, constant temperature oxidation and temperature reduction, the equipment is a tubular annealing furnace, the thermal oxidation mainly has the functions of 1 activating the diffused gap phosphorus and reducing a surface dead layer, 2 generating layers of extremely thin silicon oxide on the silicon surface and passivating dangling bonds on the silicon surface, and 3, the compactness of the silicon oxide can prevent impurities from permeating into the silicon body.
And S105, depositing a passivation film on the back surface of the silicon wafer.
The passivation film deposited on the back surface is preferably Al2O3/SiNxFilm of Al2O3/SiNxStable lamination properties, wherein Al2O3The film thickness is 5-10nm, SiNxHas a thickness of 70-140 nm. Al (Al)2O3Film, SiNxThe passivation effect is poor when the thickness of the film is too low, and the contact is affected when the thickness is too high.
And S106, depositing a passivation film on the front surface of the silicon wafer.
The deposition steps can adopt conventional PECVD equipment, ALD equipment or APCVD equipment to sequentially deposit passivation films on the back surface and the front surface of the silicon wafer. It should be noted that the order of step S105 and step S106 may be reversed and interchanged without affecting the battery structure and performance.
And S107, slotting on the passivation film on the back of the silicon wafer.
And (3) slotting on the passivation film on the back of the silicon wafer by adopting a laser slotting technology, wherein the slotting depth is up to the lower surface of the P-type silicon.
S108, placing the silicon wafer into heat treatment equipment, wherein the heat treatment equipment comprises a high-temperature activation region and a low-temperature repair region, and the silicon wafer is subjected to high-temperature thermal annealing treatment in the high-temperature activation region so as to increase the overall lattice thermal motion of the silicon substrate; and then carrying out low-temperature thermal annealing treatment in the low-temperature repairing region to recrystallize the silicon substrate.
The temperature of the high-temperature activation region is 600-900 ℃, and the annealing time of the high-temperature section is 20 s-3 min;
the temperature of the low-temperature repair area is 200-500 ℃, and the annealing time of the low-temperature section is 40 s-5 min;
as shown in fig. 3, the thermal annealing temperature profile of the present invention, activated before recrystallization, is roughly as follows:
heating to 600-900 ℃ from room temperature within 1-4 min;
keeping the temperature at 600-900 ℃ for 20 s-2 min;
rapidly cooling from 600-900 ℃ within 40 s-8 min, and then slowly cooling to 200-500 ℃;
rapidly cooling from 200-500 ℃ to below 50 ℃ within 1-2 min.
Preferably, the thermal annealing temperature profile is approximately as follows:
heating to 700-850 ℃ from room temperature within 1-2 min;
keeping the temperature at 700-850 ℃ for 40 s-1 min;
rapidly cooling from 700-850 ℃ to 550-600 ℃ within 1-2 min, and then slowly cooling to 400 ℃ within 5-6 min;
rapidly cooling from 400 ℃ to below 50 ℃ within 1-2 min.
More preferably, the thermal annealing temperature profile is substantially as follows:
heating to 780-800 ℃ from room temperature within 1-2 min;
keeping the temperature at 780-800 ℃ for 1 min;
rapidly cooling to 600 ℃ from 780-800 ℃ within 2min, and then slowly cooling to 400 ℃ within 5 min;
rapidly cooling from 400 deg.C to below 50 deg.C within 1 min.
The silicon chip is transmitted between the high-temperature activation area and the low-temperature repair area through a conveyor belt, the belt speed of the conveyor belt is 500-4000 mm/min, and the total annealing time is 1-12 min.
The silicon wafer is transmitted through a conveying belt in a heat treatment device, uniform annealing treatment can be realized through the upper high-temperature activation region, the upper low-temperature repair region, the lower high-temperature activation region and the lower low-temperature repair region which are symmetrical up and down, the thermal motion of the integral crystal lattice of the substrate silicon can be greatly increased during high-temperature annealing, the consistency of recrystallization of the silicon substrate can be improved during low-temperature annealing, the crystal lattice defect can be better repaired, and the back recombination rate can be reduced.
The heat treatment equipment is a crystalline silicon solar sintering furnace. The invention can be realized by selecting a conventional solar cell sintering furnace, and the equipment has the characteristics of simple structure, convenient operation, high capacity and the like, and is suitable for large-scale production and application.
And S109, printing a back electrode and a front electrode.
And printing the back silver paste according to the pattern of the back silver main grid. The pattern of the back silver main grid is a continuous straight grid; or the back silver main grids are arranged at intervals in a segmented manner; or the back silver main grids are arranged in segments at intervals, and all adjacent segments are connected through a communicating area.
And after the back silver main grid is printed, printing aluminum paste on the grooved area to form a plurality of aluminum grid lines, wherein the aluminum grid lines are vertical to or obliquely intersected with the back silver main grid. Preferably, the width of the aluminum grid line is 30-550 μm; the width of the back silver main grid is 0.5-5 mm.
Finally, the front electrode is printed according to the design requirement of the front electrode.
And S110, sintering the silicon wafer at high temperature to obtain the P-type PERC double-sided solar cell.
According to the invention, before the front passivation film and the back passivation film are deposited, thermal oxidation treatment is firstly carried out on the silicon wafer, and then a thermal annealing process is added between the steps of back film laser grooving and screen mesh sintering, so that lattice defects can be obviously repaired, and the back surface recombination rate is reduced, specifically, after the semi-finished cell after back film laser is subjected to thermal annealing repair, the amplified _ Voc is increased by 2-4 mV, the actual open circuit voltage Voc is increased by 2-3 mV, and the conversion efficiency of the solar cell is increased by more than 0.1%.
It should be noted that the interpolated _ Voc refers to Voc measured when the battery is not manufactured after diffusion, i.e., a theoretical Voc value of the battery.
The invention is further illustrated by the following specific example
Example 1
(1) Forming a suede on the front side and the back side of a silicon wafer, wherein the silicon wafer is P-type silicon;
(2) diffusing on the front side of the silicon wafer to form an N-type emitter;
(3) removing phosphorosilicate glass and peripheral PN junctions formed in the diffusion process, and polishing the back of the silicon wafer;
(4) carrying out thermal oxidation treatment on the silicon wafer;
the temperature profile of the thermal oxidation process includes:
heating to 500 deg.C from room temperature within 2 min;
maintaining at 500 deg.C for 2 min;
and (3) cooling to room temperature from 500 ℃ within 3 min.
(5) Depositing a passivation film on the back of the silicon wafer;
(6) depositing a passivation film on the front side of the silicon wafer;
(7) grooving the passivation film on the back of the silicon wafer;
(8) placing a silicon wafer into heat treatment equipment, wherein the heat treatment equipment comprises a high-temperature activation region and a low-temperature repair region, and the silicon wafer is subjected to high-temperature thermal annealing treatment in the high-temperature activation region so as to increase the overall lattice thermal motion of the silicon substrate; then, low-temperature thermal annealing treatment is carried out in the low-temperature repairing region to recrystallize the silicon substrate;
wherein the thermal annealing treatment curve of the silicon wafer comprises the following steps:
heating to 700 deg.C from room temperature within 1 min;
holding at 700 deg.C for 50 s;
rapidly cooling from 700 deg.C to 550 deg.C within 1min, and slowly cooling to 400 deg.C within 5 min;
rapidly cooling from 400 deg.C to below 50 deg.C within 1 min.
(9) Printing a back electrode and a front electrode;
(10) and (4) sintering the silicon wafer at high temperature to obtain the P-type PERC double-sided solar cell.
Example 2
(1) Forming a suede on the front side and the back side of a silicon wafer, wherein the silicon wafer is P-type silicon;
(2) diffusing on the front side of the silicon wafer to form an N-type emitter;
(3) removing phosphorosilicate glass and peripheral PN junctions formed in the diffusion process, and polishing the back of the silicon wafer;
(4) carrying out thermal oxidation treatment on the silicon wafer;
the temperature profile of the thermal oxidation process includes:
heating to 600 deg.C from room temperature within 4 min;
maintaining at 600 deg.C for 3 min;
and (3) cooling from 600 ℃ to room temperature within 5 min.
(5) Depositing a passivation film on the back of the silicon wafer;
(6) depositing a passivation film on the front side of the silicon wafer;
(7) grooving the passivation film on the back of the silicon wafer;
(8) placing a silicon wafer into heat treatment equipment, wherein the heat treatment equipment comprises a high-temperature activation region and a low-temperature repair region, and the silicon wafer is subjected to high-temperature thermal annealing treatment in the high-temperature activation region so as to increase the overall lattice thermal motion of the silicon substrate; then, low-temperature thermal annealing treatment is carried out in the low-temperature repairing region to recrystallize the silicon substrate;
wherein the thermal annealing treatment curve of the silicon wafer comprises the following steps:
heating to 780 deg.C from room temperature within 2 min;
maintaining at 780 deg.C for 1 min;
rapidly cooling from 780 deg.C to 600 deg.C within 2min, and slowly cooling to 400 deg.C within 5 min;
rapidly cooling from 400 deg.C to below 50 deg.C within 1 min.
(9) Printing a back electrode and a front electrode;
(10) and (4) sintering the silicon wafer at high temperature to obtain the P-type PERC double-sided solar cell.
Example 3
(1) Forming a suede on the front side and the back side of a silicon wafer, wherein the silicon wafer is P-type silicon;
(2) diffusing on the front side of the silicon wafer to form an N-type emitter;
(3) removing phosphorosilicate glass and peripheral PN junctions formed in the diffusion process, and polishing the back of the silicon wafer;
(4) carrying out thermal oxidation treatment on the silicon wafer;
the temperature profile of the thermal oxidation process includes:
heating to 650 deg.C from room temperature within 5 min;
maintaining at 650 deg.C for 3 min;
and cooling from 650 ℃ to room temperature within 5 min.
(5) Depositing a passivation film on the back of the silicon wafer;
(6) depositing a passivation film on the front side of the silicon wafer;
(7) grooving the passivation film on the back of the silicon wafer;
(8) placing a silicon wafer into heat treatment equipment, wherein the heat treatment equipment comprises a high-temperature activation region and a low-temperature repair region, and the silicon wafer is subjected to high-temperature thermal annealing treatment in the high-temperature activation region so as to increase the overall lattice thermal motion of the silicon substrate; then, low-temperature thermal annealing treatment is carried out in the low-temperature repairing region to recrystallize the silicon substrate;
wherein the thermal annealing treatment curve of the silicon wafer comprises the following steps:
heating to 800 deg.C from room temperature within 1 min;
maintaining at 8000 deg.C for 1 min;
rapidly cooling to 580 deg.C from 800 deg.C within 2min, and slowly cooling to 400 deg.C within 6 min;
rapidly cooling from 400 deg.C to below 50 deg.C within 1 min.
(9) Printing a back electrode and a front electrode;
(10) and (4) sintering the silicon wafer at high temperature to obtain the P-type PERC double-sided solar cell.
Example 4
(1) Forming a suede on the front side and the back side of a silicon wafer, wherein the silicon wafer is P-type silicon;
(2) diffusing on the front side of the silicon wafer to form an N-type emitter;
(3) removing phosphorosilicate glass and peripheral PN junctions formed in the diffusion process, and polishing the back of the silicon wafer;
(4) carrying out thermal oxidation treatment on the silicon wafer;
the temperature profile of the thermal oxidation process includes:
heating to 700 deg.C from room temperature within 3 min;
maintaining at 700 deg.C for 4 min;
and (3) cooling from 700 ℃ to room temperature within 7 min.
(5) Depositing a passivation film on the back of the silicon wafer;
(6) depositing a passivation film on the front side of the silicon wafer;
(7) grooving the passivation film on the back of the silicon wafer;
(8) placing a silicon wafer into heat treatment equipment, wherein the heat treatment equipment comprises a high-temperature activation region and a low-temperature repair region, and the silicon wafer is subjected to high-temperature thermal annealing treatment in the high-temperature activation region so as to increase the overall lattice thermal motion of the silicon substrate; then, low-temperature thermal annealing treatment is carried out in the low-temperature repairing region to recrystallize the silicon substrate;
wherein the thermal annealing treatment curve of the silicon wafer comprises the following steps:
heating to 850 deg.C from room temperature within 3 min;
maintaining at 850 deg.C for 2 min;
rapidly cooling to 560 deg.C from 850 deg.C within 3min, and slowly cooling to 380 deg.C within 5 min;
rapidly cooling from 380 deg.C to below 50 deg.C within 2 min.
(9) Printing a back electrode and a front electrode;
(10) and (4) sintering the silicon wafer at high temperature to obtain the P-type PERC double-sided solar cell.
The P-type PERC double-sided solar cells obtained in examples 1 to 4 were tested, and the results were as follows:
according to the invention, after the semi-finished cell after the back film laser is subjected to thermal annealing repair, the amplified _ Voc is increased by 2-4 mV, the actual open-circuit voltage Voc is increased by 2-3 mV, and the conversion efficiency of the solar cell is increased by more than 0.1%.
While the invention has been described with reference to certain preferred embodiments , it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1, method for repairing PERC solar cell back film laser grooving damage, which comprises:
(1) forming a suede on the front side and the back side of a silicon wafer, wherein the silicon wafer is P-type silicon;
(2) diffusing on the front side of the silicon wafer to form an N-type emitter;
(3) removing phosphorosilicate glass and peripheral PN junctions formed in the diffusion process, and polishing the back of the silicon wafer;
(4) carrying out thermal oxidation treatment on the silicon wafer;
(5) depositing a passivation film on the back of the silicon wafer;
(6) depositing a passivation film on the front side of the silicon wafer;
(7) grooving the passivation film on the back of the silicon wafer;
(8) placing a silicon wafer into heat treatment equipment, wherein the heat treatment equipment comprises a high-temperature activation region and a low-temperature repair region, and the silicon wafer is subjected to high-temperature thermal annealing treatment in the high-temperature activation region so as to increase the overall lattice thermal motion of the silicon substrate; then, low-temperature thermal annealing treatment is carried out in the low-temperature repairing region to recrystallize the silicon substrate;
(9) printing a back electrode and a front electrode;
(10) and (4) sintering the silicon wafer at high temperature to obtain the P-type PERC double-sided solar cell.
2. The method for repairing the laser grooving damage of the back film of the PERC solar cell as claimed in claim 1, wherein the temperature of the high temperature activation region is 600-900 ℃, and the time of the high temperature thermal annealing treatment is 20 s-3 min.
3. The method for repairing the laser grooving damage of the back film of the PERC solar cell as claimed in claim 1, wherein the temperature of the low-temperature repairing region is 200-500 ℃, and the time of the low-temperature thermal annealing treatment is 40 s-5 min.
4. The method of repairing PERC solar cell back film laser grooving damage of claim 1, wherein the thermal annealing treatment profile of the silicon wafer comprises:
heating to 600-900 ℃ from room temperature within 1-4 min;
keeping the temperature at 600-900 ℃ for 20 s-2 min;
rapidly cooling from 600-900 ℃ within 40 s-8 min, and then slowly cooling to 200-500 ℃;
rapidly cooling from 200-500 ℃ to below 50 ℃ within 1-2 min.
5. The method for repairing the laser grooving damage to the back film of the PERC solar cell as claimed in claim 1, wherein the silicon wafer is transported between the high temperature activation region and the low temperature repair region by a conveyor belt, the belt speed of the conveyor belt is 500mm/min to 4000mm/min, and the total annealing time is 1min to 12 min.
6. The method of repairing PERC solar cell backsheet laser grooving damage of claim 5 wherein said high temperature active region comprises an upper high temperature active region and a lower high temperature active region and said low temperature repair region comprises an upper low temperature repair region and a lower low temperature repair region, said upper high temperature active region, said upper low temperature repair region and said lower high temperature active region and said lower low temperature repair region being symmetrically disposed on opposite sides of said conveyor belt.
7. The method for repairing the laser grooving damage to the back film of the PERC solar cell as claimed in claim 6, wherein the heat treatment equipment is a crystalline silicon solar sintering furnace.
8. The method for repairing the laser grooving damage of the back film of the PERC solar cell as claimed in claim 1, wherein the thermal oxidation treatment is performed at a treatment temperature of 500 ℃ to 700 ℃ for a treatment time of 5min to 12 min.
9. The method of repairing PERC solar cell back film laser grooving damage of claim 8, wherein the thermal oxidation process temperature profile comprises:
heating to 500-700 ℃ from room temperature within 2-6 min;
keeping the temperature at 500-700 ℃ for 2-4 min;
and cooling to room temperature from 500-700 ℃ within 3-7 min.
10. The method of repairing PERC solar cell back film laser grooving damage of claim 1, wherein the back deposited passivation film is Al2O3/SiNxFilm of, wherein Al2O3The film thickness is 5-10nm, SiNxHas a thickness of 70-140 nm.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111987191A (en) * | 2020-09-09 | 2020-11-24 | 苏州腾晖光伏技术有限公司 | Method for repairing PERC battery laser membrane opening damage |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140017846A1 (en) * | 2011-12-26 | 2014-01-16 | Solexel, Inc. | Systems and methods for enhanced light trapping in solar cells |
| CN103560173A (en) * | 2013-11-08 | 2014-02-05 | 中电电气（扬州）光伏有限公司 | Preparation method of P-type back passivation solar cell |
| TW201436274A (en) * | 2013-02-08 | 2014-09-16 | Applied Materials Inc | Improved passivation layer removal by delivering a split laser pulse |
| CN105226112A (en) * | 2015-09-25 | 2016-01-06 | 中节能太阳能科技（镇江）有限公司 | A kind of preparation method of efficient crystal silicon solar batteries |
| CN109301030A (en) * | 2018-09-07 | 2019-02-01 | 江苏顺风光电科技有限公司 | A kind of low cost N-type double-side cell preparation method |
| CN109616556A (en) * | 2018-12-18 | 2019-04-12 | 韩华新能源（启东）有限公司 | A kind of annealing of silicon chip back side and the integrated method of front plated film and a kind of preparation method of cell piece |
-
2019
- 2019-10-16 CN CN201910982137.4A patent/CN110739366B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140017846A1 (en) * | 2011-12-26 | 2014-01-16 | Solexel, Inc. | Systems and methods for enhanced light trapping in solar cells |
| TW201436274A (en) * | 2013-02-08 | 2014-09-16 | Applied Materials Inc | Improved passivation layer removal by delivering a split laser pulse |
| CN103560173A (en) * | 2013-11-08 | 2014-02-05 | 中电电气（扬州）光伏有限公司 | Preparation method of P-type back passivation solar cell |
| CN105226112A (en) * | 2015-09-25 | 2016-01-06 | 中节能太阳能科技（镇江）有限公司 | A kind of preparation method of efficient crystal silicon solar batteries |
| CN109301030A (en) * | 2018-09-07 | 2019-02-01 | 江苏顺风光电科技有限公司 | A kind of low cost N-type double-side cell preparation method |
| CN109616556A (en) * | 2018-12-18 | 2019-04-12 | 韩华新能源（启东）有限公司 | A kind of annealing of silicon chip back side and the integrated method of front plated film and a kind of preparation method of cell piece |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111987191A (en) * | 2020-09-09 | 2020-11-24 | 苏州腾晖光伏技术有限公司 | Method for repairing PERC battery laser membrane opening damage |
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