CN218414591U

CN218414591U - Solar cell

Info

Publication number: CN218414591U
Application number: CN202222369575.3U
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Sany Silicon Energy Zhuzhou Co Ltd
Current assignee: Sany Silicon Energy Zhuzhou Co Ltd
Priority date: 2022-09-06
Filing date: 2022-09-06
Publication date: 2023-01-31
Anticipated expiration: 2032-09-06

Abstract

The utility model relates to the field of photovoltaic technology, a solar cell is provided, include: the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer are sequentially stacked on the silicon wafer substrate, the doped polycrystalline silicon layer comprises a heavily doped region and a lightly doped region outside the heavily doped region, and the heavily doped region is used for arranging a metal grid line. The utility model discloses be used for solving and cause the damage to the silicon chip basement among the prior art, be unfavorable for improving the defect of battery efficiency, have the doping polycrystalline silicon layer in heavy doping region through the setting, avoid setting up the heavy doping region in the silicon chip basement, reduce the damage to the silicon chip basement, promote the passivation effect simultaneously, be favorable to improving battery efficiency.

Description

Solar cell

Technical Field

The utility model relates to the field of photovoltaic technology, especially, relate to a solar cell.

Background

With the rapid development of photovoltaic technology, the demand of high-efficiency solar cells is more and more urgent. The preparation of solar cells by selective doping is an effective way to increase the efficiency of the cells. The solar cell is prepared by selective doping, namely heavy doping is carried out on a metal contact area on the surface of a silicon wafer, so that the contact resistance of the cell is reduced, light doping is carried out on a non-metal contact area on the surface of the silicon wafer, the spectral response of the cell is improved, and the recombination of photon-generated carriers in the cell is reduced.

At present, a solar cell prepared by selective doping mainly forms a heavily doped region in a silicon wafer substrate, and the silicon wafer substrate is used as a selective doping structure, so that the silicon wafer substrate is damaged, and the efficiency of the cell is not improved.

SUMMERY OF THE UTILITY MODEL

The utility model provides a solar cell for solve among the prior art and cause the damage to the silicon chip basement, be unfavorable for improving battery efficiency's defect, when realizing avoiding causing the damage to the silicon chip basement, promote the passivation effect, be favorable to improving battery efficiency.

The utility model provides a solar cell, include: the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer are sequentially stacked on the silicon wafer substrate, the doped polycrystalline silicon layer comprises a heavily doped region and a lightly doped region outside the heavily doped region, and the heavily doped region is used for arranging a metal grid line.

According to the utility model provides a pair of solar cell, nanocrystalline silicon layer is doping nanocrystalline silicon layer.

According to the utility model provides a pair of solar cell, the doping type of silicon chip basement is N type doping or P type doping.

According to the utility model provides a pair of solar cell, the doping type of doping polycrystalline silicon layer is N type doping or P type doping.

According to the utility model provides a pair of solar cell, the material of tunneling oxide layer includes silicon oxide, the thickness of tunneling oxide layer is 1 ~ 3 nanometers.

According to the utility model provides a pair of solar cell, the tunneling oxide layer nanocrystalline silicon layer with the doping polycrystalline silicon layer sets up at least one side in the front or the back of silicon chip basement.

According to the utility model provides a pair of solar cell, the tunneling oxide layer nanocrystalline silicon layer with the doping polycrystalline silicon layer sets up the front of silicon chip basement, the surface of doping polycrystalline silicon layer stacks gradually and is provided with passivation layer, positive antireflection coating and front electrode, the back of silicon chip basement stacks gradually and is provided with back passivation contact structure, back antireflection coating and back electrode.

According to the utility model provides a pair of solar cell, the tunneling oxide layer nanocrystalline silicon layer with the doping polycrystalline silicon layer sets up the back of silicon chip basement, the surface of doping polycrystalline silicon layer stacks gradually and is provided with back antireflection coating and back electrode, the front of silicon chip basement stacks gradually and is provided with doping layer, passivation layer, positive antireflection coating and front electrode.

According to the utility model provides a pair of solar cell, the passivation layer is including the silicon oxide layer and the aluminium oxide layer of range upon range of setting.

According to the utility model provides a pair of solar cell, the front antireflection coating with the back antireflection coating is the silicon nitride layer.

The utility model provides a solar cell, include the tunneling oxide layer, nanocrystalline silicon layer and the doping polycrystalline silicon layer that stack gradually and set up on the silicon chip basement, wherein, the tunneling oxide layer can improve the passivation effect of silicon chip basement surface, and nanocrystalline silicon layer has lower extinction coefficient, and the absorption to the light is showing to the reduction, reduces optical absorption loss; the doped polycrystalline silicon layer comprises a heavily doped region and a lightly doped region, the doped polycrystalline silicon layer has a selective doping effect, the heavily doped region is arranged on the doped polycrystalline silicon layer, damage to a silicon wafer substrate is avoided, in addition, the heavily doped region is used for arranging metal grid lines and corresponds to a metal contact region of the silicon wafer substrate, contact resistance can be effectively reduced, filling factors are improved, the lightly doped region outside the heavily doped region corresponds to a non-metal contact region of the silicon wafer substrate, the passivated contact effect is good, and improvement of the battery efficiency is facilitated.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic flow chart of a method for manufacturing a solar cell provided by the present invention;

FIG. 2 is a process curve of an annealing treatment provided by the present invention;

fig. 3 is a schematic structural diagram of a film layer formed on the front surface of a silicon wafer substrate in the method for manufacturing a solar cell according to the present invention;

fig. 4 is a second schematic structural diagram of a film layer formed on the front surface of the silicon wafer substrate in the method for manufacturing a solar cell according to the present invention;

fig. 5 is a schematic structural diagram of a film layer formed on the back surface of a silicon wafer substrate in the method for manufacturing a solar cell according to the present invention;

fig. 6 is a second schematic structural diagram of a film layer formed on the back surface of the silicon wafer substrate in the method for manufacturing a solar cell according to the present invention;

fig. 7 is a schematic structural diagram of a solar cell provided by the present invention;

fig. 8 is a second schematic structural diagram of a solar cell according to the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the present invention clearer, the drawings of the present invention are combined to clearly and completely describe the technical solutions of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The following describes a method for manufacturing a solar cell according to the present invention with reference to fig. 1 and 6.

Fig. 1 is a schematic flow chart of a method for manufacturing a solar cell according to the present invention.

As shown in fig. 1, the method for manufacturing a solar cell provided in this embodiment at least includes the following steps:

and S100, forming a tunneling oxide layer on the silicon wafer substrate.

The doping type of the silicon wafer substrate can be N-type doping or P-type doping, and the silicon wafer substrate can be subjected to pretreatment such as texturing, polishing and/or etching before the tunneling oxide layer is formed. For example, the tunnel oxide layer may be silicon oxide, have a thickness of 1 to 3 nanometers (nm), and may be deposited by thermal oxidation, thermal nitric acid oxidation, or a CVD (Chemical Vapor Deposition) method.

And S200, forming a nano amorphous silicon layer on the tunneling oxide layer.

The nano amorphous silicon layer has a lower extinction coefficient, and can remarkably reduce the absorption of light and reduce the optical absorption loss. Meanwhile, the nano amorphous silicon layer has a buffering effect, and atoms of doping elements are reduced from penetrating through the tunneling oxide layer in the subsequent process of selectively doping the first doped amorphous silicon layer.

And S300, forming a first doped amorphous silicon layer on the nano amorphous silicon layer.

The doping type of the first doped amorphous silicon layer may be N-type doping or P-type doping, when the doping type of the first doped amorphous silicon layer is N-type doping, the phosphorus doped amorphous silicon layer may be used, and when the doping type of the first doped amorphous silicon layer is P-type doping, the boron doped amorphous silicon layer may be used. The first doped amorphous silicon layer can be prepared and formed by adopting the processes of CVD, PVD (Physical Vapor Deposition) or ion implantation and the like, the process temperature is low, the process time is short, and the preparation efficiency can be improved. The CVD process includes PECVD (Plasma Enhanced Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), and the like.

And S400, forming a doping source layer on the first doping amorphous silicon layer.

Wherein the doping type of the doping source layer is consistent with that of the first doped amorphous silicon layer. The doping type of the doping source layer can be N-type doping or P-type doping, when the doping type of the doping source layer is N-type doping, the doping element of the doping source layer can be phosphorus element, and when the doping type of the doping source layer is P-type doping, the doping element of the doping source layer can be boron element. The doping source layer can be prepared and formed by adopting the processes of CVD, PVD or ion implantation and the like, the process temperature is low, the process time is short, and the preparation efficiency can be improved. The doping concentration of the doping source can be adjusted according to actual needs.

S500, injecting doping elements of the doping source layer into a region of the first doping amorphous silicon layer corresponding to the metal grid line through selective doping to form a heavily doped region, enabling the first doping amorphous silicon layer to form a doping polycrystalline silicon layer through annealing treatment, and enabling the nano amorphous silicon layer to form a nano crystalline silicon layer.

The region of the first doped amorphous silicon layer corresponding to the metal grid line refers to a metal contact region for arranging the metal grid line on the silicon wafer substrate. Therefore, the formed heavily doped region corresponds to the metal contact region for disposing the metal gate line.

And S600, removing the doping source layer.

The doping source layer is an intermediate structure formed by selective doping in the preparation method of the solar cell, and is not the structure of the solar cell, so that after the doped polycrystalline silicon layer is obtained, the doping source layer on the surface of the doped polycrystalline silicon layer needs to be removed. According to the material of the doped source layer, the doped source layer can be removed by etching and/or cleaning.

To sum up, the utility model provides a preparation method of solar cell, at first, form the tunneling oxide layer on the silicon chip basement, improve the passivation effect on silicon chip basement surface; secondly, a nanocrystalline silicon layer is added on the tunneling oxide layer, the nanocrystalline silicon layer has a lower extinction coefficient, can obviously reduce the absorption of light and reduce the optical absorption loss, and has a buffer effect at the same time, so that the atoms of doped elements can be reduced from penetrating through the tunneling oxide layer; then, a first doped amorphous silicon layer and a doped source layer are sequentially formed on the nanocrystalline silicon layer, doping elements of the doped source layer are injected into a region of the first doped amorphous silicon layer corresponding to the metal grid line through selective doping, and a heavily doped region is formed on the first doped amorphous silicon layer without selectively doping the silicon wafer substrate, so that the damage to the silicon wafer substrate is avoided, and the improvement of the cell efficiency is facilitated; in addition, a doping source layer is formed on the first doping amorphous silicon layer and serves as a doping source for selective doping, the doping concentration of the doping source layer can be flexibly adjusted according to needs, the concentration of a heavily doped region can be adjusted, the preparation method is simple and efficient, and the preparation efficiency is improved.

Illustratively, the doping concentration of the doping source layer is greater than the doping concentration of the first doped amorphous silicon layer.

In order to ensure that the heavily doped region has a higher doping concentration, a doping source layer with a high doping concentration needs to be formed on the surface of the first doped amorphous silicon layer with a low doping concentration, and therefore, the doping concentration of the doping source layer can be greater than that of the first doped amorphous silicon layer. For example, the first doped amorphous silicon layer is a boron doped amorphous silicon layer with a low doping concentration of 1 to 2 × 10 ¹⁹ atoms/cm ³ The doping element of the doping source layer is boron element, and the doping concentration is 3-5 multiplied by 10 ¹⁹ atoms/cm ³ (ii) a Or the first doped amorphous silicon layer is a phosphorus doped amorphous silicon layer with low doping concentration of 3-6 multiplied by 10 ²⁰ atoms/cm ³ The doping element of the doping source layer is phosphorus element, and the doping concentration is 1-3 multiplied by 10 ²¹ atoms/cm ³ 。

The doping source is used for providing the doping source for the selective doping process, and various structures can be arranged according to actual requirements.

Illustratively, the forming a doping source layer on the first doped amorphous silicon layer includes:

forming a first oxide layer on the surface of the first doped amorphous silicon layer; illustratively, the first oxide layer may be silicon oxide, and may be prepared by thermal oxidation, thermal nitric acid oxidation, or a CVD process;

forming at least one second doped amorphous silicon layer on the surface of the first oxide layer; for example, the second doped amorphous silicon layer may be prepared by PECVD, LPCVD, PVD, ion implantation, or the like;

the first oxide layer and the at least one second doped amorphous silicon layer form the doping source layer.

The number of prepared layers of the second doped amorphous silicon layer can be determined according to actual needs, so that the doping concentration of the medium and heavy doped region can be adjusted conveniently, and the doping concentration of the second doped amorphous silicon layer can be higher than that of the first doped amorphous silicon layer.

Further, in the step S500, the second doped amorphous silicon layer may be crystallized into a doped polysilicon layer by an annealing process.

Further, in step S600, removing the doping source layer includes:

removing the doped polysilicon layer crystallized from the second doped amorphous silicon layer by etching, for example, removing the doped polysilicon layer crystallized from the second doped amorphous silicon layer by trench etching;

the first oxide layer is removed by cleaning, and may be removed by cleaning with hydrofluoric acid (HF), for example.

Wherein the first oxide layer functions as: and when the doped polycrystalline silicon layer formed by the crystallization of the second doped amorphous silicon layer is removed by etching, an isolation protection effect is formed on the doped polycrystalline silicon layer formed by the crystallization of the first doped amorphous silicon layer, so that the etching damage to the doped polycrystalline silicon layer formed by the crystallization of the first doped amorphous silicon layer is avoided, and the integrity of the doped polycrystalline silicon layer is protected. Therefore, the doping source layer formed by the first oxidation layer and the second doping amorphous silicon layer can ensure the integrity of the battery structure in the preparation process, and the preparation process is safer and more reliable.

and forming at least one doped oxide layer on the surface of the first doped amorphous silicon layer, wherein the at least one doped oxide layer forms the doped source layer.

The doped oxide layer may be a boron-doped oxide layer, such as boron-doped silicon oxide, or a phosphorus-doped oxide layer, such as phosphorus-doped silicon oxide. Illustratively, the doped oxide layer may be prepared by CVD, PVD, or the like.

Further, in the step S600, removing the doping source layer includes:

the doped oxide layer may be removed using an HF clean.

Therefore, by forming the doping source layer formed by the doping oxide layer, the preparation process is simpler, and the preparation efficiency of the solar cell is improved.

Illustratively, the doping type of the first doped amorphous silicon layer is determined according to the doping type of the silicon wafer substrate and the forming position on the silicon wafer substrate, and the doping type of the doping source layer is consistent with the doping type of the first doped amorphous silicon layer.

For example, the doping type of the silicon wafer substrate is N-type doping, the first doped amorphous silicon layer is formed on the front surface of the silicon wafer substrate, and the doping type of the first doped amorphous silicon layer can be P-type doping, so that the doping type of the finally prepared doped polycrystalline silicon layer is also P-type doping, and forms a PN junction with the N-type doped silicon wafer substrate, and the doped polycrystalline silicon layer with a heavily doped region can be used as a selective emitter of the solar cell.

For another example, the doping type of the silicon wafer substrate is N-type doping, the first doped amorphous silicon layer is formed on the back surface of the silicon wafer substrate, and the doping type of the first doped amorphous silicon layer can be N-type doping, so that the doping type of the finally prepared doped polycrystalline silicon layer is also N-type doping, and then the tunneling oxide layer and the doped polycrystalline silicon layer can form a passivation contact structure of the solar cell, which is beneficial to improving the photoelectric conversion efficiency of the cell.

In practical application, the doping type of the silicon wafer substrate and the forming position of the first doped amorphous silicon layer on the silicon wafer substrate can be determined according to actual needs, and then the doping types of the first doped amorphous silicon layer and the doping source layer are determined.

Illustratively, the forming the first doped amorphous silicon layer into a doped polysilicon layer and the forming the nano amorphous silicon layer into a nano crystalline silicon layer by an annealing process includes:

the method comprises the steps of firstly carrying out oxygen-free annealing treatment at a first temperature, and then carrying out oxidation annealing treatment at a second temperature to enable the first doped amorphous silicon layer to form a doped polycrystalline silicon layer and enable the nano amorphous silicon layer to form a nano crystalline silicon layer, wherein the first temperature is lower than the second temperature.

Specifically, as shown in fig. 2, the temperature may be first raised to 800-860 ℃, the temperature is kept at a low temperature for 5-15 min, the temperature is continuously raised to 880-950 ℃, oxygen is introduced to perform the temperature keeping at a high temperature for 10-30 min, and then the temperature is lowered, so that the first doped amorphous silicon layer is crystallized to form a doped polysilicon layer and the nano amorphous silicon layer is crystallized to form a nano crystalline silicon layer.

The utility model discloses an annealing treatment process at first carries out low temperature anaerobic annealing treatment, then carries out high temperature oxidation annealing, has reduced the damage to the silicon chip basement, has promoted the passivation effect.

Illustratively, the first doped amorphous silicon layer and the doping source layer are formed by chemical vapor deposition, physical vapor deposition or ion implantation.

The chemical vapor deposition, physical vapor deposition or ion implantation process has the characteristics of short process time and low process temperature, and is favorable for improving the preparation quality and efficiency of the battery. For example, the tunneling oxide layer, the first doped amorphous silicon layer and the doping source layer may be formed using the same chemical vapor deposition process. Specifically, the deposition preparation of each film layer can be carried out by adopting a low-temperature synchronous doping process such as PECVD or LPCVD, and the like, without replacing deposition equipment, only by adjusting suitable process parameters. The film layers are prepared by the PECVD or LPCVD process, only one annealing treatment is needed, and the overall process time of the whole preparation method is obviously shorter than that of the traditional diffusion process due to the short process time of the PECVD or LPCVD process, so that the preparation efficiency can be effectively improved. And the PECVD or LPCVD process has low temperature, can reduce the damage to the surface of the silicon wafer substrate, reduces the surface defects and recombination of the silicon wafer substrate, and is favorable for increasing the open-circuit voltage and improving the battery efficiency.

Illustratively, the implanting, by selective doping, the doping element of the doping source layer into a region of the first doped amorphous silicon layer corresponding to the metal gate line to form a heavily doped region includes:

and injecting the doping elements of the doping source layer into the region of the first doping amorphous silicon layer corresponding to the metal grid line through laser selective doping to form a heavily doped region. Illustratively, the laser selective doping can adopt a picosecond laser with the laser wavelength of 355nm, the power of 5-35W and the energy density of 0.01-0.18J/cm ² . The heavily doped region can be quickly formed by laser selective doping, and the selective doping efficiency is improved.

Illustratively, the forming a tunneling oxide layer on a silicon wafer substrate includes:

and forming the tunneling oxide layer on at least one of the front surface or the back surface of the silicon wafer substrate.

For example, a tunneling oxide layer is formed on the front surface of the silicon wafer substrate, and then a nanocrystalline silicon layer formed on the surface of the tunneling oxide layer and a doped polysilicon layer having a heavily doped region formed on the surface of the nanocrystalline silicon layer are also located on the front surface of the silicon wafer substrate, and the doped polysilicon layer may serve as a selective emitter.

For another example, a tunneling oxide layer is formed on the back surface of the silicon wafer substrate, and then a doped polysilicon layer having a heavily doped region is formed on the surface of the tunneling oxide layer and is also located on the back surface of the silicon wafer substrate, and the tunneling oxide layer and the doped polysilicon layer may form a passivation contact structure.

In addition, the tunneling oxide layer can be formed on the front surface and the back surface of the silicon wafer substrate at the same time, so that a doped polycrystalline silicon layer with a heavily doped region is formed on the front surface and the back surface of the silicon wafer substrate at the same time, and the doping types of the silicon wafer substrate and the doped polycrystalline silicon layer can be determined according to actual requirements, so that the finally formed structure is determined to be used as a selective emitter or a passivation contact structure.

The following describes a method for manufacturing the solar cell in detail, taking as an example that the doping type of the silicon wafer substrate is N-type doping, and the tunneling oxide layer is prepared on the front surface of the silicon wafer substrate. Wherein the silicon wafer substrate is an N-type silicon wafer.

First, fig. 3 is a schematic structural diagram of a film layer formed on the front surface of a silicon wafer substrate in a method for manufacturing a solar cell according to the present invention. As shown in fig. 3, the doping source layer is formed by a first oxide layer 17 and a second doped amorphous silicon layer 18 which are stacked, and the first doped amorphous silicon layer 16 and the second doped amorphous silicon layer 18 are both boron doped amorphous silicon layers. In the preparation process of the solar cell, the tunneling oxide layer 14, the nano amorphous silicon layer 15, the first doped amorphous layer 16, the first oxide layer 17 and the second doped amorphous silicon layer 18 form a film structure which is sequentially stacked on the front surface of the silicon wafer substrate 1. In this embodiment, the method for manufacturing a solar cell at least includes the following steps:

(1) And (3) feeding the N-type silicon wafer into a PECVD deposition system, setting the temperature at 400-600 ℃, and simultaneously vacuumizing and detecting leakage of the PECVD deposition cavity.

(2) Forming a tunneling oxide layer on the front side of the silicon wafer substrate: introducing laughing gas with the flow of 2000-10000 sccm into the PECVD deposition cavity, wherein the process pressure is 1000-3500 mtorr, the power is 8000-20000W, the switching ratio is 20-100, and the process time is 1-5 min, so that 1-3 nm of SiO is formed on the front surface of the N-type silicon wafer _x (silicon oxide) film as the tunnel oxide layer.

(3) Forming a nano amorphous silicon layer on the tunneling oxide layer: and after the steps are finished, closing the laughing gas, and then vacuumizing and purging. And (3) introducing 500-5000 sccm silane gas and 100-3000 sccm hydrogen into the cavity, wherein the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 10-50, and the process time is 1-5 min, so that the nano amorphous silicon layer thin film is formed, and the thickness of the thin film is 2-8 nm.

(4) Forming a first doped amorphous silicon layer on the nano amorphous silicon layer: after the steps are completed, the laughing gas is closed, the vacuum pumping and purging are carried out, then 300-5000 sccm of silane gas, 100-4000 sccm of borane gas and 100-3000 sccm of hydrogen gas are introduced into the deposition cavity, the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 10-50, the process time is 5-15 min, and a boron-doped amorphous silicon layer with low doping concentration is formed on the surface of the nano amorphous silicon layer and is used as the first doped amorphous silicon layer.

(5) Forming the first oxide layer on the surface of the first doped amorphous silicon layer: and after the steps are finished, closing the gas and vacuumizing and purging. Laughing gas with the flow of 2000-10000 sccm is introduced into the deposition cavity, the process pressure is 1000-3500 mtorr, the power is 8000-20000W, the switching ratio is 20-100, the process time is 1-5 min, and 1-3 nm of SiO is formed on the surface of the first doped amorphous silicon layer _x And a thin film as the first oxide layer.

(6) Forming the second doped amorphous silicon layer on the surface of the first oxide layer: and after the steps are finished, closing the gas and then vacuumizing and purging. And introducing 300-5000 sccm of silane gas, 200-4000 sccm of borane gas and 100-3000 sccm of hydrogen into the deposition cavity, wherein the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 15-50, and the process time is 10-25 min, so that a boron-doped amorphous silicon layer with high doping concentration is formed on the surface of the first oxide layer and is used as the second doped amorphous silicon layer.

(7) Through selective doping, doping elements of the doping source layer are injected into the region of the first doping amorphous silicon layer corresponding to the metal grid line to form a heavy doping region: selectively doping the second doped amorphous silicon layer and the first doped amorphous silicon layer by laser, specifically, laser processing the region corresponding to the metal gate line on the second doped amorphous silicon layer, pushing the doping elements of the second doped amorphous silicon layer into the first doped amorphous silicon layer by using laser energy, and doping the first doped amorphous silicon layer with the doping elementsAnd the impurity amorphous silicon layer and the region corresponding to the metal grid line form a heavily doped region. Wherein, a picosecond laser with the laser wavelength of 355nm can be selected for carrying out laser selective doping, the power is 5-35W, and the energy density is 0.01-0.18J/cm ² In this embodiment, the doping element is boron.

(8) Forming the first doped amorphous silicon layer into a doped polycrystalline silicon layer by annealing treatment, and forming the nano amorphous silicon layer into a nano crystalline silicon layer: and (3) sending the N-type silicon wafer after the process is finished into an annealing furnace for annealing, wherein during annealing, the temperature is firstly increased to 800-860 ℃, the temperature is kept constant for 5-15 min at low temperature, the temperature is continuously increased to 880-950 ℃, oxygen is introduced for keeping the temperature constant for 10-30 min at high temperature, then the temperature is reduced, the first doped amorphous silicon layer and the second doped amorphous silicon layer are crystallized to form a doped polycrystalline silicon layer, and the nano amorphous silicon layer forms a nano crystalline silicon layer.

(9) Removing the doping source layer: and performing groove etching on the N-type silicon wafer after the annealing treatment, removing the boron-doped polycrystalline silicon layer with high doping concentration on the top layer on the front surface, namely removing the doped polycrystalline silicon layer formed by the second doped amorphous silicon layer, etching the back surface to form a polished surface, and finally removing the first oxidation layer and the oxidation layer on the surface of the N-type silicon wafer through HF cleaning.

Second, fig. 4 is a second schematic structural diagram of a film layer formed on the front surface of the silicon wafer substrate in the method for manufacturing a solar cell according to the present invention. As shown in fig. 4, the doping source layer may be formed of a doped oxide layer 19, the doped oxide layer 19 may be a boron doped oxide layer, such as boron doped silicon oxide, and the first doped amorphous silicon layer 16 may be a boron doped amorphous silicon layer. In the preparation process of the solar cell, the tunneling oxide layer 14, the nano amorphous silicon layer 15, the first doped amorphous layer 16 and the doped oxide layer 19 form a film structure which is sequentially stacked on the front surface of the silicon wafer substrate 1. In this embodiment, the method for manufacturing a solar cell at least includes the following steps:

(1) And (3) sending the N-type silicon wafer into a PECVD deposition system, setting the temperature at 400-600 ℃, and simultaneously vacuumizing and detecting the leakage of the PECVD deposition cavity.

(2) In siliconForming a tunneling oxide layer on a substrate: introducing laughing gas with the flow of 2000-10000 sccm into the PECVD deposition cavity, wherein the process pressure is 1000-3500 mtorr, the power is 8000-20000W, the switching ratio is 20-100, and the process time is 1-5 min, so that 1-3 nm of SiO is formed on the front surface of the N-type silicon wafer _x And the film is used as the tunneling oxide layer.

(3) Forming a nano amorphous silicon layer on the tunneling oxide layer: and (4) after the steps are finished, closing the laughing gas, and vacuumizing and purging. And (3) introducing 500-5000 sccm silane gas and 100-3000 sccm hydrogen into the cavity, wherein the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 10-50, and the process time is 1-5 min, so that the nano amorphous silicon layer film is formed, and the thickness is 2-8 nm.

(5) Forming the doped oxide layer on the surface of the first doped amorphous silicon layer: and after the steps are finished, closing the gas, and vacuumizing and purging. Introducing silane gas of 300-5000 sccm, borane gas of 200-4000 sccm, hydrogen of 100-3000 sccm and laughing gas of 2000-15000 sccm into the cavity, wherein the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 15-50, and the process time is 10-25 min, so that boron-doped silicon oxide with high doping concentration is formed on the surface of the first doped amorphous silicon layer and is used as the doped oxide layer.

(6) Through selective doping, doping elements of the doping source layer are injected into a region of the first doping amorphous silicon layer corresponding to the metal grid line to form a heavy doping region: selectively doping the doped oxide layer and the first doped amorphous silicon layer, specifically, laser processing the region of the doped oxide layer corresponding to the metal gate line, and doping oxygen by using laser energyAnd the doping element of the layer advances the first doped amorphous silicon layer, and a heavily doped region is formed in the region of the first doped amorphous silicon layer corresponding to the metal grid line. Wherein, a picosecond laser with the laser wavelength of 355nm can be selected for carrying out laser selective doping, the power is 5-35W, and the energy density is 0.01-0.18J/cm ² . In this embodiment, the doping element is boron.

(7) Forming the first doped amorphous silicon layer into a doped polycrystalline silicon layer by annealing treatment, and forming the nano amorphous silicon layer into a nano crystalline silicon layer: and (3) conveying the silicon wafer substrate after the process is finished into an annealing furnace for annealing treatment, wherein during annealing, the temperature is firstly increased to 800-860 ℃, the temperature is kept constant for 5-15 min at a low temperature, the temperature is continuously increased to 880-950 ℃, oxygen is introduced for keeping the temperature at a high temperature for 10-30 min, then the temperature is reduced, the first doped amorphous silicon layer is crystallized to form a doped polycrystalline silicon layer, and the nano amorphous silicon layer forms a nano crystalline silicon layer.

(8) Removing the doping source layer: and (3) performing chain HF cleaning on the N-type silicon wafer after the process is finished, removing boron-doped silicon oxide with high doping concentration at the top layer, namely removing the doped oxide layer, and then etching the back of the N-type silicon wafer to form a polished surface.

In the two embodiments, the method for manufacturing a solar cell further includes:

before a tunneling oxide layer is formed on a silicon wafer substrate, texturing pretreatment is carried out on the surface of the silicon wafer substrate to form a pyramid-shaped textured structure.

The preparation method of the solar cell further comprises the following steps:

preparing a back passivation contact structure on the back of the silicon wafer substrate;

removing the winding plating on the front surface of the silicon chip substrate and cleaning;

plating a passivation layer consisting of a silicon oxide layer and an aluminum oxide layer on the front surface of the silicon wafer substrate, and plating silicon nitride layers on the two surfaces of the silicon wafer substrate;

and screen printing to form a front electrode and a back electrode of the silicon chip substrate.

The following describes a method for manufacturing the solar cell in detail, taking as an example that the doping type of the silicon wafer substrate is N-type doping, and the tunneling oxide layer is prepared on the back side of the silicon wafer substrate. Wherein the silicon wafer substrate is an N-type silicon wafer.

First, fig. 5 is a schematic structural diagram of a film layer formed on the back surface of a silicon wafer substrate in a method for manufacturing a solar cell according to the present invention. As shown in fig. 5, the doping source layer is formed by a first oxide layer 17 and a second doped amorphous silicon layer 18 which are stacked, the first doped amorphous silicon layer 16 and the second doped amorphous silicon layer 18 are phosphorus doped amorphous silicon layers, and the tunneling oxide layer 14, the nano amorphous silicon layer 15, the first doped amorphous layer 16, the first oxide layer 17 and the second doped amorphous silicon layer 18 form a sequentially stacked film structure on the back surface of the silicon wafer substrate 1. In this embodiment, the method for manufacturing a solar cell at least includes the following steps:

(2) Forming a tunneling oxide layer on the back of the silicon wafer substrate: introducing laughing gas with the flow of 2000-10000 sccm into the PECVD deposition cavity, wherein the process pressure is 1000-3500 mtorr, the power is 8000-20000W, the switching ratio is 20-100, and the process time is 1-5 min, so that 1-3 nm of SiO is formed on the back of the N-type silicon wafer _x And the thin film is used as a tunneling oxide layer.

(3) Forming a nano amorphous silicon layer on the tunneling oxide layer: and (4) after the steps are finished, closing the laughing gas, and vacuumizing and purging. And (3) introducing 500-5000 sccm silane gas and 100-3000 sccm hydrogen into the cavity, wherein the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 10-50, and the process time is 1-5 min, so that the nano amorphous silicon layer thin film is formed, and the thickness of the thin film is 2-8 nm.

(4) Forming a first doped amorphous silicon layer on the nano amorphous silicon layer: after the steps are completed, the laughing gas is closed, then the vacuum pumping and purging are carried out, then 500-5000 sccm of silane gas, 100-3000 sccm of phosphine gas and 100-3000 sccm of hydrogen gas are introduced into the deposition cavity, the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 10-50, the process time is 5-15 min, and a phosphorus-doped amorphous silicon layer with low doping concentration is formed on the surface of the nano amorphous silicon layer and is used as a first doped amorphous silicon layer.

(5) Forming the first oxide layer on the surface of the first doped amorphous silicon layer: and after the steps are finished, closing the gas and vacuumizing and purging. 2000-12000 sccm of laughing gas is introduced into the deposition cavity, the process pressure is 1000-3500 mtorr, the power is 8000-20000W, the on-off ratio is 20-100, the process time is 1-5 min, and 1-3 nm of SiO is formed on the surface of the first doped amorphous silicon layer _x And the film is used as a first oxide layer.

(6) Forming the second doped amorphous silicon layer on the surface of the first oxide layer, so that the nano amorphous silicon layer forms a nano crystalline silicon layer: and after the steps are finished, closing the gas and then vacuumizing and purging. And (2) introducing silane gas of 500-5000 sccm, phosphane gas of 300-3000 sccm and hydrogen of 100-3000 sccm into the deposition cavity, wherein the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 10-50, and the process time is 10-25 min, so that a phosphorus-doped amorphous silicon layer with high doping concentration is formed on the surface of the first oxide layer and is used as a second doped amorphous silicon layer.

(7) Through selective doping, doping elements of the doping source layer are injected into a region of the first doping amorphous silicon layer corresponding to the metal grid line to form a heavy doping region: and carrying out laser selective doping on the second doped amorphous silicon layer and the first doped amorphous silicon layer, specifically, carrying out laser processing on a region corresponding to the metal grid line on the second doped amorphous silicon layer, pushing doping elements of the second doped amorphous silicon layer into the first doped amorphous silicon layer by using laser energy, and forming a heavily doped region in the region corresponding to the metal grid line on the first doped amorphous silicon layer. Wherein, a picosecond laser with the laser wavelength of 355nm can be selected for carrying out laser selective doping, the power is 5-35W, and the energy density is 0.01-0.18J/cm ² . In this embodiment, the doping element is phosphorus.

(8) Forming the first doped amorphous silicon layer into a doped polycrystalline silicon layer by annealing treatment, and forming the nano amorphous silicon layer into a nano crystalline silicon layer: sending the N-type silicon wafer after the process is finished into an annealing furnace for annealing treatment, wherein during annealing, the temperature is firstly increased to 800-860 ℃, the temperature is kept constant for 5-15 min at low temperature, the temperature is continuously increased to 880-950 ℃, oxygen is introduced for keeping the temperature at high temperature for 10-30 min, then the temperature is reduced, the first doped amorphous silicon layer and the second doped amorphous silicon layer are both crystallized to form a doped polycrystalline silicon layer, and the nano amorphous silicon layer forms a nano crystalline silicon layer;

(9) Removing the doping source layer: and performing groove etching on the N-type silicon wafer after the annealing treatment, and removing the phosphorus-doped polycrystalline silicon layer with high doping concentration on the back, namely removing the doped polycrystalline silicon layer formed by the second doped amorphous silicon layer.

Second, fig. 6 is a second schematic structural diagram of a film layer prepared on the back surface of the silicon wafer substrate in the method for preparing a solar cell according to the present invention. As shown in fig. 6, the doping source layer is formed by a doped oxide layer 19, the doped oxide layer 19 may be a phosphorus-doped oxide layer, such as phosphorus-doped silicon oxide, the first doped amorphous silicon layer 16 may be a phosphorus-doped amorphous silicon layer, and the tunneling oxide layer 14, the nano amorphous silicon layer 15, the first doped amorphous layer 16 and the doped oxide layer 19 form a sequentially stacked film structure on the back surface of the silicon wafer substrate 1. In this embodiment, the method for manufacturing a solar cell at least includes the following steps:

(2) Forming a tunneling oxide layer on a silicon wafer substrate: introducing laughing gas with the flow rate of 2000-12000 sccm into the PECVD deposition cavity, wherein the process pressure is 1000-3500 mtorr, the power is 8000-20000W, the switching ratio is 20-100, and the process time is 1-5 min, so that 1-3 nm of SiO is formed on the back surface of the N-type silicon wafer _x The film is used as a tunneling oxide layer.

(5) Forming a doped oxide layer on the first doped amorphous silicon layer: and after the steps are finished, closing the gas, and vacuumizing and purging. And (2) introducing silane gas of 500-5000 sccm, phosphane gas of 300-3000 sccm, hydrogen of 100-3000 sccm and laughing gas of 2000-15000 sccm into the cavity, wherein the process pressure is 1000-3500 mtorr, the power is 15000-30000W, the switching ratio is 15-50, and the process time is 10-25 min, so that the phosphorus-doped silicon oxide with high doping concentration is formed on the surface of the first doped amorphous silicon layer to be used as a doped oxide layer.

(6) Through selective doping, doping elements of the doping source layer are injected into a region of the first doping amorphous silicon layer corresponding to the metal grid line to form a heavy doping region: and carrying out laser doping treatment on the doped oxide layer and the first doped amorphous silicon layer, specifically, carrying out laser processing on the region of the doped oxide layer corresponding to the metal grid line, pushing the doping elements of the doped oxide layer into the first doped amorphous silicon layer by using laser energy, and forming a heavily doped region in the region of the first doped amorphous silicon layer corresponding to the metal grid line. Wherein, a picosecond laser with the laser wavelength of 355nm can be selected for carrying out laser selective doping, the power is 5-35W, and the energy density is 0.01-0.18J/cm ² . In this embodiment, the doping element is phosphorus.

(8) Removing the doping source layer: and performing chain type HF cleaning on the N-type silicon wafer after the process is finished, removing the phosphorus-doped silicon oxide with high doping concentration on the back, namely removing the doped oxide layer, and simultaneously removing the oxide layer on the surface of the N-type silicon wafer through HF cleaning.

In the above two embodiments, the method for manufacturing a solar cell further includes:

before a tunneling oxide layer is formed on a silicon wafer substrate, performing alkali polishing on the back of the silicon wafer substrate; and (3) performing texturing pretreatment on the front side of the silicon wafer substrate to form a pyramid-shaped textured structure.

The preparation method of the solar cell further comprises the following steps:

forming a doping layer on the front surface of the silicon wafer substrate in a boron diffusion, PECVD, LPCVD or ion implantation mode and the like to be used as a PN junction, namely an emitter;

The utility model provides a solar cell's preparation method, except above-mentioned embodiment, also can be applied to the condition that the silicon chip basement is P type silicon chip, for example, can form the doping polycrystalline silicon layer that has selective phosphorus doping in the front of P type silicon chip, perhaps can form the doping polycrystalline silicon layer that has selective phosphorus or boron doping at the back of P type silicon chip.

The utility model also provides a solar cell, include: the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer are sequentially stacked on the silicon wafer substrate, the doped polycrystalline silicon layer comprises a heavily doped region and a lightly doped region outside the heavily doped region, and the heavily doped region is used for arranging a metal grid line. The surface of the silicon wafer substrate is provided with the tunneling oxide layer, the surface of the tunneling oxide layer is provided with the nanocrystalline silicon layer, and the surface of the nanocrystalline silicon layer is provided with the doped polycrystalline silicon layer. By adding the nanocrystalline silicon layer between the tunneling oxide layer and the doped polycrystalline silicon layer, the thickness of the doped polycrystalline silicon can be properly reduced, and the ineffective absorption loss on the surface of the solar cell can be further reduced.

The solar cell can be prepared by any one of the above methods for preparing a solar cell.

Since the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer can form a passivation contact structure, the solar cell can be a TOPCon cell, and the surface of the solar cell has excellent transmission contact characteristics.

Illustratively, the nanocrystalline silicon layer may be a doped nanocrystalline silicon layer. The thickness of the nanocrystalline silicon layer may be 2-8 nm. The nanocrystalline silicon layer has a lower extinction coefficient, and can remarkably reduce the absorption of light and reduce the optical absorption loss.

Illustratively, the doping type of the silicon wafer substrate is N-type doping or P-type doping.

Illustratively, the doping type of the doped polysilicon layer is N-type doping or P-type doping. When the doping type of the doped polycrystalline silicon layer is N-type doping, a phosphorus doped polycrystalline silicon layer can be adopted, and when the doping type of the doped polycrystalline silicon layer is P-type doping, a boron doped polycrystalline silicon layer can be adopted. The doping type of the doped polysilicon layer can be determined according to the doping type of the silicon wafer substrate and the setting position on the silicon wafer substrate. The doped polycrystalline silicon layer comprises a heavily doped region and a lightly doped region, the doped polycrystalline silicon layer has a selective doping effect, the heavily doped region is arranged on the doped polycrystalline silicon layer, damage to a silicon wafer substrate is avoided, in addition, the heavily doped region is used for arranging metal grid lines and corresponds to a metal contact region of the silicon wafer substrate, contact resistance can be effectively reduced, filling factors are improved, the lightly doped region outside the heavily doped region corresponds to a non-metal contact region of the silicon wafer substrate, the passivated contact effect is good, and improvement of the battery efficiency is facilitated.

Illustratively, the tunneling oxide layer is made of silicon oxide, and the tunneling oxide layer may be a silicon oxide layer with a thickness of 1 to 3nm. The tunneling oxide layer can improve the passivation effect of the surface of the silicon wafer substrate.

Illustratively, the tunneling oxide layer, the nanocrystalline silicon layer and the doped polysilicon layer are disposed on at least one of a front surface or a back surface of the silicon wafer substrate.

Fig. 7 is a schematic structural diagram of a solar cell provided by the present invention.

In the embodiment of the solar cell shown in fig. 7, for example, the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer are disposed on the front surface of the silicon wafer substrate, a passivation layer, a front anti-reflection layer and a front electrode are sequentially stacked on the surface of the doped polycrystalline silicon layer, and a back passivation contact structure, a back anti-reflection layer and a back electrode are sequentially stacked on the back surface of the silicon wafer substrate. The passivation layer is arranged on the surface of the doped polycrystalline silicon layer, the front antireflection layer is arranged on the surface of the passivation layer, the front electrode is arranged on the surface of the front antireflection layer, and the front electrode penetrates through the front antireflection layer and the passivation layer and is in contact with the heavily doped region of the doped polycrystalline silicon layer. The back of the silicon chip substrate is provided with the back passivation contact structure, the surface of the back passivation contact structure is provided with the back antireflection layer, the surface of the back antireflection layer is provided with the back electrode, and the back electrode penetrates through the back antireflection layer and contacts with the back passivation contact structure.

Illustratively, the passivation layer includes a silicon oxide layer and an aluminum oxide layer which are stacked. The silicon oxide layer is arranged on the surface of the doped polycrystalline silicon layer, and the aluminum oxide layer is arranged on the surface of the silicon oxide layer.

Illustratively, the front anti-reflective layer and the back anti-reflective layer are both silicon nitride layers.

In this embodiment, as shown in fig. 7, the solar cell includes a front side tunneling oxide layer 2, a nano-crystalline silicon layer 3, a front side doped polysilicon layer 4, a silicon oxide layer 7, an aluminum oxide layer 8, a front side silicon nitride layer 9, and a front side electrode 11 sequentially disposed on the front side of a silicon wafer substrate 1, and a back side tunneling oxide layer 5, a back side doped polysilicon layer 6, a back side silicon nitride layer 10, and a back side electrode 12 sequentially disposed on the back side of the silicon wafer substrate 1.

The front doped polysilicon layer 4 includes a heavily doped region 13 and a lightly doped region outside the heavily doped region 13, the heavily doped region 13 is used for setting a metal gate line, and the heavily doped region 13 is in contact with the front electrode 11. The front side tunneling oxide layer 2, the nanocrystalline silicon layer 3 and the front side doped polycrystalline silicon layer 4 form a front side selective emitter, and the back side tunneling oxide layer 5 and the back side doped polycrystalline silicon layer 6 form a back side passivation contact structure. The back doped polysilicon layer 6 is in contact with the back electrode 12.

For example, the silicon wafer substrate 1 may be an N-type silicon wafer, and correspondingly, the front-side doped polysilicon layer 4 may be a boron-doped polysilicon layer, and the back-side doped polysilicon layer 6 may be a phosphorus-doped polysilicon layer.

In the embodiment of the solar cell shown in fig. 8, for example, the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer are disposed on the back surface of the silicon wafer substrate, a back antireflection layer and a back electrode are sequentially stacked on the surface of the doped polycrystalline silicon layer, and a doped layer, a passivation layer, a front antireflection layer and a front electrode are sequentially stacked on the front surface of the silicon wafer substrate. The back antireflection layer is arranged on the surface of the doped polycrystalline silicon layer, the back electrode is arranged on the surface of the back antireflection layer, and the back electrode penetrates through the back antireflection layer and is in contact with the heavily doped region of the doped polycrystalline silicon layer. The front surface of the silicon wafer substrate is provided with the doping layer, the surface of the doping layer is provided with the passivation layer, the surface of the passivation layer is provided with the front surface antireflection layer, the surface of the front surface antireflection layer is provided with the front surface electrode, and the front surface electrode penetrates through the front surface antireflection layer and the passivation layer and is in contact with the doping layer.

In this embodiment, as shown in fig. 8, the solar cell includes a doping layer 2a, a silicon oxide layer 6a, an aluminum oxide layer 7a, a front silicon nitride layer 8a, and a front electrode 10a sequentially disposed on the front surface of a silicon substrate 1a, and a tunneling oxide layer 3a, a nano-crystalline silicon layer 4a, a doped polysilicon layer 5a, a back silicon nitride layer 9a, and a back electrode 11a sequentially disposed on the back surface of the silicon substrate 1a.

The doped polysilicon layer 5a includes a heavily doped region 12a and a lightly doped region outside the heavily doped region 12a, the heavily doped region 12a is used for setting a metal gate line, and the heavily doped region 12a is in contact with the back electrode 11a. The tunneling oxide layer 3a, the nanocrystalline silicon layer 4a and the doped polycrystalline silicon layer 5a form a passivation contact structure on the back surface. The doped polysilicon layer 5a is in contact with the back electrode 11a.

For example, the silicon wafer substrate 1 may be an N-type silicon wafer, and correspondingly, the doped layer 2a may be a boron doped layer, and the doped polysilicon layer 5a may be a phosphorus doped polysilicon layer.

To sum up, the utility model provides a solar cell, firstly, can set up the tunneling oxide layer in the front of silicon chip basement, nanocrystalline silicon layer and doping polycrystalline silicon layer, can regard as positive projecting pole, the heavy doping region that the metal contact zone of silicon chip basement corresponds can reduce contact resistance, promote the fill factor, and the tunneling oxide layer that the non-metal contact zone of silicon chip basement corresponds, nanocrystalline silicon layer and the doping polycrystalline silicon layer of lower concentration can constitute passivation contact structure, increase the positive passivation effect of silicon chip basement, promote open circuit voltage, and simultaneously, can also set up passivation contact structure at the back of silicon chip basement, the photoelectric conversion efficiency of battery has further been promoted; and secondly, a tunneling oxide layer, a nanocrystalline silicon layer and a doped polycrystalline silicon layer can be arranged on the back of the silicon wafer substrate to form a selective doped passivation contact structure, and meanwhile, a doped layer is arranged on the front of the silicon wafer substrate to serve as an emitter, so that the photoelectric conversion efficiency of the battery can be improved through the structural combination design. In addition, the utility model provides a solar cell is the heterojunction structure that a crystal silicon, silicon oxide and polycrystalline silicon constitute, has the passivation contact characteristic of selectivity doping, has improved the battery performance greatly.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims

1. A solar cell, comprising: the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer are sequentially stacked on the silicon wafer substrate, the doped polycrystalline silicon layer comprises a heavily doped region and a lightly doped region outside the heavily doped region, and the heavily doped region is used for arranging a metal grid line.

2. The solar cell of claim 1, wherein the nanocrystalline silicon layer is a doped nanocrystalline silicon layer.

3. The solar cell of claim 1, wherein the doping type of the silicon wafer substrate is N-type doping or P-type doping.

4. The solar cell of claim 1, wherein the doped polysilicon layer is doped N-type or P-type.

5. The solar cell of claim 1, wherein the tunneling oxide layer is made of silicon oxide and has a thickness of 1 to 3nm.

6. The solar cell of any one of claims 1 to 5, wherein the tunneling oxide layer, the nanocrystalline silicon layer, and the doped polycrystalline silicon layer are disposed on at least one of the front side or the back side of the silicon wafer substrate.

7. The solar cell according to claim 6, wherein the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer are disposed on the front surface of the silicon wafer substrate, a passivation layer, a front anti-reflection layer and a front electrode are sequentially stacked on the surface of the doped polycrystalline silicon layer, and a back passivation contact structure, a back anti-reflection layer and a back electrode are sequentially stacked on the back surface of the silicon wafer substrate.

8. The solar cell according to claim 6, wherein the tunneling oxide layer, the nanocrystalline silicon layer and the doped polycrystalline silicon layer are disposed on a back surface of the silicon wafer substrate, a back antireflection layer and a back electrode are sequentially stacked on a surface of the doped polycrystalline silicon layer, and a doped layer, a passivation layer, a front antireflection layer and a front electrode are sequentially stacked on a front surface of the silicon wafer substrate.

9. The solar cell according to claim 7 or 8, wherein the passivation layer comprises a silicon oxide layer and an aluminum oxide layer stacked.

10. The solar cell of claim 7 or 8, wherein the front side anti-reflective layer and the back side anti-reflective layer are both silicon nitride layers.