CN111416011B - P-type PERC crystalline silicon solar cell and preparation method thereof - Google Patents

Abstract

The invention provides a p-type PERC crystalline silicon solar cell and a preparation method thereof, wherein a silicon oxide layer and a polycrystalline silicon layer with a suede structure are grown on the front side of a p-type crystalline silicon wafer, and the preparation method comprises the following steps: texturing the surface of the silicon wafer to form a pyramid textured surface which is distributed randomly; high temperature phosphorus diffusion to form n ⁺ Emitter, and removing front-side phosphorosilicate glass; forming the silicon oxide layer by thermal oxidation; and depositing an intrinsic polycrystalline silicon layer, and carrying out phosphorus doping on the intrinsic polycrystalline silicon layer by high-temperature diffusion to obtain a full-area TOPCon structure with carrier selective contact. The invention has the beneficial effects that: effectively reduces the recombination of current carriers on the front surface of the battery, and the preparation process can be compatible with the existing PERC production line without laser selective doping equipment.

Description

A kind of p-type PERC crystalline silicon solar cell and its preparation method

technical field

The present application relates to the technical field of crystalline silicon solar cells, in particular to a p-type passivated emitter rear cell (PERC).

Background technique

Crystalline silicon (c-Si) solar cells occupy a dominant position in the current global photovoltaic market due to their high conversion efficiency and mature industrial technology, and traditional crystalline silicon aluminum back field (Al-BSF) cells are gradually being replaced by PERC cells. substitute. The traditional Al-BSF battery has serious carrier recombination due to the direct contact of the metal semiconductor on the back, and at the same time lacks the reflection of the dielectric film layer on the long-wave band. The PERC battery can greatly reduce the This photoelectric loss is eliminated, thereby increasing the absolute conversion efficiency by 1 to 2%. After continuous optimization, the mass production efficiency of monocrystalline PERC cells has increased from 20% in 2014 to over 22% in 2019. However, it must be pointed out that when the conversion efficiency of PERC cells increases, especially after it exceeds 22.5%, the passivation of the front surface, which used to have no major impact, becomes more and more important. German scientific research institutes have analyzed the efficiency loss of PERC cells with a conversion efficiency of 22%, and found that the carrier recombination loss mainly occurs in the uniform diffusion area and selective diffusion area of the emitter. Therefore, if only the selective emitter is used on the front surface of the battery, the advantages of further improving the efficiency of the PERC battery cannot be fully utilized.

In recent years, the popular tunneling oxide passivation contact (TOPCon) technology has found a feasible solution for us. The TOPCon structure consists of an ultra-thin silicon oxide (SiO ₂ ) layer and a doped polysilicon (poly-Si) layer, which has the advantages of full-area passivation contacts and compatibility with the high-temperature sintering process of PERC production lines. However, most of TOPCon's research results are based on n-type crystalline silicon cells, which are used as the back surface field of n-type substrates, and the annual production capacity of n-type crystalline silicon cells is currently less than 5GWp, which is much lower than that of p-type crystalline silicon cells. Silicon-based PERC cell capacity (>100GWp). A small number of scientific research teams have begun to try to prepare TOPCon on p-type substrates, proving the high efficiency potential of the combination of TOPCon structure and p-type crystalline silicon cells. silicon substrate. The passivation performance of TOPCon is very sensitive to the textured surface, and the parasitic absorption of poly-Si itself also seriously affects the wide application of TOPCon. Therefore, the preparation of high-performance TOPCon on the front textured structure of p-type crystalline silicon substrate has important academic and industrial value for the further development of high-efficiency PERC cells.

Contents of the invention

The object of the present invention is to provide a low-cost and high-efficiency p-type PERC crystalline silicon solar cell with front full-area passivation and a preparation method.

Low-pressure chemical vapor deposition (LPCVD) equipment is used to grow ultra-thin silicon oxide and polysilicon layers with a textured structure on the front of the p-type silicon wafer.

Include the following steps:

Step 1, making texture on the surface of the silicon chip to form randomly distributed pyramid texture;

Step 2, high-temperature phosphorus diffusion to form n ⁺ emitter, and then remove the front-side phosphosilicate glass;

Step 3, thermal oxidation to form an ultra-thin and dense silicon oxide layer;

Step 4, depositing an intrinsic polysilicon layer and performing phosphorus doping on the polysilicon by high-temperature diffusion to obtain a full-area TOPCon structure with carrier selective contact.

Further, in the step 1, the silicon wafer is placed in a potassium hydroxide solution with a volume ratio of 3%, and the soaking time is 420s, and the difference in the corrosion rate of different crystal planes is carried out by using the potassium hydroxide solution. Pyramid texture is formed to form randomly distributed pyramid textures with a size of 1-2 μm, and then the metal ions and oxide layers are removed with hydrochloric acid and hydrofluoric acid solutions, and standard RCA cleaning is performed.

Further, in the step 2, the silicon wafers are placed back-to-back in pairs and placed in a high-temperature tube furnace for phosphorus diffusion, so that the inside of the silicon wafers that are in contact with each other cannot be effectively treated like the outside. Diffused; forming an n ⁺ emitter with a surface sheet resistance of 130Ω/□; then removing the front phosphosilicate glass with a hydrofluoric acid solution.

Further, in the step 3, the silicon wafer is placed in a tubular LPCVD device, and thermally oxidized at 580°C for 10 minutes to form an ultra-thin and dense silicon oxide layer; the silicon oxide layer is observed with a transmission electron microscope The thickness is 1.5nm.

Further, in the step 4, use the same tube furnace as the LPCVD equipment to deposit the intrinsic polysilicon layer by thermal decomposition of silane, the deposition temperature is 610°C, and the deposition time is 3 to 15 minutes; when the deposition time is 5 minutes, the corresponding The thickness of the polysilicon is 25nm; then the silicon wafers are also placed in pairs back to back, with the n ⁺ emitter facing outward, and the polysilicon is doped with phosphorus by high temperature diffusion, and the crystallinity of the polysilicon is improved by annealing and the phosphorus ions are fully activated. Full-area TOPCon structure with carrier-selective contacts, annealed at 780 °C.

Further, after the step 4, the following steps are included:

Step 5, prepare a mixed acid solution with a volume fraction of 68% nitric acid and a volume fraction of 50% hydrofluoric acid in a volume ratio of 3:1, etch the back surface and edge of the silicon wafer after the previous step to remove the edge The p-n junction makes the upper and lower surfaces of the silicon wafer insulated from each other; the subsequent potassium hydroxide solution removes the porous silicon on the back to form a polished surface, and then uses the hydrofluoric acid solution to treat the front of the silicon wafer with phosphorus-silicon glass;

Step 6, put the silicon wafer into another tube furnace, feed ammonia gas, connect the high-frequency power supply and deposit hydrogenated silicon nitride anti-reflection film, aluminum oxide and hydrogenated nitrogen on the front and rear surfaces of the battery respectively by PECVD process Silicon oxide laminated passivation film;

Step 7, printing Ag paste and Al paste electrodes on the front and back surfaces of the silicon wafer respectively, and performing co-sintering in an infrared belt sintering furnace to form a good ohmic contact.

A crystalline silicon solar cell is an improvement of a p-type PERC crystalline silicon solar cell, and a TOPCon structure is superimposed on a textured structure on the front side.

Further, the material of the polysilicon layer in the TOPCon structure is phosphorus-doped polysilicon.

Further, in the TOPCon structure, the silicon oxide layer has a thickness of 1.5 nm, and the polysilicon layer has a thickness of 25 nm.

The beneficial effects of the present application are: first, compared with the current heavily doped selective emitter, the use of a full-area TOPCon structure can effectively reduce the recombination of carriers on the front surface of the battery, not just reduce the recombination of carriers at the metal-semiconductor interface. carrier recombination. Second, ultra-thin silicon oxide and phosphorus-doped polysilicon are prepared based on the same tube furnace as the LPCVD equipment to shorten the contact time with air and avoid the formation of a natural oxide layer. Third, the preparation process of the cell is compatible with the existing PERC production line, and does not require laser selective doping equipment, and does not increase the cost of the cell while obtaining high efficiency.

Description of drawings

Fig. 1 is a p-type PERC crystalline silicon solar cell structure schematic diagram of a preferred embodiment of the present application;

Fig. 2 is a hidden open circuit voltage and phosphorus impurity advance time relation figure of a preferred embodiment of the present application;

Fig. 3 is a comparison diagram of electrical parameters of a preferred embodiment of the present application;

Among them, 1-hydrogenated silicon nitride anti-reflection layer, 2-front-side Ag electrode, 3-phosphorus-doped polysilicon layer, 4-ultra-thin silicon oxide layer, 5-emitter formed by high-temperature phosphorus diffusion, 6-aluminum oxide film, 7-hydrogenated silicon nitride passivation film, 8-p-type crystalline silicon substrate, 9-back Al electrode.

Detailed ways

The following describes the preferred embodiments of the present application with reference to the accompanying drawings to make the technical content clearer and easier to understand. The present application can be embodied in many different forms of embodiments, and the protection scope of the present application is not limited to the embodiments mentioned herein.

A p-type PERC crystalline silicon solar cell with a front-side full-area passivation structure is produced by the following steps:

In the first step, an industrial-grade p-type Cz monocrystalline silicon wafer with a crystal orientation of (100) is used, the thickness of the silicon wafer is 180 μm, and the resistivity is ~1Ω·cm. First, the silicon wafer is pretreated, including removing the damaged layer, and the original silicon wafer is soaked in a potassium hydroxide solution (4% by volume) at a temperature of 75 ° C for 150 seconds to remove the damage on the surface of the silicon wafer layer.

In the second step, the silicon wafer with the damaged layer removed is placed in a potassium hydroxide solution (3% by volume), and the soaking time is 420s, and the random pyramid texturing of the surface is carried out by utilizing the difference in the corrosion rate of different crystal planes by the potassium hydroxide solution , to form randomly distributed pyramid suede with a size of 1-2 μm, remove metal ions and oxide layers with hydrochloric acid and hydrofluoric acid solutions, and perform standard RCA cleaning.

In the third step, the textured silicon wafers are placed in pairs back to back and placed in a high-temperature tube furnace for phosphorus diffusion, so that the inside of the silicon wafers that are in contact with each other cannot be effectively diffused like the outside. An n ⁺ emitter with a surface sheet resistance of 130Ω/□ was formed, and then the front phosphosilicate glass was removed with a hydrofluoric acid solution.

In the fourth step, the diffused silicon wafer is placed in a tubular LPCVD device, and thermally oxidized at 580°C for 10 minutes to form an ultra-thin and dense silicon oxide layer. The silicon oxide layer was observed to have a thickness of 1.5 nm with a transmission electron microscope.

The fifth step is to use the same tube furnace as the LPCVD equipment to deposit the intrinsic polysilicon layer by thermal decomposition of silane. The deposition temperature is 610°C, and the deposition time is 3, 5, and 15 min, respectively. The optimal deposition time is 5 min, corresponding to The polysilicon thickness is 25nm. Then, the silicon wafers are also placed in pairs back to back, with the n ⁺ emitter facing outward, and the polysilicon is doped with phosphorus by high-temperature diffusion, and the crystallinity of the polysilicon is improved by annealing, and the phosphorus ions are fully activated to obtain carrier selectivity. The contacted full-area TOPCon structure was annealed at 780 °C.

In the sixth step, nitric acid (68% by volume) and hydrofluoric acid (50% by volume) are prepared into a mixed acid solution according to the volume ratio of 3:1, and the back surface and edge of the silicon wafer after the previous step are processed. Etching, removing the p-n junction at the edge, so that the upper and lower surfaces of the silicon wafer are insulated from each other; the subsequent potassium hydroxide solution removes the porous silicon on the back to form a polished surface, and then uses a hydrofluoric acid solution to treat the front of the silicon wafer with phosphorus-silicon glass.

In the seventh step, the annealed silicon wafer is put into another tube furnace, and ammonia gas is introduced, and the high-frequency power supply is connected, and the hydrogenated silicon nitride anti-reflection film and the aluminum oxide/hydrogenated silicon nitride film are deposited on the front and rear surfaces of the battery by the PECVD process. Silicon nitride laminated passivation film.

The eighth step, finally, print Ag paste and Al paste electrodes on the front and rear surfaces of the battery by screen printing method, and carry out co-sintering in an infrared belt sintering furnace to form a good ohmic contact.

Figure 1 is a schematic diagram of the structure of the prepared crystalline silicon solar cell, 1 is the hydrogenated silicon nitride anti-reflection layer, 2 is the front Ag electrode, 3 is the phosphorus-doped polysilicon layer, 4 is the ultra-thin silicon oxide layer, and 5 is the high-temperature phosphorus Emitter formed by diffusion, 6 is an aluminum oxide film, 7 is a hydrogenated silicon nitride passivation film, 8 is a p-type crystal silicon substrate, and 9 is an Al electrode on the back.

Figure 2 shows the relationship between the implicit open-circuit voltage (implied-V _OC ) and the phosphorus impurity advance time of the symmetrical structure of the battery when the poly-Si/SiO ₂ /c-Si structure corresponds to the poly-Si deposition time of 3, 5 and 15 min. relation. Among them, the 15min poly-Si is thicker than the 5min poly-Si, and the corresponding advancing time is longer.

Figure 3 shows the comparison of the corresponding solar cell electrical parameters (open circuit voltage V _OC , short circuit current density J _SC , fill factor FF and conversion efficiency Eff) when the deposition time of poly-Si is 5 and 15 min.

It can be seen from Figure 2 that when the deposition time of poly-Si is 5min, the phosphorus doping advance time of 900s has the best effect, and compared with the poly-Si of 3min, the battery has a higher tolerance to the advance time, The process preparation window is wider; for cells with a poly-Si deposition time of 15 min, the J _SC drops significantly due to the light absorption loss of poly-Si, as shown in Figure 3. The solar cell with a full-area TOPCon structure on the front surface can further improve the V _OC compared with the conventional p-type PERC cell, thereby improving the conversion efficiency of the cell.

The preferred specific embodiments of the present application have been described in detail above. It should be understood that those skilled in the art can make many modifications and changes based on the concept of the present application without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present application on the basis of the prior art shall be within the scope of protection defined by the claims.

Claims (2)

1. A method for preparing a p-type PERC crystalline silicon solar cell, characterized in that, the front growth of a p-type crystalline silicon wafer has a thickness of a textured surface and is a silicon oxide layer of 1.5nm and a phosphorus-doped polysilicon layer to form a TOPCon structure , the thickness of the phosphorus-doped polysilicon layer is 25nm, the silicon oxide layer and the phosphorus-doped polysilicon layer are prepared by LPCVD, and there is a hydrogenated silicon nitride anti-reflection layer on the TOPCon structure; the p-type PERC A method for preparing a crystalline silicon solar cell, comprising the following steps: Step 1, making texture on the surface of the silicon chip to form randomly distributed pyramid texture; Step 2, high-temperature phosphorus diffusion to form n ⁺ emitter, and then remove the front-side phosphosilicate glass; Step 3, forming the silicon oxide layer by thermal oxidation; Step 4, depositing an intrinsic polysilicon layer, and performing phosphorus doping on the intrinsic polysilicon layer by high-temperature diffusion to obtain a full-area TOPCon structure with carrier selective contact; Step 5, prepare a mixed acid solution with a volume fraction of 68% nitric acid and a volume fraction of 50% hydrofluoric acid according to a volume ratio of 3:1, etch the back surface and edge of the silicon wafer after the previous step, and remove the edge The p-n junction makes the upper and lower surfaces of the silicon wafer insulated from each other; the subsequent potassium hydroxide solution removes the porous silicon on the back to form a polished surface, and then uses the hydrofluoric acid solution to treat the front of the silicon wafer with phosphorus-silicon glass; Step 6, put the silicon wafer into another tube furnace, feed ammonia gas, connect the high-frequency power supply, and deposit hydrogenated silicon nitride anti-reflection film and aluminum oxide film on the front and rear surfaces of the silicon wafer respectively by PECVD process. and hydrogenated silicon nitride laminated passivation film; Step 7, printing Ag paste and Al paste electrodes on the front and rear surfaces of the silicon wafer respectively, and co-sintering in an infrared belt sintering furnace to form a good ohmic contact; In the step 2, the silicon wafers are placed in a high-temperature tube furnace in a manner of placing back-to-back in pairs, and phosphorus is diffused, so that the inside of the silicon wafers in contact with each other cannot be effectively absorbed like the outside. Diffusion; formation of an n ⁺ emitter with a surface sheet resistance of 130Ω/□; subsequent removal of the front-side phosphosilicate glass with a hydrofluoric acid solution; In the step 3, the silicon wafer is placed in a tubular LPCVD device, and thermally oxidized at 580° C. for 10 minutes to form the silicon oxide layer; the thickness of the silicon oxide layer is observed by a transmission electron microscope. 1.5nm; In the step 4, use the same tube furnace as the LPCVD equipment to deposit the intrinsic polysilicon layer by thermal decomposition of silane, the deposition temperature is 610°C, the deposition time is 5min, and the corresponding intrinsic polysilicon layer thickness is 25nm Then, the silicon wafers are also placed in pairs back to back, with the n ⁺ emitters facing outwards, and the intrinsic polysilicon layer is doped with phosphorus by high-temperature diffusion. To check the crystallinity of the polysilicon layer and fully activate phosphorus ions to obtain a full-area TOPCon structure with carrier selective contact, the annealing temperature is 780°C. 2. the p-type PERC crystalline silicon solar cell preparation method as claimed in claim 1, is characterized in that, in described step 1, described silicon chip is placed in the potassium hydroxide solution that volume ratio is 3%, soaks The time is 420s, and the difference in corrosion rate of different crystal planes is carried out by using potassium hydroxide solution to perform random pyramid texture on the surface to form randomly distributed pyramid textures with a size of 1-2 μm, and then use hydrochloric acid and hydrofluoric acid solutions to remove metal ions respectively and oxide layer, and perform standard RCA cleaning.

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