CN111416011B - P-type PERC crystalline silicon solar cell and preparation method thereof - Google Patents
P-type PERC crystalline silicon solar cell and preparation method thereof Download PDFInfo
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Abstract
The invention provides a p-type PERC crystalline silicon solar cell and a preparation method thereof, wherein a silicon oxide layer and a polycrystalline silicon layer with a suede structure are grown on the front side of a p-type crystalline silicon wafer, and the preparation method comprises the following steps: texturing the surface of the silicon wafer to form a pyramid textured surface which is distributed randomly; high temperature phosphorus diffusion to form n + Emitter, and removing front-side phosphorosilicate glass; forming the silicon oxide layer by thermal oxidation; and depositing an intrinsic polycrystalline silicon layer, and carrying out phosphorus doping on the intrinsic polycrystalline silicon layer by high-temperature diffusion to obtain a full-area TOPCon structure with carrier selective contact. The invention has the beneficial effects that: effectively reduces the recombination of current carriers on the front surface of the battery, and the preparation process can be compatible with the existing PERC production line without laser selective doping equipment.
Description
Technical Field
The present application relates to the field of crystalline silicon solar cell technology, and more particularly to a p-type passivated emitter back cell (PERC).
Background
Crystalline silicon (c-Si) solar cells are dominant in the current global photovoltaic market due to their high conversion efficiency and mature industrial technology, and traditional crystalline silicon aluminum back field (Al-BSF) cells are gradually replaced by PERC cells. The traditional Al-BSF battery has serious carrier recombination caused by direct contact of a metal semiconductor on the back surface, and lacks the reflection of a dielectric film layer to a long wave band, and the PERC battery reduces the photoelectric loss to a greater extent by attaching a dielectric passivation layer on the back surface, so that the absolute conversion efficiency is improved by 1-2%. Through continuous optimization, the mass production efficiency of the single crystal PERC battery is improved from 20% in 2014 to over 22% in 2019. However, it must be noted that as the conversion efficiency of PERC cells increases, especially beyond 22.5%, it becomes increasingly important that the front surface passivation, which once had no major effect, begins to begin. Efficiency loss analysis was performed by the german scientific research institute on PERC cells with a conversion efficiency of 22%, and carrier recombination losses were found to occur mainly in the uniform diffusion region and the selective diffusion region of the emitter. The advantage of the PERC cell efficiency that can be further improved cannot be fully exploited if only selective emitters are used on the front surface of the cell.
The hot tunneling oxidation passivation contact (TOPCon) technology has recently found a viable solution for us. TOPCon structure made of ultra-thin silicon oxide (SiO) 2 ) Layer and doped polyThe silicon (poly-Si) layer has the advantages of full-area passivation contact, compatibility with a high-temperature sintering process of a PERC production line and the like. However, most of the research results of TOPCon are based on n-type crystalline silicon cell, which is used as the back surface field of n-type substrate, and the annual capacity of n-type crystalline silicon cell is currently less than 5GWp, which is much lower than the PERC cell capacity using p-type crystalline silicon as the substrate(s) ((s))>100 GWp). A few research teams have been attempting to fabricate TOPCon on p-type substrates, demonstrating the high efficiency potential of TOPCon structures in combination with p-type crystalline silicon cells, but as a result of the work-up, these cells were found to be either still back TOPCon structures or based on planar crystalline silicon substrates. The passivation performance of TOPCon is sensitive to the surface of the wool, and the parasitic absorption of poly-Si itself also seriously affects the wide application of TOPCon. Therefore, the preparation of high-performance TOPCon on the front side suede structure of the p-type crystalline silicon substrate has important academic and industrial values for further developing high-efficiency PERC batteries.
Disclosure of Invention
The invention aims to provide a p-type PERC crystalline silicon solar cell with low cost and high efficiency and with front full-area passivation and a preparation method thereof.
And growing ultra-thin silicon oxide and polysilicon layers with textured structures on the front side of the p-type crystalline silicon wafer by adopting a low-pressure chemical vapor deposition (LPCVD) device.
The method comprises the following steps:
and 4, depositing an intrinsic polycrystalline silicon layer, and carrying out phosphorus doping on the polycrystalline silicon by high-temperature diffusion to obtain a full-area TOPCon structure with carrier selective contact.
Further, in the step 1, the silicon wafer is placed in a potassium hydroxide solution with the volume ratio of 3%, the soaking time is 420s, the potassium hydroxide solution is used for conducting surface random pyramid texturing on the difference of different crystal face corrosion rates to form a pyramid textured face with the size of 1-2 μm in random distribution, then hydrochloric acid and hydrofluoric acid solutions are used for respectively removing metal ions and an oxide layer, and standard RCA cleaning is conducted.
Further, in the step 2, the silicon wafers are placed into a high-temperature tube furnace in a back-to-back mode in pairs for phosphorus diffusion, so that the insides of the silicon wafers which are contacted with each other can not be effectively diffused like the outsides; n for forming a surface sheet resistance of 130 omega/\ 9633 + An emitter; the front side phosphosilicate glass is then removed with a hydrofluoric acid solution.
Further, in the step 3, the silicon wafer is placed in a tubular LPCVD equipment, and is thermally oxidized for 10min at 580 ℃ to form an ultrathin and compact silicon oxide layer; the thickness of the silicon oxide layer was observed to be 1.5nm by a transmission electron microscope.
Further, in the step 4, a tube furnace with the same LPCVD equipment is used, the intrinsic polycrystalline silicon layer is deposited by utilizing silane thermal decomposition, the deposition temperature is 610 ℃, and the deposition time is 3-15 min; when the deposition time is 5min, the thickness of the corresponding polycrystalline silicon is 25nm; then, the silicon wafers are placed back to back in pairs + And (3) enabling the emitter to face outwards, carrying out phosphorus doping on the polycrystalline silicon by high-temperature diffusion, improving the crystallization degree of the polycrystalline silicon by annealing, and fully activating phosphorus ions to obtain a full-area TOPCon structure with carrier selective contact, wherein the annealing temperature is 780 ℃.
Further, after the step 4, the following steps are included:
step 5, mixing nitric acid with volume fraction of 68% and hydrofluoric acid with volume fraction of 50% according to the ratio of 3:1, preparing mixed acid liquor, corroding the back surface and the edge of the silicon chip treated in the previous step, and removing p-n junctions at the edge to insulate the upper surface and the lower surface of the silicon chip from each other; removing porous silicon on the back surface by using a potassium hydroxide solution to form a polished surface, and performing phosphorosilicate glass removal treatment on the front surface of the silicon wafer by using a hydrofluoric acid solution;
and 7, respectively printing Ag paste electrodes and Al paste electrodes on the front surface and the rear surface of the silicon wafer, and performing co-sintering through an infrared belt sintering furnace to form good ohmic contact.
A crystal silicon solar cell is an improvement of a p-type PERC crystal silicon solar cell, and a TOPCon structure is superposed on a front side suede structure.
Further, the polysilicon layer material in the TOPCon structure is phosphorus-doped polysilicon.
Further, in the TOPCon structure, the thickness of the silicon oxide layer is 1.5nm and the thickness of the polysilicon layer is 25nm.
The beneficial effect of this application is: first, compared with the current heavily doped selective emitter, the adoption of the full-area TOPCon structure can effectively reduce the recombination of carriers on the front surface of the battery, and not only reduce the recombination of carriers at the metal semiconductor interface. Second, the ultra-thin silicon oxide and the phosphorus-doped polysilicon are prepared based on the same tube furnace as the LPCVD equipment to shorten the contact time with air and avoid the formation of a native oxide layer. Thirdly, the preparation process of the battery is compatible with the existing PERC production line, meanwhile, laser selective doping equipment is not needed, and the battery cost is not additionally increased while the high efficiency is obtained.
Drawings
FIG. 1 is a schematic diagram of a p-type PERC crystal silicon solar cell according to a preferred embodiment of the present application;
FIG. 2 is a graph of hidden open circuit voltage versus phosphorus impurity drive time for a preferred embodiment of the present application;
FIG. 3 is a comparison of electrical parameters for a preferred embodiment of the present application;
the solar cell comprises a substrate, a 1-hydrogenated silicon nitride antireflection layer, a 2-front Ag electrode, a 3-phosphorus-doped polycrystalline silicon layer, a 4-ultrathin silicon oxide layer, an emitter formed by 5-high-temperature phosphorus diffusion, a 6-aluminum oxide film, a 7-hydrogenated silicon nitride passivation film, an 8-p type crystalline silicon substrate and a 9-back Al electrode.
Detailed Description
The preferred embodiments of the present application will be described below with reference to the accompanying drawings for clarity and understanding of the technical contents thereof. The present application may be embodied in many different forms of embodiments and the scope of the present application is not limited to only the embodiments set forth herein.
The p-type PERC crystalline silicon solar cell with the front-side full-area passivation structure is manufactured by the following steps:
in the first step, a p-type Cz monocrystalline silicon wafer with the industrial grade crystal orientation of (100) is adopted, the thickness of the silicon wafer is 180 mu m, and the resistivity is 1 omega cm. Firstly, preprocessing a silicon wafer, including removing a damaged layer, soaking an original silicon wafer in a potassium hydroxide solution (the volume ratio is 4%) at the temperature of 75 ℃ for 150s so as to remove the damaged layer on the surface of the silicon wafer.
And secondly, placing the silicon wafer without the damage layer in a potassium hydroxide solution (the volume ratio is 3%), soaking for 420s, performing surface random pyramid texturing by utilizing the difference of corrosion rates of different crystal faces of the potassium hydroxide solution to form a pyramid textured face with randomly distributed sizes of 1-2 mu m, removing metal ions and an oxidation layer by using hydrochloric acid and hydrofluoric acid solutions respectively, and performing standard RCA cleaning.
And thirdly, putting the silicon wafers after the texturing into a high-temperature tube furnace in a back-to-back placing mode in pairs for phosphorus diffusion, so that the insides of the silicon wafers which are contacted with each other cannot be effectively diffused like the outsides. N for forming a surface sheet resistance of 130 omega/\ 9633 + Emitter, and then front side phosphorosilicate glass is removed by hydrofluoric acid solution.
Fourthly, the diffused silicon wafer is placed in a tubular LPCVD device and is thermally oxidized for 10min at the temperature of 580 ℃ to form an ultrathin and compact silicon oxide layer. The thickness of the silicon oxide layer was observed to be 1.5nm by a transmission electron microscope.
And fifthly, depositing the intrinsic polycrystalline silicon layer by using a tube furnace with the same LPCVD equipment and utilizing silane thermal decomposition, wherein the deposition temperature is 610 ℃, the deposition time is 3min, 5min and 15min respectively, the optimal deposition time is 5min, and the corresponding thickness of the polycrystalline silicon layer is 25nm. Then, the silicon wafers are placed back to back in pairs + The emitter faces outwards, the polysilicon is doped with phosphorus by high-temperature diffusion, and annealing is carried outThe crystallization degree of the polycrystalline silicon is improved, phosphorus ions are fully activated to obtain a full-area TOPCon structure with carrier selective contact, and the annealing temperature is 780 ℃.
And a sixth step of mixing nitric acid (volume fraction is 68%) and hydrofluoric acid (volume fraction is 50%) according to a ratio of 3:1, preparing mixed acid liquor, corroding the back surface and the edge of the silicon wafer treated in the previous step, and removing p-n junctions at the edge to insulate the upper surface and the lower surface of the silicon wafer from each other; and removing the porous silicon on the back surface by using a potassium hydroxide solution to form a polished surface, and performing phosphorosilicate glass removal treatment on the front surface of the silicon wafer by using a hydrofluoric acid solution.
And seventhly, putting the annealed silicon wafer into another tube furnace, introducing ammonia gas, connecting a high-frequency power supply, and respectively depositing hydrogenated silicon nitride antireflection films and aluminum oxide/hydrogenated silicon nitride laminated passivation films on the front surface and the rear surface of the cell by using a PECVD (plasma enhanced chemical vapor deposition) process.
And eighthly, respectively printing Ag paste electrodes and Al paste electrodes on the front surface and the rear surface of the battery by using a screen printing method, and performing co-sintering by using an infrared belt sintering furnace to form good ohmic contact.
Fig. 1 is a schematic structural diagram of a prepared crystalline silicon solar cell, wherein 1 is a hydrogenated silicon nitride antireflection layer, 2 is a front Ag electrode, 3 is a phosphorus-doped polycrystalline silicon layer, 4 is an ultrathin silicon oxide layer, 5 is an emitter formed by high-temperature phosphorus diffusion, 6 is an aluminum oxide film, 7 is a hydrogenated silicon nitride passivation film, 8 is a p-type crystalline silicon substrate, and 9 is a back Al electrode.
FIG. 2 shows poly-Si/SiO 2 When the deposition time of poly-Si corresponding to the/c-Si structure is 3,5 min and 15min respectively, the hidden open circuit voltage (amplified-V) of the symmetrical structure of the battery OC ) With respect to the lead time of phosphorus impurities. Wherein 15min of poly-Si is thicker than 5min of poly-Si, and the corresponding propulsion time is longer.
FIG. 3 shows the corresponding electrical parameters (open-circuit voltage V) of the solar cell at 5 and 15min of poly-Si deposition time OC Short-circuit current density J SC Fill factor FF and conversion efficiency Eff).
As can be seen from FIG. 2, the phosphorus doping advancing time is 900s at 5min for poly-Si deposition, and the effect is best with 3min poly-Si phaseCompared with the prior art, the battery has higher tolerance to the propulsion time and wider process preparation window; cell with poly-Si deposition time of 15min, J due to absorption loss of poly-Si SC The drop is evident, see fig. 3. The solar cell with the whole area TOPCon structure on the front surface has V compared with the conventional p-type PERC cell OC Can be further improved, and then the battery conversion efficiency is improved.
The foregoing detailed description of the preferred embodiments of the present application. It should be understood that numerous modifications and variations can be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the prior art according to the concepts of the present application should be within the scope of protection determined by the claims.
Claims (2)
1. A method for preparing a p-type PERC crystalline silicon solar cell is characterized in that a silicon oxide layer with a suede structure and a phosphorus-doped polycrystalline silicon layer with the thickness of 1.5nm and a TOPCon structure is formed by growing the silicon oxide layer and the phosphorus-doped polycrystalline silicon layer on the front side of a p-type crystalline silicon wafer, the thickness of the phosphorus-doped polycrystalline silicon layer is 25nm, the silicon oxide layer and the phosphorus-doped polycrystalline silicon layer are prepared through an LPCVD method, and a hydrogenated silicon nitride antireflection layer is arranged on the TOPCon structure; the preparation method of the p-type PERC crystalline silicon solar cell comprises the following steps:
step 1, texturing the surface of the silicon wafer to form a pyramid textured surface which is randomly distributed;
step 2, high temperature phosphorus diffusion to form n + Emitter, removing front phosphorosilicate glass;
step 3, forming the silicon oxide layer by thermal oxidation;
step 4, depositing an intrinsic polycrystalline silicon layer, and carrying out phosphorus doping on the intrinsic polycrystalline silicon layer by high-temperature diffusion to obtain a full-area TOPCon structure with carrier selective contact;
step 5, preparing a mixed acid solution from 68% by volume of nitric acid and 50% by volume of hydrofluoric acid according to a volume ratio of 3; removing porous silicon on the back surface by using a potassium hydroxide solution to form a polished surface, and performing phosphorosilicate glass removal treatment on the front surface of the silicon wafer by using a hydrofluoric acid solution;
step 6, putting the silicon wafer into another tubular furnace, introducing ammonia gas, and connecting a high-frequency power supply to deposit a hydrogenated silicon nitride antireflection film, aluminum oxide and a hydrogenated silicon nitride laminated passivation film on the front surface and the rear surface of the silicon wafer respectively by using a PECVD (plasma enhanced chemical vapor deposition) process;
step 7, respectively printing Ag paste and Al paste electrodes on the front and rear surfaces of the silicon wafer, and performing co-sintering through an infrared belt sintering furnace to form good ohmic contact;
in the step 2, the silicon wafers are placed in a high-temperature tube furnace in a back-to-back mode in pairs for phosphorus diffusion, so that the insides of the silicon wafers which are contacted with each other can not be effectively diffused like the outsides; n for forming a surface sheet resistance of 130 omega/\ 9633 + An emitter; then, removing the phosphorosilicate glass on the front surface by using a hydrofluoric acid solution;
in the step 3, the silicon wafer is placed in a tubular LPCVD equipment and is thermally oxidized for 10min at 580 ℃, so that the silicon oxide layer is formed; observing the thickness of the silicon oxide layer to be 1.5nm by using a transmission electron microscope;
in the step 4, a tube furnace with the same LPCVD equipment is used, silane is utilized to carry out thermal decomposition deposition on the intrinsic polycrystalline silicon layer, the deposition temperature is 610 ℃, the deposition time is 5min, and the thickness of the corresponding intrinsic polycrystalline silicon layer is 25nm; then, the silicon wafers are placed back to back in pairs + And (3) outwards diffusing the emitter to dope phosphorus into the intrinsic polycrystalline silicon layer at high temperature, wherein the phosphorus doping advancing time is 900s, the crystallization degree of the intrinsic polycrystalline silicon layer is improved through annealing, phosphorus ions are fully activated to obtain a full-area TOPCon structure with carrier selective contact, and the annealing temperature is 780 ℃.
2. The method for preparing a p-type PERC crystalline silicon solar cell as defined in claim 1, wherein in the step 1, the silicon wafer is placed in a potassium hydroxide solution with a volume ratio of 3%, the soaking time is 420s, the potassium hydroxide solution is used for surface random pyramid texturing on the difference of different crystal face corrosion rates to form a pyramid textured surface with randomly distributed sizes of 1-2 μm, and then hydrochloric acid and hydrofluoric acid solutions are used for respectively removing metal ions and an oxide layer, and standard RCA cleaning is performed.
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