CN110880541A - Novel-structure n-type crystalline silicon PERT double-sided battery and preparation method thereof - Google Patents
Novel-structure n-type crystalline silicon PERT double-sided battery and preparation method thereof Download PDFInfo
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Abstract
The invention discloses an n-type crystalline silicon PERT double-sided battery with a novel structure and a preparation method thereof, relating to the field of silicon solar cells+An emitter layer, a hydrogenated silicon nitride antireflection layer, and an Ag/Al electrode+The emitter layer is partially formed with p++And in the selective emitter region, a silicon oxide layer, a p-doped polycrystalline silicon layer, a hydrogenated silicon nitride passivation layer and an Ag electrode are sequentially formed on the rear surface of the n-type crystalline silicon substrate. The invention adopts the laser doping on the surface of the borosilicate glass which is conventionally diffused to reduce the carrier recombination of a metal contact area, and does not need equipment such as low-pressure diffusion and the like to make high sheet resistance; the ultrathin silicon oxide layer with good performance is prepared by a simple, easily-controlled and extremely-low-cost mode of chemical oxidation of nitric acid; through proper edge insulation and high-temperature annealingAnd then, the characteristics of the front and rear side structures of the battery can be improved simultaneously, mutual interference is avoided, and the follow-up lifting space is large, so that the method has important significance.
Description
Technical Field
The invention relates to the technical field of crystalline silicon solar cells, in particular to an N-type crystalline silicon PERT double-sided cell with a novel structure and a preparation method thereof.
Background
In recent years, the industry has paid more attention to an n-type crystalline silicon PERT double-sided solar cell, which is a passivated emitter back surface total diffusion cell and has the advantages of long body life, high tolerance to metal impurities, no photoinduced attenuation effect caused by boron-oxygen complex in a P-type material, 10-30% of power generation gain compared with a traditional single-sided solar cell and the like. The n-PERT solar cell was originally proposed by doctor Zhao Jian Hua of university of Welsh Wales, Australia, the IMEC company in Belgium recently enabled the highest conversion efficiency to exceed 22% by optimization of laboratory technology, and companies such as English, Chinese, aerospace, electromechanical and Linyang in China have started mass production of this type of solar cell, and the mass production efficiency is above 21%. However, the process flow of the n-PERT double-sided battery is slightly more complicated than that of the conventional battery, and two key technologies influencing industrialization are provided: double-sided doping techniques and double-sided passivation techniques. This carrier recombination, which is mainly caused by the metal/semiconductor schottky contact, limits further enhancement of the cell efficiency, so that a more superior passivation of the metal electrode region is necessary. Heterojunction formed by hydrogenated amorphous silicon (a-Si: H) and TOPCon structures in the crystalline silicon solar cell has carrier selectivity and a good passivation effect. Compared with an a-Si: H passivation layer (deposition temperature of 250 ℃), the TOPCon structure can not only obtain lower composite current density (<10fA cm < -2 >) at low contact resistance, but also be compatible with a high-temperature metallization process. The TOPCon structure is integrated into the n-PERT double-sided solar cell, and the laser doping SE technology is combined, so that the TOPCon double-sided solar cell has innovation and great significance in the research and development of the next generation of crystalline silicon solar cells, but the TOPCon double-sided solar cell is still lack of research aiming at the type of crystalline silicon solar cell at present.
Therefore, those skilled in the art are devoted to develop a new structure N-type crystalline silicon PERT double-sided battery and a preparation method thereof, which effectively reduces the recombination of carriers at a metal/semiconductor interface, thereby improving the conversion efficiency of the battery and achieving lower cost and higher efficiency.
Disclosure of Invention
In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is to solve the problems of recombination of carriers at the metal/semiconductor interface, insufficient passivation of the metal electrode region, and high cost and low efficiency of the conventional method.
In order to achieve the purpose, the invention provides an n-type crystalline silicon PERT double-sided battery with a novel structure, which is characterized in that p is sequentially formed on the front surface of an n-type crystalline silicon substrate+An emitter layer, a hydrogenated silicon nitride antireflection layer, and an Ag/Al electrode+The emitter layer is partially formed with p++And in the selective emitter region, a silicon oxide layer, a p-doped polycrystalline silicon layer, a hydrogenated silicon nitride passivation layer and an Ag electrode are sequentially formed on the back surface of the n-type crystalline silicon substrate.
Preferably, the n-type crystalline silicon substrate is n-type Cz single crystal silicon having a crystal phase of (100), a thickness of 180 μm, and a resistivity of 0.5 Ω · cm to 3.0 Ω · cm.
Preferably, the thickness of the silicon oxide layer is 1.5 nm.
Preferably, said p is+The emitter layer had a sheet resistance of 110 Ω/□ and a junction depth of 0.7 μm.
The invention also provides a preparation method of the n-type crystalline silicon PERT double-sided battery with the novel structure, which comprises the following steps:
step 6, oxidizing the back surface of the polished silicon wafer obtained in the step 5 by using a nitric acid solution to form an ultrathin silicon oxide layer silicon wafer;
step 7, depositing a phosphorus-doped amorphous silicon layer on the back surface of the ultrathin silicon oxide layer silicon wafer obtained in the step 6 by using a PECVD (plasma enhanced chemical vapor deposition) method to obtain the phosphorus-doped amorphous silicon layer, and then performing high-temperature annealing to form polycrystalline silicon and fully activate phosphorus ions to obtain a TOPCon structure silicon wafer with carrier selective contact;
step 8, forming a hydrogenated silicon nitride passivation antireflection layer on the front surface of the TOPCon structure silicon wafer obtained in the step 7 by using a PECVD (plasma enhanced chemical vapor deposition) process, and forming a hydrogenated silicon nitride passivation layer on the back surface of the TOPCon structure silicon wafer to obtain a passivation antireflection film silicon wafer;
and 9, printing Ag/Al paste on the front surface of the passivated antireflection film silicon wafer obtained in the step 8 by using a screen printing method, printing Ag paste on the rear surface of the passivated antireflection film silicon wafer, and finally performing co-sintering by using an infrared belt sintering furnace.
Preferably, the wavelength of the nanosecond pulse laser in the step 4 is 532nm, and the pulse energy is between 80 muJ and 300 muJ.
Preferably, the temperature of the oxidation process in the step 6 is 80 ℃ and the oxidation time is 20 min.
Preferably, the concentration of the nitric acid solution in step 6 is 68%.
Preferably, the temperature of the high-temperature annealing treatment condition in the step 7 is 910 ℃, and the time is 30 min.
Preferably, the deposition temperature in step 7 is 250 ℃.
The invention has the following technical effects:
1. compared with the traditional p + emitter, the selective emitter formed by laser heavy doping can effectively reduce the recombination of current carriers at a metal/semiconductor interface;
2. compared with the preparation of silicon oxide by high-temperature oxidation, the silicon oxide grown by chemical oxidation with nitric acid solution also has excellent compactness and does not need expensive professional equipment;
3. compared with the original single n-type PERT double-sided solar cell, the characteristics of the front surface and the back surface of the solar cell with the laser selective emitter and the TOPCon structure can be simultaneously improved without mutual interference;
4. after the annealing treatment with proper time and temperature, the open-circuit voltage and the conversion efficiency of the n-PERT double-sided battery can be effectively improved.
The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.
Drawings
FIG. 1 is a schematic structural diagram of an n-PERT crystalline silicon double-sided solar cell of the present invention;
FIG. 2 is a 3D micrograph of the front surface of the cell with laser selective heavy doping for optimum conversion efficiency according to the present invention;
FIG. 3 is a graph comparing cell conversion efficiency of n-PERT bifacial cells of the present invention under different annealing conditions;
the light emitting diode comprises a 1-n type crystalline silicon substrate, a 2-p + emitter layer, a 3-hydrogenated silicon nitride antireflection layer, a 4-p + + selective emitter region, a 5-Ag/Al electrode, a 6-silicon oxide layer, a 7-p doped polycrystalline silicon layer, an 8-Ag electrode and a 9-hydrogenated silicon nitride passivation layer.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings for clarity and understanding of technical contents. The present invention may be embodied in many different forms of embodiments and the scope of the invention is not limited to the embodiments set forth herein.
In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. The size and thickness of each component shown in the drawings are arbitrarily illustrated, and the present invention is not limited to the size and thickness of each component. The thickness of the components may be exaggerated where appropriate in the figures to improve clarity.
As shown in FIG. 1, p is formed on the front surface of an n-type crystalline silicon substrate 1 in this order+An emitter layer 2, a hydrogenated silicon nitride antireflection layer 3 and an Ag/Al electrode 5, p+The emitter layer 2 is partially formed with p++And a selective emitter region 4, wherein a silicon oxide layer 6, a p-doped polycrystalline silicon layer 7, a hydrogenated silicon nitride passivation layer 9 and an Ag electrode 8 are sequentially formed on the rear surface of the n-type crystalline silicon substrate 1.
Example 1: the preparation method of the N-type crystalline silicon PERT double-sided battery with the novel structure comprises the following steps:
step 6, oxidizing the back surface of the polished silicon wafer obtained in the step 5 by using a nitric acid solution with the concentration of 68%, wherein the oxidation temperature is 80 ℃, the oxidation time is 20min, and the thickness of the silicon oxide layer is tested to be 1.5nm by using an ellipsometer to obtain an ultrathin silicon oxide layer silicon wafer;
step 7, depositing the back surface of the ultrathin silicon oxide layer silicon wafer obtained in the step 6 by using a PECVD method (deposition temperature is 250 ℃) to obtain a phosphorus-doped amorphous silicon layer, and then carrying out high-temperature annealing (annealing temperature is 910 ℃, annealing time is 30min) to crystallize the amorphous silicon to form polycrystalline silicon and fully activate phosphorus ions to obtain a TOPCon structure silicon wafer with carrier selective contact;
step 8, introducing ammonia gas into another tube furnace, connecting a high-frequency power supply, and forming a hydrogenated silicon nitride passivation antireflection layer on the front surface of the TOPCon structure silicon wafer obtained in the step 7 by using a PECVD (plasma enhanced chemical vapor deposition) process, and forming a hydrogenated silicon nitride passivation layer on the back surface of the TOPCon structure silicon wafer to obtain a passivated antireflection film silicon wafer;
and 9, printing Ag/Al paste on the front surface of the passivated antireflection film silicon wafer obtained in the step 8 by using a screen printing method, printing Ag paste on the rear surface of the passivated antireflection film silicon wafer, and finally performing co-sintering by using an infrared belt sintering furnace so as to form good ohmic contact.
As shown in fig. 2, a 3D micrograph of the cell front surface with laser selective heavy doping for optimum conversion efficiency.
As shown in fig. 3, a graph comparing cell conversion efficiency of n-PERT bifacial cells under different annealing conditions. Wherein the annealing temperature and the annealing time are respectively A-1:890 ℃/20 min; a-2, 910 ℃/20 min; a-3, 930 ℃/20 min; a-4, 890 ℃/30 min; a-5, 910 ℃/30 min; a-6 at 930 deg.C/30 min. The optimal battery conversion efficiency of 21.15 percent can be obtained when the annealing temperature is 910 ℃ and the annealing time is 30 min.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (10)
1. The novel structural n-type crystalline silicon PERT double-sided battery is characterized in that p is sequentially formed on the front surface of an n-type crystalline silicon substrate+An emitter layer, a hydrogenated silicon nitride antireflection layer, and an Ag/Al electrode+The emitter layer is partially formed with p++And in the selective emitter region, a silicon oxide layer, a p-doped polycrystalline silicon layer, a hydrogenated silicon nitride passivation layer and an Ag electrode are sequentially formed on the back surface of the n-type crystalline silicon substrate.
2. The new structure n-type crystalline silicon PERT double sided battery as claimed in claim 1, wherein the n-type crystalline silicon substrate is n-type Cz single crystalline silicon with a crystalline phase of (100), a thickness of 180 μm, and a resistivity of 0.5 Ω -cm-3.0 Ω -cm.
3. The new structure n-type crystalline silicon PERT double sided cell as claimed in claim 1 wherein the thickness of the silicon oxide layer is 1.5 nm.
4. The new structure n-type crystalline silicon PERT double sided cell as claimed in claim 1 wherein p is selected from the group consisting of+The emitter layer had a sheet resistance of 110 Ω/□ and a junction depth of 0.7 μm.
5. A preparation method of an n-type crystalline silicon PERT double-sided battery with a novel structure is characterized by comprising the following steps:
step 1, preparing an n-type Cz monocrystalline silicon wafer with an industrial grade crystal orientation of (100) as an n-type crystalline silicon substrate, and removing a damaged layer formed on the surface of the n-type crystalline silicon substrate by linear cutting with a sodium hydroxide solution;
step 2, texturing the n-type crystalline silicon substrate obtained in the step 1 by using an alkali solution, and then carrying out standard RCA cleaning to obtain a pretreated silicon wafer;
step 3, putting the silicon wafers obtained in the step 2 into a traditional high-temperature diffusion furnace in pairs in a back-to-back manner for BBr3Diffusing to form p on the front surface+An emission level layer;
step 4, using nanosecond pulse laser to perform laser treatment on the p in the step 3+The emitter layer is locally heavily doped to form p++A selective emitter region;
step 5, etching the front surface and the periphery of the silicon wafer obtained in the step 4 by using a mixed solution of nitric acid and hydrogen fluoride, then cleaning by using deionized water, and polishing the back surface of the silicon wafer by using a potassium hydroxide solution at room temperature to obtain a polished silicon wafer;
step 6, oxidizing the back surface of the polished silicon wafer obtained in the step 5 by using a nitric acid solution to form an ultrathin silicon oxide layer silicon wafer;
step 7, depositing a phosphorus-doped amorphous silicon layer on the back surface of the ultrathin silicon oxide layer silicon wafer obtained in the step 6 by using a PECVD (plasma enhanced chemical vapor deposition) method to obtain the phosphorus-doped amorphous silicon layer, and then performing high-temperature annealing to form polycrystalline silicon and fully activate phosphorus ions to obtain a TOPCon structure silicon wafer with carrier selective contact;
step 8, forming a hydrogenated silicon nitride passivation antireflection layer on the front surface of the TOPCon structure silicon wafer obtained in the step 7 by using a PECVD (plasma enhanced chemical vapor deposition) process, and forming a hydrogenated silicon nitride passivation layer on the back surface of the TOPCon structure silicon wafer to obtain a passivation antireflection film silicon wafer;
and 9, printing Ag/Al paste on the front surface of the passivated antireflection film silicon wafer obtained in the step 8 by using a screen printing method, printing Ag paste on the rear surface of the passivated antireflection film silicon wafer, and finally performing co-sintering by using an infrared belt sintering furnace.
6. The method for preparing the n-type crystalline silicon PERT double-sided battery with the novel structure as claimed in claim 5, wherein the nanosecond pulse laser in the step 4 has the wavelength of 532nm and the pulse energy of 80-300 muJ.
7. The method for preparing the n-type crystalline silicon PERT double-sided battery with the novel structure as claimed in claim 5, wherein the temperature of the oxidation process in the step 6 is 80 ℃ and the oxidation time is 20 min.
8. The method for preparing the n-type crystalline silicon PERT double-sided battery with the novel structure as claimed in claim 5, wherein the concentration of the nitric acid solution in the step 6 is 68%.
9. The method for preparing the n-type crystalline silicon PERT double-sided battery with the new structure as claimed in claim 5, wherein the temperature of the high temperature annealing treatment condition in step 7 is 910 ℃ and the time is 30 min.
10. The method for preparing a novel structural n-type crystalline silicon PERT double-sided battery as claimed in claim 5, wherein the deposition temperature in the step 7 is 250 ℃.
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Cited By (12)
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| CN108648996A (en) * | 2018-05-03 | 2018-10-12 | 武汉新芯集成电路制造有限公司 | A method of reducing floating boom square resistance |
| CN111416012A (en) * | 2020-05-02 | 2020-07-14 | 熵熠(上海)能源科技有限公司 | Silicon heterojunction solar cell comprising silicon nitride antireflection layer and preparation method |
| CN111416014A (en) * | 2020-05-08 | 2020-07-14 | 熵熠(上海)能源科技有限公司 | Passivated contact back junction silicon heterojunction solar cell and preparation method thereof |
| CN111416011A (en) * | 2020-04-08 | 2020-07-14 | 上海交通大学 | P-type PERC crystalline silicon solar cell and preparation method thereof |
| CN111628049A (en) * | 2020-06-11 | 2020-09-04 | 常州时创能源股份有限公司 | Method for realizing local hole passivation contact, crystalline silicon solar cell and preparation method thereof |
| CN111816726A (en) * | 2020-06-15 | 2020-10-23 | 隆基绿能科技股份有限公司 | Back contact solar cell, production method thereof and back contact cell assembly |
| CN113937186A (en) * | 2021-09-26 | 2022-01-14 | 东莞南玻光伏科技有限公司 | Back doping process and application of P-type silicon wafer |
| EP3982421A1 (en) * | 2020-10-09 | 2022-04-13 | International Solar Energy Research Center Konstanz E.V. | Method for local modification of etching resistance in a silicon layer, use of this method in the production of passivating contact solar cells and thus-created solar cell |
| CN115036384A (en) * | 2022-04-25 | 2022-09-09 | 青海黄河上游水电开发有限责任公司西宁太阳能电力分公司 | N-type TOPCon solar cell and manufacturing method thereof |
| CN115732597A (en) * | 2022-12-01 | 2023-03-03 | 江苏杰太光电技术有限公司 | Preparation method of TOPCon battery selective emitter and passivation contact structure |
| WO2023072013A1 (en) * | 2021-10-25 | 2023-05-04 | 天合光能股份有限公司 | Emitter, selective emitter cell preparation method and selective emitter cell |
| WO2024032224A1 (en) * | 2022-08-10 | 2024-02-15 | 常州捷佳创精密机械有限公司 | Preparation method for laser boron-doped battery emitter, and battery and preparation system |
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| CN108648996A (en) * | 2018-05-03 | 2018-10-12 | 武汉新芯集成电路制造有限公司 | A method of reducing floating boom square resistance |
| CN111416011B (en) * | 2020-04-08 | 2023-02-21 | 上海交通大学 | P-type PERC crystalline silicon solar cell and preparation method thereof |
| CN111416011A (en) * | 2020-04-08 | 2020-07-14 | 上海交通大学 | P-type PERC crystalline silicon solar cell and preparation method thereof |
| CN111416012A (en) * | 2020-05-02 | 2020-07-14 | 熵熠(上海)能源科技有限公司 | Silicon heterojunction solar cell comprising silicon nitride antireflection layer and preparation method |
| CN111416014A (en) * | 2020-05-08 | 2020-07-14 | 熵熠(上海)能源科技有限公司 | Passivated contact back junction silicon heterojunction solar cell and preparation method thereof |
| CN111416014B (en) * | 2020-05-08 | 2022-03-04 | 熵熠(上海)能源科技有限公司 | Passivated contact back junction silicon heterojunction solar cell and preparation method thereof |
| CN111628049A (en) * | 2020-06-11 | 2020-09-04 | 常州时创能源股份有限公司 | Method for realizing local hole passivation contact, crystalline silicon solar cell and preparation method thereof |
| CN111816726A (en) * | 2020-06-15 | 2020-10-23 | 隆基绿能科技股份有限公司 | Back contact solar cell, production method thereof and back contact cell assembly |
| CN111816726B (en) * | 2020-06-15 | 2023-10-03 | 隆基绿能科技股份有限公司 | Back contact solar cell, production method thereof and back contact cell assembly |
| EP3982421A1 (en) * | 2020-10-09 | 2022-04-13 | International Solar Energy Research Center Konstanz E.V. | Method for local modification of etching resistance in a silicon layer, use of this method in the production of passivating contact solar cells and thus-created solar cell |
| WO2022074091A1 (en) * | 2020-10-09 | 2022-04-14 | International Solar Energy Research Center Konstanz E.V. | Method for local modification of etching resistance in a silicon layer, use of this method in the production of passivating contact solar cells and thus-created solar cell |
| CN113937186A (en) * | 2021-09-26 | 2022-01-14 | 东莞南玻光伏科技有限公司 | Back doping process and application of P-type silicon wafer |
| WO2023072013A1 (en) * | 2021-10-25 | 2023-05-04 | 天合光能股份有限公司 | Emitter, selective emitter cell preparation method and selective emitter cell |
| CN115036384A (en) * | 2022-04-25 | 2022-09-09 | 青海黄河上游水电开发有限责任公司西宁太阳能电力分公司 | N-type TOPCon solar cell and manufacturing method thereof |
| WO2024032224A1 (en) * | 2022-08-10 | 2024-02-15 | 常州捷佳创精密机械有限公司 | Preparation method for laser boron-doped battery emitter, and battery and preparation system |
| CN115732597A (en) * | 2022-12-01 | 2023-03-03 | 江苏杰太光电技术有限公司 | Preparation method of TOPCon battery selective emitter and passivation contact structure |
| CN115732597B (en) * | 2022-12-01 | 2024-03-22 | 江苏杰太光电技术有限公司 | Preparation method of TOPCON battery selective emitter and passivation contact structure |
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