CN113937186A - Back doping process and application of P-type silicon wafer - Google Patents

Back doping process and application of P-type silicon wafer Download PDF

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CN113937186A
CN113937186A CN202111131526.XA CN202111131526A CN113937186A CN 113937186 A CN113937186 A CN 113937186A CN 202111131526 A CN202111131526 A CN 202111131526A CN 113937186 A CN113937186 A CN 113937186A
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silicon wafer
type silicon
diffusion
boron
doping process
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王丹丹
陈家健
祁嘉铭
杨江海
杨健
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Dongguan Csg Photovoltaic Technology Co ltd
CSG Holding Co Ltd
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Dongguan Csg Photovoltaic Technology Co ltd
CSG Holding Co Ltd
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    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
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Abstract

The invention provides a back doping process and application of a P-type silicon wafer, and relates to the technical field of preparation of photovoltaic power generation products. The process comprises the following steps: the front surfaces of the P-type silicon wafers face to face and are close together, and boron diffusion is carried out on the back surfaces of the P-type silicon wafers under the condition that the pressure is 50mTorr-300 mTorr; and carrying out first laser doping on the back surface after the boron diffusion, and then carrying out first cleaning. The low-pressure boron diffusion is carried out on the back of the silicon wafer, the diffusion sheet resistance can be reduced, the local boron heavily-doped P + + region is further formed by laser doping, the conversion efficiency of the cell can be improved by 0.05%, and the technical bottleneck that the conversion efficiency is difficult to further improve by the existing silicon wafer doping technology is broken through. According to the scheme, the doped silicon wafer can form metal contact with an aluminum back surface field on the back surface, so that the series resistance is reduced, and the doped silicon wafer can be used for preparing a PERC battery.

Description

Back doping process and application of P-type silicon wafer
Technical Field
The embodiment of the invention relates to the technical field of photovoltaic power generation product preparation, and particularly relates to a back doping process and application of a P-type silicon wafer.
Background
The conventional single crystal PERC Cell (Passivated Emitter and Rear Cell, PERC Cell for short) is doped with phosphorus on the front side of a silicon wafer to form a PN junction, and the Rear side of the silicon wafer is sintered after an aluminum grid line is printed to realize doping. Because the sintering adopts a rapid sintering process, the doping concentration is low, which is not beneficial to the reduction of series resistance and causes the conversion efficiency of the cell to be low.
The current efficiency improving means is difficult to break through the technical bottleneck, and the improvement of the battery conversion efficiency is difficult to realize.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a back doping process and application of a P-type silicon wafer (hereinafter also referred to as a silicon wafer), wherein impurity distribution with light doping on the surface and heavy doping on the local part is formed on the back of the P-type silicon wafer, so that the conversion efficiency is improved.
In a first aspect, an embodiment of the present invention provides a back doping process for a P-type silicon wafer, including:
the front surfaces of the P-type silicon wafers face to face and are close together, and boron diffusion is carried out on the back surfaces of the P-type silicon wafers under the condition that the pressure is 50mTorr-300 mTorr;
and carrying out first laser doping on the back surface after the boron diffusion, and then carrying out first cleaning.
The boron is diffused under the low pressure condition of 50mTorr-300mTorr, the good boron doping can be realized through the one-time source passing process, and the sheet resistance of the doped silicon wafer is reduced. And further, the silicon substrate is instantaneously melted by means of laser energy, boron atoms are pushed to the surface of the silicon wafer to form local heavy doping, namely a boron heavy doping P + + region, and the purpose of improving the conversion efficiency of the PERC cell is achieved.
The first cleaning is used for removing Boron Silicon Glass (BSG) and a peripheral diffusion layer formed by a Boron diffusion process. The first cleaning may use an acid solution such as a mixed solution of hydrofluoric acid, hydrochloric acid, or the like, or an alkali solution such as a sodium hydroxide solution or a potassium hydroxide solution as the etchant.
According to some embodiments of the invention, the etchant for the first cleaning is a mixture of 45-55% by mass of HF, 40-55% by mass of HCl and water in a volume ratio of 1 (1-2) to (2-4).
According to some embodiments of the present invention, the laser power of the first laser doping is 25W-30W, the spot size can be controlled within 80 μm-100 μm, and the depth can be controlled within 0.1 μm-0.3 μm, so as to prevent the silicon wafer from being broken by the stress.
According to some embodiments of the invention, before bringing the front surfaces of the P-type silicon wafers face towards each other, preparing a mask on the front surface of the P-type silicon wafer is further included.
The mask is used for protecting the front side of the P-type silicon wafer, so that boron atoms are prevented from entering the front side of the silicon wafer to be doped due to diffraction in a subsequent boron diffusion process, and the mask can play a role in protecting the silicon wafer and prevent the silicon wafer from being scratched on the surface when the silicon wafer is leaned together.
Before boron diffusion is carried out, if phosphorus doping is carried out on the front surface of the silicon wafer, the mask can protect PN junctions on the surface of the silicon wafer from being damaged in subsequent links such as boron diffusion, and meanwhile, boron atoms are prevented from diffusing into the silicon wafer on the front surface in the boron diffusion process to form PN junctions with phosphorus, so that short circuit is caused.
The mask can be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The mask may be made of SixOy、SixNyEtc., the thickness may be 10-20 nm.
According to some embodiments of the invention, before the preparing the mask on the front side of the P-type silicon wafer, the texturing, front side phosphorus diffusion and second cleaning are sequentially performed on the P-type silicon wafer.
The texturing is mainly used for forming a textured surface on the surface of the silicon wafer and improving the effect of filling light. The etching may use an acid solution or an alkali solution as an etchant. Further, a texturing additive, such as sodium silicate and isopropyl alcohol, may be added to the above-mentioned etchant, thereby controlling the reaction rate and obtaining a better texturing state.
The front side phosphorus diffusion is used for forming an N-type diffusion layer on the front side of the silicon wafer, and phosphorus oxychloride (POCl) can be adopted3) Is a phosphorus source.
The above-described texturing, front side phosphorus diffusion, is well known in the art and will not be described in detail.
And a second cleaning step for removing a phosphosilicate Glass (PSG) and a peripheral diffusion layer formed by the phosphorus diffusion process.
According to some embodiments of the invention, the etchant of the second cleaning employs HF at a mass concentration of 45-55%, HNO at a mass concentration of 45-60%3And water is mixed according to the volume ratio of (1-2) to (2-3) to (10-12).
According to some embodiments of the present invention, before the second cleaning, the method further includes performing second laser doping on the diffusion layer obtained by the front-side phosphorus diffusion, where the second laser doping is used to push phosphorus atoms to the surface of the silicon wafer to form local heavy doping, that is, to form a phosphorus heavy doping N + + region.
The laser power of the second laser doping can be 20W-30W, the spot size can be controlled to be 100 μm-130 μm, and the depth can be controlled to be 0.1 μm-0.4 μm.
According to some embodiments of the invention, the boron-diffused boron source is a commonly used liquid boron source, exemplified by boron tribromide, trimethyl borate, triethyl borate, and the like. Further, the boron source of the boron diffusion is boron tribromide.
According to some embodiments of the invention, in the boron diffusion, the boron source is sourced through a shower. Compared with the existing source passing mode through a furnace opening, the liquid boron source is output in a spraying and diffusing mode, so that the gasified boron source molecules are uniformly distributed in a spraying pipe and a diffusion furnace, the boron diffusion uniformity is improved, and the sheet resistance is further reduced. Therefore, the number of the spray holes of the spray pipe can be increased, and the spray holes are distributed on the spray pipe at intervals as uniformly as possible.
According to some embodiments of the invention, the flux temperature of the boron diffusion is 900 ℃ to 980 ℃.
The source connection time can be 300s-900s, and the quality of the PN junction can be improved by regulating the source connection time.
The flux source small nitrogen flow rate can be 800sccm-1100 sccm.
The flux source large nitrogen flow rate can be 800sccm-1500 sccm.
The flux oxygen flow rate can be 100sccm to 400 sccm.
According to some embodiments of the invention, the boron diffusion further comprises a high temperature drive treatment after the source introduction, wherein the high temperature drive treatment is performed under the condition of introducing nitrogen, the temperature is 980-1000 ℃, and the time is 300-520 s.
Introducing nitrogen to improve the furnace tube gas atmosphere in the high-temperature propulsion process, wherein the nitrogen introducing flow in the nitrogen introducing process is as follows: the flow rate of the large nitrogen is 900-1300 sccm, and the flow rate of the small nitrogen is 300-700 sccm.
According to some embodiments of the invention, the P-type silicon wafer is a P-type monocrystalline silicon wafer or a P-type polycrystalline silicon wafer.
In a second aspect, the embodiment of the present invention provides an application of the above-mentioned back doping process for a P-type silicon wafer in the preparation of a PERC cell. And under the condition that the P-type silicon wafer is a P-type monocrystalline silicon wafer, the PERC cell is a monocrystalline PERC cell.
The PERC cell may be a single-sided PERC cell or a double-sided PERC cell.
According to the scheme provided by the embodiment of the invention, the PN junction is formed by carrying out low-pressure boron diffusion on the back surface of the P-type silicon wafer within a specific pressure range, so that the diffusion sheet resistance can be reduced. Further matching with the source-through mode of the spray pipe, the diffusion sheet resistance can be between 50 and 70 omega, and in the conventional phosphorus source diffusion process, the diffusion sheet resistance is generally between 120 and 130 omega.
And further, the laser energy is utilized to push the boron atoms of the boron diffusion layer to the surface of the silicon wafer to form a local heavily doped P + + region to plump PN junctions inside the cell, so that the conversion efficiency of the cell can be improved by 0.05%, and the technical bottleneck that the conversion efficiency is difficult to further improve by the existing silicon wafer doping technology is broken through.
Compared with the existing back doping mode of only performing rapid sintering, the silicon wafer obtained by the doping mode can form metal contact with an aluminum back field on the back surface, and can effectively reduce series resistance.
Definition of
As used herein, the term "boron diffusion" refers to the doping of the face of a silicon wafer to be doped with a liquid boron source at a pressure and temperature to form a gas.
As used herein, the term "phosphorus diffusion" refers not only to doping the surface of a silicon wafer to be doped with a liquid phosphorus source under a certain pressure and a certain temperature to form a gas, but also to other well-known diffusion doping methods, such as coating a phosphorus-containing doping layer (e.g., phosphoric acid) and then performing a heat treatment to achieve phosphorus diffusion.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a schematic structural view of a shower corresponding to an orifice region according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of fig. 1.
In the figure, a shower pipe 100, a spray hole 110 and an inner cavity 120 are shown.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It is noted that the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Examples
In the back doping process of a P-type silicon wafer according to an embodiment of the present invention, the P-type silicon wafer is a P-type monocrystalline silicon wafer. Before the back doping process is carried out, texturing, front phosphorus diffusion, second laser doping and second cleaning treatment are sequentially carried out on the silicon wafer, and the method specifically comprises the following steps:
s110, cleaning the original silicon wafer by using a NaOH solution with the mass concentration of 40-50% to remove a surface damage layer, and performing texturing treatment on the surface of the silicon wafer by using a mixed solution of NaOH and a texturing additive.
And S120, relatively leaning the back surfaces of the silicon wafers together to perform single-side phosphorus diffusion, wherein the front surface of the silicon wafer is a diffusion surface.
And S130, performing laser doping on the front surface of the silicon wafer after phosphorus diffusion to form a partial phosphorus heavily doped N + + region. The laser power of laser doping is 20W-30W, the spot size is controlled to be 100 μm-130 μm, and the depth is controlled to be 0.1 μm-0.4 μm.
S140, cleaning, wherein the cleaning solution is HF with the mass concentration of 45-55% and HNO with the mass concentration of 45-60%3And mixing water according to the volume ratio of (1-2) to (2-3) to (10-12), and removing peripheral junctions and PSG formed by phosphorus diffusion to obtain the processed silicon wafer.
Performing back doping on the silicon wafer processed in the steps S1 to S4, specifically as follows:
s210, plating a layer of SixNy film with the thickness of 10-20nm on the front surface of the cleaned silicon wafer by utilizing PECVD equipment.
And S220, putting the front surfaces of the coated silicon wafers into a diffusion furnace with the front surfaces facing to each other, and performing boron diffusion by using boron tribromide as a boron source, wherein the back surfaces of the silicon wafers are diffusion surfaces.
The source passing mode of boron diffusion is that the spray pipe passes through the source, the spray pipe is suspended at the top in the diffusion furnace pipe, the length of the spray pipe is matched with the length of the diffusion furnace pipe, the outer diameter of the spray pipe is about 14mm, and the inner diameter of the spray pipe is about 8 mm.
As shown in fig. 1, which is a physical diagram of the shower pipe 100, two rows of spray holes 110 are densely distributed along the length direction of the shower pipe 100, the aperture of each spray hole 110 is 0.3mm-0.4mm, and the hole pitch of each row of spray holes 110 is 4mm-5 mm. The inner cavity 120 of the shower pipe 100 is used for boron source gas to pass through and uniformly enter the diffusion furnace through the spray holes 110.
In this example, the process parameters of each stage of boron diffusion are shown in table 1 below.
The diffusion sheet resistance is detected by a four-probe sheet resistance tester, and the result shows that the low-pressure diffusion process of the embodiment can realize the diffusion sheet resistance of 50-70 omega. And (4) obtaining the silicon wafer with low diffusion sheet resistance by utilizing the advantages of low-pressure diffusion and source communication of the spray pipe, and preparing for subsequent heavy doping.
TABLE 1
Figure BDA0003280633430000041
And S230, doping the back of the silicon wafer after boron diffusion by using laser, and pushing boron atoms adsorbed on the silicon wafer to the surface of the silicon wafer by using the high energy of the laser for instantly melting silicon to form a boron heavily-doped P + + region.
It should be noted that the laser pattern needs to avoid the back electrode region to prevent the silicon wafer from being damaged by laser grooving in the subsequent electrode preparation process. In the embodiment, the laser power is between 25W and 30W, the spot size is controlled between 80 mu m and 100 mu m, the depth is controlled within 0.1 mu m to 0.3 mu m, and the silicon wafer is prevented from being damaged under the stress action.
And S240, carrying out acid cleaning on the back of the silicon wafer subjected to boron diffusion by using a chain type cleaning machine to obtain the silicon wafer subjected to back doping.
The pickling solution is a mixed solution obtained by mixing HF (mass concentration of 45-55%), HCl (mass concentration of 40-55%) and water according to a volume ratio of 1:1: 2-1: 2:4, and the pickling solution can remove BSG (barium strontium silicate), peripheral junctions and a mask on the front side of the silicon wafer, does not damage PN junctions on the front side of the silicon wafer, and does not affect the light trapping effect on the front side of the silicon wafer.
Comparative example
The resulting P-type single crystal silicon wafer was processed using steps S110 to S140 of the example.
Test example
The silicon wafers prepared in the examples and the comparative examples are respectively subjected to the subsequent working procedures of thermal oxidation, back coating, front coating, laser grooving, screen printing and the like in turn according to the known PERC cell manufacturing flow to prepare the single crystal PERC cell.
Short-circuit current (Isc), open-circuit voltage (Uoc), Fill Factor (FF), series resistance (Rs), parallel resistance (Rsh), and conversion efficiency (Eta) were tested, and the test results are shown in table 2.
TABLE 2
Figure BDA0003280633430000051
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.

Claims (10)

1. A back doping process of a P-type silicon wafer is characterized by comprising the following steps:
the front surfaces of the P-type silicon wafers face to face and are close together, and boron diffusion is carried out on the back surfaces of the P-type silicon wafers under the condition that the pressure is 50mTorr-300 mTorr;
and carrying out first laser doping on the back surface after the boron diffusion, and then carrying out first cleaning.
2. The back doping process of the P-type silicon wafer according to claim 1, wherein before the front sides of the P-type silicon wafers are close together in a face-to-face mode, the back doping process further comprises the steps of preparing a mask on the front sides of the P-type silicon wafers; further, the method for preparing the mask is plasma enhanced chemical vapor deposition.
3. The back doping process of the P-type silicon wafer according to claim 2, wherein before the preparation of the mask on the front surface of the P-type silicon wafer, the process further comprises the steps of texturing, front surface phosphorus diffusion and secondary cleaning of the P-type silicon wafer in sequence.
4. The back doping process of the P-type silicon wafer according to claim 3, wherein before the second cleaning, the second laser doping is performed on the diffusion layer made by the front phosphorus diffusion.
5. The back side doping process of a P-type silicon wafer according to claim 1, wherein the boron source of the boron diffusion is boron tribromide.
6. The back side doping process of the P-type silicon wafer according to claim 5, wherein the open source temperature of the boron diffusion is 900 ℃ to 980 ℃; further, the source passing time of the boron diffusion is 300-900 s; further, the boron diffusion also comprises high-temperature propelling treatment after source introduction, wherein the high-temperature propelling treatment is carried out under the condition of introducing nitrogen, the temperature is 980-1000 ℃, and the time is 300-520 s.
7. The back side doping process of P-type silicon wafer according to claim 6, wherein the flux source small nitrogen flow rate of the boron diffusion is 800sccm to 1100 sccm.
8. The back doping process of the P-type silicon wafer according to claim 1, 5, 6 or 7, wherein in the boron diffusion, a boron source is communicated through a shower pipe.
9. The back side doping process of a P-type silicon wafer according to claim 1, wherein the P-type silicon wafer is a P-type monocrystalline silicon wafer or a P-type polycrystalline silicon wafer.
10. Use of the back side doping process of a P-type silicon wafer according to any one of claims 1 to 9 for the preparation of a PERC cell.
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