WO2014137284A1

WO2014137284A1 - Method of fabricating a solar cell

Info

Publication number: WO2014137284A1
Application number: PCT/SG2013/000089
Authority: WO
Inventors: Fei Zheng; Johnson WONG; Matthew BORELAND; Bram Hoex; Anahita KARPOUR; Armin Gerhard Aberle; Shubham DUTTAGUPTA; Thomas Mueller
Original assignee: Trina Solar Energy Development Pte Ltd
Priority date: 2013-03-05
Filing date: 2013-03-05
Publication date: 2014-09-12

Abstract

According to one aspect, there is provided a method of fabricating a solar cell comprising: forming a patterned passivation layer that is in contact with a surface of a wafer, the surface being doped with dopant of a first polarity; and masklessly performing, over the patterned passivation layer, a fabrication step selected from the steps of: etching further, trenches in the surface of the wafer that result after forming the patterned passivation layer; and doping the trenches with dopant of second polarity that is opposite to the dopant of the first polarity.

Description

Method of fabricating a solar cell

FIELD OF INVENTION The invention relates to a method of fabricating a solar cell.

BACKGROUND

All-back-contact (ABC) silicon wafer solar cells, in particular back-junction ABC cells, have the potential of achieving very high energy conversion efficiency. ABC cells have several advantages over conventional silicon wafer solar cells, which have contacts on both surfaces, whereby the front contact is a metal grid consisting of parallel fingers and several busbars connecting the metal fingers. The advantages of ABC cells include increased photogeneration of carriers due to the elimination of the optical front-metal grid shading and improved blue response since a heavy front- surface doping to reduce the front contact resistance is not required due to the shifting of the front contacts to the rear of the cell. In addition, ABC cells have a favourable appearance in modules due to the homogeneous dark colour (almost black) provided by the surface texture in combination with an effective anti-reflective coating.

Silicon substrates with high bulk minority carrier iifetime and an excellent front and rear surface passivation are required for back-junction ABC solar cells, because photo-generated carriers must travel to the rear surface where the charge-separating p-n junction is located. As a result, industrial n-type silicon wafers are used for back- junction ABC solar cells due to their typical higher bulk minority carrier Iifetime compared to industrial p-type silicon wafers.

ABC silicon wafer solar cell architectures have the potential for very high conversion efficiencies due to their high minority carrier lifetime wafers, eliminated optical shading at the front, improved blue response and lower bulk and surface recombination currents enabled by excellent surface passivation and more freedom in the emitter, BSF and FSF diffusion profile. However, current fabrication methods and cost considerations have prevented the ABC cell from being cost-effective for application in conventional low-cost industrial solar cell manufacturing lines. The main issues during the manufacturing are related to the patterning of the rear side in order to establish the interdigitated p-doped and n-doped regions including the use of photoresist or printed resist, processing, mask alignments, and the use of metal deposition providing a low contact resistance, such as thermal or electron-beam evaporation or sputtering.

A need therefore exists to provide cost-effective processing and manufacturing methods to reduce the number of process steps and hence reduce production costs of industrial all-back-contact solar cells.

SUMMARY

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention, in which:

Figure 1 shows a flowchart that illustrates a method to fabricate a solar cell according to one embodiment.

Figures 2A to 2D illustrate a first process to fabricate a solar cell in accordance with a method that follows the flowchart of Figure .

Figures 3A to 3H illustrate a second process to fabricate a solar cell in accordance with a method that follows the flowchart of Figure 1.

Figures 4A to 4E illustrate a third process to fabricate a solar cell in accordance with a method that follows the flowchart of Figure 1.

Figure 5 shows the structure of a solar cell built in accordance with a method that follows the flowchart of Figure 1. DEFINITIONS The following provides sample, but not exhaustive, definitions for expressions used throughout various embodiments disclosed herein.

^{^} The term "patterned passivation layer" may refer to an initial passivation layer that has portions removed so that there are openings that allows access to a surface with which the initial passivation layer is in contact or covers. The patterned passivation layer may then act as a template to form subsequent layers of the fabricated. solar cell, whereby the subsequent layers may partially or entirely follow the pattern of the patterned passivation layer.

The term "passivation layer" may mean a layer made from materials such as silicon nitride, silicon dioxide or titanium dioxide that can reduce surface recombination, which leads to losses in solar cells.

The term "masklessly" may mean that a mask is not used for fabrication steps that are performed over the patterned passivation layer.

The term "etching further" is in respect of trenches that are a by-product when patterning an initial passivation layer to form the patterned passivation layer, such trenches being formed in a wafer with which the patterned passivation layer is in contact. Thus, the term "etching further" may mean that such trenches are further deepened into the wafer.

The term "performing over" may mean that subsequent steps to fabricate the solar cell are carried out with the patterned passivation layer being present. Accordingly, the patterned passivation layer is not removed, but remains on the wafer surface, with further structures formed over the patterned passivation layer after fabrication of the solar cell is completed.

The term "trenches" may mean openings in the wafer having a depth that is confined within the thickness of the wafer.

DETAILED DESCRIPTION

In the following description, various embodiments are described with reference to the drawings, where like reference characters generally refer to the same parts throughout the different views.

In various embodiments, the number of process steps to manufacture all- back-contact (ABC) solar cells is significantly reduced, thereby reducing the manufacturing costs of these cells. This is done by exploiting the fact that certain dielectric stacks can have various functional properties, such as using dielectric stacks as masking layer for wet-chemical processes and diffusion barriers, whilst maintaining the same dielectrics as surface passivating layers of p-type and n-type doped silicon regions. Each of the various embodiments provide a method to manufacture ABC silicon wafer solar cells that is easier and cheaper than manufacturing sequences utilising micro-electronic circuit processing techniques, while maintaining the high-efficiency potential of back-junction ABC structures. The selective passivation dielectric stacks are self-aligned in nature and deposited without any mask, therefore provide a cheaper and better way to fabricate all-back- contact silicon wafer solar cells. These self-aligned passivation dielectric stacks will also serve as a diffusion barrier for one polarity and etch-back mask for a front- surface-field (FSF).

Figure 1 shows a flowchart 100 that illustrates a method to fabricate a solar cell (not shown) according to one embodiment.

In step 102, a patterned passivation layer that is in contact with a surface of a wafer is formed, the surface being doped with dopant of a first polarity. Reference numeral 104 is used to denote the maskless performance, over the patterned passivation layer (from step 102), of a fabrication step selected from the steps denoted using reference numerals 106 and 108. In step 106, trenches in the surface of the wafer (from step 102) that result after forming the patterned passivation layer are further etched. In step 108, the trenches are doped with dopant of second polarity that is opposite to the dopant of the first polarity.

Figures 2A to 2D illustrate a first process to fabricate a portion of a solar cell in accordance with a method that follows the flowchart 100 of Figure 1.

In Figure 2A, a semiconductor wafer 200 is provided (of which only a portion is shown), having a surface 202 (interchangeably referred to as the rear surface) and an opposite surface (not shown, but interchangeably referred to as the front surface). The surface 202 of the wafer 200 is doped with dopant of a first polarity to form a first doped region 201.

In Figure 2B, a passivation layer 206 is formed to be in contact with the surface 202 of the wafer 200 is formed. However, it will also be appreciated that one or more layers (not shown) may be formed over the surface 202 before the passivation layer 206 is formed.

In Figure 2C, the passivation layer 206 is patterned to form a patterned passivation layer 208. The patterned passivation layer 208 may be formed by laser ablation of the passivation layer 206. Patterning of the passivation layer 206 results in trenches 2 0 being formed in the surface 202 of the wafer 200. Further fabrication is then masklessly performed over the patterned passivation layer 208, i.e. a mask is not used, to perform the subsequent steps to fabricate a solar cell. Various embodiments allow for the subsequent steps to be masklessly performed as well as ensuring that the subsequent layers are masklessly self aligned by the pattern established by the patterned passivation layer 208.

The omission of a mask eliminates alignment issues associated with using a mask in semiconductor fabrication. Subsequent layers that are formed are self- aligned, i.e. they are aligned by the pattern established by the patterned passivation layer 208. Even the patterned passivation layer 208 may be formed without the use of a mask, for example when laser ablation is used to form the patterned passivation layer 208.

Further fabrication being performed over the patterned passivation layer 208 means that the patterned passivation layer 208 remains in the fabricated solar cell, i.e. the patterned passivation layer 208 is not removed. This has the advantage of saving a processing step in fabricating the solar cell. Leaving the patterned passivation layer 208 is also advantageous because a passivation layer reduces surface recombination, which leads to losses in solar cells.

The trenches 210 that result after forming the patterned passivation layer 208 are further etched (to form deeper trenches, shown as reference numeral 212 in Figure 2D). These trenches 212 are doped with dopant of second polarity that is opposite to the dopant of the first polarity to form a second doped region 213. The rear of the resulting structure 220, shown in Figure 2D, thus has a first portion that is doped to a first polarity (i.e. the rear surface that is covered by the patterned passivation layer 208) and a second portion that is doped to a second polarity (i.e. the walls of the trenches 212). During doping of the trenches 212, the patterned passivation layer 208 acts as a diffusion barrier to the dopant of second polarity for the portions of the surface 202 that the patterned passivation layer 208 covers.

In one embodiment, the dopant of the first polarity to form the first doped region 201 is p-type and the dopant of the second polarity to form the second doped region 2 3 is n-type. In another embodiment, the dopant of the first polarity to form the first doped region 201 is n-type and the dopant of the second polarity to form the second doped region 213 is p-type.

Only one subsequent fabrication step is illustrated in the process of Figures

2A to 2D, i.e. that of Figure 2D. However, it will be appreciated that in other process embodiments, there may be further fabrication steps.

Such further fabrication steps are shown in a second process, illustrated in Figures 3A to 3H. This second process is in accordance with a method that follows the flowchart 100 of Figure 1.

The second process is a method to manufacture an all-back-contact (ABC) silicon wafer solar cell, which may be summarised as follows. P-type dopants are diffused into the rear surface of an n-type Si wafer substrate. A dielectric stack is then deposited at the rear surface of the device to effectively passivate the p-type doped regions. The patterning of the dielectric passivation on the rear surface can be realised by laser ablation and subsequently, n-type doped regions are formed in these areas. A dielectric stack is then provided on the rear surface to passivate the n-doped regions. These dielectric stacks will serve as masking layer to protect the rear surface while etching back the front-side n-type diffusion to form the front surface field (FSF). The front surface will then receive a dielectric layer stack which provides good electronic passivation and antireflection properties. Metal contacts are then made by screen printing of metal pastes onto the rear dielectric stack, followed by a fast firing process whereby the metal electrodes penetrate through the dielectric stack to form electrical contact to the underlying heavily doped silicon regions. Further detail on the second process is provided below.

A cross-sectional view of a starting wafer 300, used to fabricate a solar cell 380 (see Figure 3H), is shown in Figure 3A. In one embodiment, silicon may be used for the wafer 300, although other materials such as germanium or a compound like gallium arsenide may be used. The wafer 300 may be n-type doped in the resistivity range of 0.5-10 Ohm-cm and may have a starting thickness of 50-200 pm and a bulk minority carrier lifetime of greater than 0.5 ms.

The wafer 300 has a surface 302 (interchangeably referred to as the rear surface) and an opposite surface 304 (interchangeably referred to as the front surface).

A caustic etch (KOH, NaOH, TMAH or similar) may be used to texture the front surface 304 of the wafer 300 by using the rear surface 302, doped with p-type dopant (such as Boron), as a texturing-stop-layer. In a preferred embodiment, the front surface 304 of the wafer 300 is modified for anti-reflectivity, by texturing the opposite surface 304 to be uneven. The opposite surface 304 may be made uneven by having the wafer 300 comprise a monocrystaHine structure having an orientation aligned to form a non-planar texture having protrusions on the opposite surface 304, such as using monocrystaHine wafers of orientation <100>, leading to the formation 0fupi¾§fct pyr mids !¾Μ¾¾ <Φ > oriented sidewalls. The typical height of the pyramids is in the range of 1-10 pm. The texture reduces reflection losses at the front surface 304, thereby improving the efficiency of the solar cell 380 (see Figure 3H) by raising the short-circuit current density.

The rear surface 302 is doped with dopant having an opposite polarity to that of the bulk material. In the preferred embodiment, where the wafer 300 is bulk n-type doped, the rear surface 302 is doped with dopant of a first polarity (for instance p- type doping realised by standard high-temperature boron diffusion in a tube furnace) to form a first doped region 301. Typical p-n junction depth is around 0.1-2 pm and the sheet resistance of the p+ layer is typically in the range of 5-150 Ohm/square.

Then follows a wet etch to remove the boron silicate glass (BSG) and the subsequent formation of a passivation layer 206 on the rear surface 302, as shown in Figure 3B. The purpose of the passivation layer 206 provides a dielectric stack at the rear surface 302 of the solar cell 380 (see Figure 3H) to reduce the surface recombination rate. Several dielectric materials can be used for the passivation layer 206, such as a thermal silicon oxide (Si02), PECVD or LPCVD grown silicon oxide (SiOx), PECVD or LPCVD or sputtered silicon nitride (SiNx), PECVD or LPCVD or sputtered aluminium oxide (AIOx), PECVD grown or sputtered hydrogenated amorphous silicon (a-Si:H), or stacks of these materials. (PECVD stands for plasma- enhanced chemical vapour deposition; LPCVD stands for low-pressure chemical vapour deposition).

As shown in Figure 3C, a patterned passivation layer 208 is formed from the dielectric stack on the rear surface 302 (i.e. portions of the passivation layer 206 in contact with the rear surface 302 of the wafer 300 are locally removed). In the preferred embodiment, the passivation layer 206 is patterned by using laser ablation. The laser ablation creates trenches 210 or open lines approximately 100 to 3000 μιτι wide. Further fabrication (shown in Figures 3D to 3H) is then masklessly performed over the patterned passivation layer 208, i.e. a mask is not used, to perform the subsequent steps to fabricate the solar cell 380 (see Figure 3H).

The trenches 210 (refer to Figure 3C) that result after forming the patterned passivation layer 208 are further etched (to form deeper trenches, shown as reference numeral 212 in Figure 3D). This further etching is for removing portions of the wafer 300 damaged when forming the patterned passivation layer 208. The patterned passivation layer 208 serves to confine the further etching to the trenches 210, so that the patterned passivation layer 208 acts as a protective layer to the portions of the surface 202 that the patterned passivation layer 208 covers, which are not etched. In the preferred embodiment where laser ablation is used to pattern the passivation layer 206 (i.e. from Figure 3B to Figure 3C), the openings of the patterned passivation layer 208 are wet-chemically etched and cleaned to remove potential laser damage. In the preferred embodiment, a hydrofluoric acid (HF) dip is then used to remove the glassy layer left after the laser ablation process. Then, a caustic etch (using, for example, concentrated KOH, NaOH or TMAH) is used to etch about 0.1 to 5 pm of silicon, thereby removing the p-n junction in the exposed regions of the rear surface 302. These trenches 212 (i.e. the further etched trenches in the rear surface 302 of the wafer 300) are then doped with dopant of second polarity that is opposite to the dopant of the first polarity to form a second doped region 313. During doping of the trenches 212, the patterned passivation layer 208 acts as a diffusion barrier to the dopant of second polarity for the portions of the surface 302 that the patterned passivation layer 208 covers.

In one embodiment (not shown), the wafer 300 may be diffused only on the rear surface 302 by front-to-front loading of wafers 300 into diffusion boats. However, in the preferred embodiment, during doping of the trenches 212, the front surface 304 of the wafer 300 is simultaneously doped with dopant of the second polarity. As shown in Figure 3D, the wafer 300 may be diffused on both sides (i.e. both the front surface 304 and the rear surface 302) in a high-temperature diffusion furnace to form an n+ layer on both sides to form both the BSF (back surface field) and FSF (front surface field). This has the advantage of forming the BSF and the FSF in one diffusion process, instead of two separate diffusion processes. In the preferred embodiment, a liquid phosphorus source (POC13) is used for the dopant of the second polarity. In the preferred embodiment, the junction depth of the n+ diffusion is in the range of 0.1 to 2 pm and the sheet resistance in the range of 5 to 100 Ohm/square. The n+ layer at the rear forms a back-surface-field (BSF) layer, which reduces the recombination losses in the solar cell and the contact resistance losses at the base contact; at the front side, a front-surface-field (FSF) is created to repel minority charge carriers and reduce lateral resistivity.

Although not shown in Figure 3E, a wet chemical etch removes phosphorus silicate glass (PSG) formed after the doping of both opposing surfaces (302 and 304) of the wafer 300. In Figure 3E, a further passivation layer 310 is formed to be in contact with both the patterned passivation layer 208 and the trenches 212. The further passivation layer 310 may be formed by deposition on the rear surface 302 of the wafer 300. In the preferred embodiment, various layers can be used, such as a thermal silicon oxide (Si02), PECVD or LPCVD grown silicon oxide (SiOx), PECVD or LPCVD or sputtered silicon nitride (SiNx), PECVD or LPCVD or sputtered aluminium oxide (AIOx), PECVD grown or sputtered hydrogenated amorphous silicon (a-Si:H), or stacks of these materials. The further passivation layer 310 serves to protect the doped trenches 212 during subsequent etch back of the front surface 304, described with reference to Figure 3F.

Next, as shown in Figure 3F the wafer 300 may be thinned from its front surface 304. For instance, an etch-back solution (such as T AH, KOH, NaOH, or similar) is used to etch back the n+ layer on the front side. In the preferred embodiment, the preferred sheet resistance of the n+ layer on the front, after etch back, is around 80-300 Ohm/square.

In addition, or as a substitute, to the above mentioned texturing of the front surface 304, the front surface 304 of the wafer 300 is modified for anti-reflectivity by applying an anti-reflective coating 314 on the opposite surface 304 of the wafer 300. As shown in Figure 3G, a dielectric film or stack may be deposited on the front side, to serve as antireflection coating (ARC) and surface passivation layer. In the preferred embodiment, the dielectric layer may be a PECVD grown silicon nitride (SiNx).

As shown in Figure 3H, the solar cell 380 is finished after screen-print metallisation of both n-doped regions (i.e. the second doped regions 313) and p- doped regions (i.e. the first doped regions 301 ) at the rear surface 302. This is achieved by providing a first set of electrodes 316 to make contact with the trenches 312 (where the walls of the trenches 312 are doped with dopant of a second polarity) and providing a second set of electrodes 318 to make contact with the surface 302 of the wafer 300 doped with dopant of a first polarity. The metal pastes used may be fritted glass-nnetal pastes, which provide a good contact resistance by firing the pastes at high temperature to make contact through the dielectric surface passivation stack provided by the patterned passivation layer 208. Typical firing temperatures are around 550-800 °C.

At the various fabrication steps described above, the patterned passivation layer 208 serves different functions. By leaving the patterned passivation layer 208 on the rear surface 302 of the wafer 300, the patterned passivation layer 208 remains in the finished device to reduce the surface recombination rate. During laser damage removal, as described with reference to Figure 3D, the patterned passivation layer 208 serves to confine the further etching to the trenches 210. During doping of the trenches 212, the patterned passivation layer 208 acts as a diffusion barrier to the dopant of second polarity for the portions of the surface 302 that the patterned passivation layer 208 covers. Accordingly, the patterned passivation layer 208 acts as a multi-functional layer, which remains after the solar cell 380 is fabricated.

Also from the above, the preferred embodiment uses p-type dopant as dopant of the first polarity to form the first doped region 301 and n-type dopant as dopant of the second polarity to form the second doped region 313. However, in another embodiment, the dopant of the first polarity to form the first doped region 301 is n- type; while the dopant of the second polarity to form the second doped region 313 is p-type. A modification of the preferred embodiment has the n+ front-surface-field (FSF) shown in Figure 3D replaced with a p+ diffused FSF to create a floating p-n junction to provide good surface passivation. With reference to Figure 3A, this p+ FSF is created by applying a single p+ diffusion to diffuse both sides (302 and 304) of the wafer 300 (Figure 3A only shows that the rear surface 302 is doped). Thus, during doping of the surface 302 with dopant of the first polarity, the opposite surface 304 of the wafer 300 is simultaneously doped with dopant of the first polarity. This modification further contrasts with the preferred embodiment in that during doping of the trenches 212 described in Figure 3D, only the rear surface 302 is doped (i.e. the front surface 304, already doped p+ in this modification, is not simultaneously doped with the rear surface 302). Further, during thinning of the wafer 300 shown in Figure 3F, the p+ layer on the front surface 304 is etched back.

In another modification, the n+ front-surface-field (FSF) shown in Figure 3D can be eliminated if, for instance, fixed charges are present in a passivation layer (such as fixed charges in SiN or Al₂0₃) formed on the front surface 304 of the wafer 300 to create good surface passivation. An example of this is described in Figures 4A to 4F below.

Figures 4A to 4F illustrate a third process to fabricate a solar cell in accordance with a method that follows the flowchart 100 of Figure 1.

Figure 4A shows a wafer 400 that has a surface 402 (interchangeably referred to as the rear surface) and an opposite surface 404 (interchangeably referred to as the front surface). The wafer 400 has undergone fabrication as shown in Figures 2A and 2B, resulting in a front surface 404 which is not additionally doped. The structure of the wafer 400 in Figure 4A can be specifically obtained for example by applying the processes in Figures 3A-3C. Accordingly, a patterned passivation layer 208 is formed on the surface 402 (i.e. the rear surface of the wafer 400). Similar to the process shown in Figure 2C, the patterned passivation layer 208 may be formed by laser ablation of a passivation layer in contact with the surface of the wafer 400.

Prior to the formation of the patterned passivation layer 208, the rear surface

402 of the wafer 400 is doped with dopant of a first polarity to form a first doped region 401. In forming the patterned passivation layer 208, trenches 210 are formed in the surface 402 of the wafer 400. Further fabrication (shown in Figures 4B to 4F) is then masklessly performed over the patterned passivation layer 208, i.e. a mask is not used, to perform the subsequent steps to fabricate a solar cell.

The trenches 210 (refer to Figure 4A) that result after forming the patterned passivation layer 208 are further etched (to form deeper trenches, shown as reference numeral 212 in Figure 4B) in a similar manner as described with reference to Figure 3C. These trenches 212 are then doped with dopant of second polarity that is opposite to the dopant of the first polarity to form a second doped region 413. At the same time the front surface 404 will also be doped with dopants of the second polarity, leading to Figure 4B. Next, In Figure 4C, a further passivation layer 410 is formed to be in contact with both the patterned passivation layer 208 and the trenches 212. The further passivation layer 410 may be formed by deposition on the rear surface 402 of the wafer 400. In the preferred embodiment, various layers can be used, such as a thermal silicon oxide (Si0₂), PECVD or LPCVD grown silicon oxide (SiO_x), PECVD or LPCVD or sputtered silicon nitride (SiNx), PECVD or LPCVD or sputtered aluminium oxide (AIO_x), PECVD grown or sputtered hydrogenated amorphous silicon (a-Si:H), or stacks of these materials. Next, in Figure 4D, the front surface 404 of the wafer 400 is thinned from the opposite surface 404 after doping of the trenches 212 until the dopant concentration in this surface 404 is at the same level as the background dopant concentration of the wafer 400. Thinning of the wafer 400 has the advantage of improving the blue response of the fabricated solar cell.

In Figure 4E, an additional passivation layer 450 is formed on the front surface 404 of the wafer. The additional passivation layer 450 may comprise SiN or Al₂0₃ and fixed charges are introduced into the additional passivation layer 450, as an alternative to having the n+ front surface field shown in Figure 3D. In Figure 4E, the front surface 404 of the wafer 400 is modified for anti-reflectivity. In the embodiment shown in Figure 4E, the front surface 404 of the wafer 400 is modified for anti-reflectivity by applying an anti-reflective coating 414 on the additional passivation layer 450 that is on the front surface 404 of the wafer 400. In addition, or as a substitute, to the anti-reflective coat 414, the front surface of the wafer may have been modified for anti-reflectivity by texturing the opposite surface 404 to be uneven. The opposite surface 404 may be made uneven by having the wafer 400 comprise a monocrystalline structure having an orientation aligned to form protrusions on the opposite surface 404.

In Figure 4F, a first set of electrodes 416 is provided to be in contact with the trenches 212 and a second set of electrodes 418 is provided to be in contact with the surface 402 of the wafer 400 doped with dopant of a first polarity. Although not shown, the first set of electrodes 416 and the second set of electrodes 418 may be screen printed and subsequent fired for penetration to make the respective contact.

In one embodiment, the dopant of the first polarity to form the first doped region 401 is p-type and the dopant of the second polarity to form the second doped region 413 is n-type. In another embodiment, the dopant of the first polarity to form the first doped region 401 is n-type and the dopant of the second polarity to form the second doped region 413 is p-type.

From the above, various embodiments uses the following concepts to reduce processing steps, in order to decrease the manufacturing costs:

Use of a surface passivating layer as diffusion barrier for the back surface field and maintaining the surface passivation layer throughout the subsequent process;

Diffusion of back surface field (BSF) and front surface field (FSF) in one diffusion process instead of two separate diffusion processes; and

Use of a surface passivating layer as etch-back mask to reduce doping concentration of the FSF for improved blue response

The preferred embodiment (shown in Figures 3A to 3H), which utilises screen printing for the formation of the metal contacts (316 and 318) of the all-back-contact silicon wafer solar cell 380, can be readily manufactured using processing techniques that are less expensive than micro-electronic circuit processing.

Forming the interdigitated doped regions can be achieved by first applying one dopant type (to form a first doped region 301 , as shown in Figure 3A) to the entire silicon wafer rear surface 302 by means of diffusion, ion implantation, or laser doping. Then, a laser ablation of a masking layer (the masking layer is provided by the passivation layer 206, see Figure 3B; which after laser ablation forms the patterned passivation layer 208, see Figure 3C), followed by a subsequent etching step is used to form the oppositely-doped region (i.e. the second doped region 313) by means of diffusion or laser doping.

By applying a dielectric stack at the front and rear surface (i.e. the anti- reflective coat 314 on the front surface 304; and the combination of the patterned passivation layer 208 and the further passivation layer 3 0 on the rear surface 302), the surface recombination rate is reduced. The surface can be passivated by dielectric materials, such as a thermal silicon oxide (Si0₂), PECVD/LPCVD silicon oxide (SiOx), PECVD/LPCVD silicon nitride (SiN_x), aluminium oxide (AIO_x), hydrogenated amorphous silicon (a-Si:H), or stacks of these materials. A metal paste is preferably applied by screen-printing techniques and co-fired for both polarities through the rear dielectric stack. Alternatively, small line openings are fabricated using laser ablation techniques.

The front of the cell (i.e. the front surface 304) is preferably textured. The dielectric stack at the front (i.e. the anti-reflective coat 314 on the front surface 304) simultaneously provides surface passivation and anti-reflective properties. The following describes other modifications to the preferred embodiment to realise the solar cell.

Modified embodiment 1

Same as the preferred embodiment except that the p+ and n+ doped regions are applied by ion implantation, i.e. using carbon-fibre masks for patterning. Alternatively, solid or gaseous dopant sources can be used as diffusion sources for both p+ and n+ doping.

Modified embodiment 2

Same as the preferred embodiment, wherein amorphous silicon oxide (a- Si:H), AIOx, Si02, SiNx or stacks of those, grown or deposited by all means, can be used.

Modified embodiment 3

Same as the preferred embodiment, wherein the polarity of the diffusions are reversed when using a p-doped wafer.

Modified embodiment 4

Same as the preferred embodiment, wherein the sequence of the diffusions can be reversed where n-doped BSF can be formed first followed by a p-doped emitter diffusion. Modified embodiment 5

Same as the preferred embodiment, wherein a liquid dopant source is applied via spray-on, roll-on, or spin-on to diffuse the n+ regions.

Modified embodiment 6

Same as the preferred embodiment, wherein the fritted glass-metal paste can be replaced by a non-fritted paste. For that, laser ablation could be applied to provide local openings in the dielectric surface passivation stack.

Modified embodiment 7

Same as the preferred embodiment, wherein a fritted glass-metal paste can be applied to print a 3-5 μητι seed layer only to make good contact resistance. On top of the seed layer a non-fritted metal paste will be printed by screen-printing methods or inkjet-printing methods to greatly increase the thickness of the seed layer.

Modified embodiment 8

Same as the preferred embodiment, wherein laser doping will be used to form a heavier diffusion region 540 (see Figure 5) in the emitter layer 501 (selective emitter; this provides the possibility to diffuse in the range of 100 Ohm/sq and use the selective emitter to dope in the range of 5-40 Ohm/sq to improve the contact resistance of the screen printed metal contacts 516 and 518) and to reduce recombination losses. The laser doping can be applied by using the BSG (borosilicate glass) layer (i.e. the first doped region 301 ) formed during the boron diffusion shown in Figure 3A. Alternatively, the selective emitter can be formed at a later stage by applying a liquid dopant source via spray-on, roll-on, or spin-on to laser dope the p++ selective-emitter lines. The resulting final structure is shown in Figure 5.

Modified embodiment 9

Same as the preferred embodiment, wherein laser doping (laser chemical processing) will be used to form the heavy diffusion in the base contact (selective BSF).

Modified embodiment 10

Same as the preferred embodiment, wherein the texture etch step is carried out after the doping mask step to remove any residual Boron diffusion on the front side. In modified embodiment 10, fabrication of a solar cell begins by front-to-front loading of two wafers, whereby a first doped region (using, for example-,. Boron) is formed (using, for example, diffusion) in the rear surfaces of the two wafers. Residual Boron, from this diffusion, on the front side is restricted to be around the edges on the front side of each of these wafers. This residual Boron is removed during caustic etch to texture each front surface of the wafers for anti-refiectivity. In the preferred embodiment, this caustic etch is performed before the rear surface of a wafer is doped (refer to the description above in respect of Figure 3A). However, in modified embodiment 10, the caustic etch is performed after doping of the trenches formed in the rear surfaces of each of the two wafers, in the manner described with respect to Figure 3D.

It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the embodiments without departing from a spirit or scope of the invention as broadly described. The embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive.

Claims

1. A method of fabricating a solar cell comprising:

forming a patterned passivation layer that is in contact with a surface of a wafer, the surface being doped with dopant of a first polarity; and

maskless!y performing over the patterned passivation layer, a fabrication step selected from the steps of: etching further, trenches in the surface of the wafer that result after forming the patterned passivation layer; and doping the trenches with dopant of second polarity that is opposite to the dopant of the first polarity.

2. The method of claim , wherein during doping of the surface with dopant of the first polarity, an opposite surface of the wafer is simultaneously doped with dopant of the first polarity.

3. The method of claim 2, wherein the steps further comprise

forming a further passivation layer in contact with both the patterned passivation layer and the trenches; and

thinning the wafer from the opposite surface of the wafer.

4. The method of claim 1 , wherein the steps further comprise

forming a further passivation layer in contact with both the patterned passivation layer and the trenches;

forming an additional passivation layer on an opposite surface of the wafer; and

introducing charges into the additional passivation layer.

5. The method of claim 1 , wherein the steps further comprise

thinning the wafer from an opposite surface of the wafer.

6. The method of claim 5, wherein during doping of the trenches, the opposite surface of the wafer is simultaneously doped with dopant of the second polarity.

7. The method of any one of the preceding claims, wherein the patterned passivation layer is formed by laser ablation of a passivation layer in contact with the surface of a wafer.

8. The method of claims 2 to 7, wherein the opposite surface of the wafer is modified for anti-reflectivity.

9. The method of claim 8, wherein the opposite surface of the wafer is modified for anti-reflectivity by texturing the opposite surface to be uneven.

10. The method of claim 9, wherein the opposite surface is made uneven by having the wafer comprise a monocrystalline structure having an orientation aligned to form protrusions on the opposite surface.

11. The method of claims 8 to 10, wherein the opposite surface of the wafer is modified for anti-reflectivity by applying an anti-reflective coat on the opposite surface of the wafer.

12. The method of any one of the preceding claims, further comprising providing a first set of electrodes in contact with the trenches and a second set of electrodes in contact with the surface of the wafer doped with dopant of a first polarity.

13. The method of claim 12, wherein the first and the second set of electrodes are screen printed and subsequent fired for penetration to make the respective contact.

14. The method of any one of the preceding claims, wherein the dopant of the first polarity is p-type and the dopant of the second polarity is n-type.

15. The method of claims 1 to 13, wherein the dopant of the first polarity is n- type and the dopant of the second polarity is p-type.