CN115732597A - Preparation method of TOPCon battery selective emitter and passivation contact structure - Google Patents
Preparation method of TOPCon battery selective emitter and passivation contact structure Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 69
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 59
- 230000008569 process Effects 0.000 claims abstract description 39
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052796 boron Inorganic materials 0.000 claims abstract description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 26
- 230000005641 tunneling Effects 0.000 claims abstract description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 15
- 239000011574 phosphorus Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 63
- 229910052710 silicon Inorganic materials 0.000 claims description 63
- 239000010703 silicon Substances 0.000 claims description 63
- 239000007789 gas Substances 0.000 claims description 37
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 30
- 238000006243 chemical reaction Methods 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 16
- 229910052786 argon Inorganic materials 0.000 claims description 15
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 15
- 239000011261 inert gas Substances 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 238000005240 physical vapour deposition Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
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- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 6
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- 150000002500 ions Chemical class 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
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- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 239000003513 alkali Substances 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 229910000085 borane Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
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- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000004804 winding Methods 0.000 claims description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
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- 238000004519 manufacturing process Methods 0.000 abstract description 6
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- DJDFFEBSKJCGHC-UHFFFAOYSA-N Naphazoline Chemical compound Cl.C=1C=CC2=CC=CC=C2C=1CC1=NCCN1 DJDFFEBSKJCGHC-UHFFFAOYSA-N 0.000 description 1
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention relates to the technical field of battery manufacturing, in particular to a preparation method of a TOPCon battery selective emitter and a passivation contact structure, wherein a plate type process is used for preparing boron doped layers and phosphorus doped layers on the front side and the back side of a battery respectively, the boron doped layers on the front side, a silicon nitride covering layer, a tunneling oxide layer on the back side and a phosphorus doped crystalline silicon thin layer can be processed by the same equipment, and the high-temperature impurity activation of the boron doped layers and the phosphorus doped crystalline silicon thin layers can be synchronously carried out; the doping layer prepared by plating under the plate-type process has good selectivity and avoids plating around; and a silicon nitride layer is covered outside the boron doped layer, so that the problem that boron is difficult to activate is solved.
Description
Technical Field
The invention relates to the technical field of battery manufacturing, in particular to a preparation method of a TOPCon battery selective emitter and passivation contact structure.
Background
The preparation of the crystalline silicon solar cell is in the trend of flaking, and when the diffusion length of a minority carrier is greater than the thickness of the silicon wafer, the efficiency of the solar cell is particularly obviously influenced by the recombination rate of the surface of the silicon wafer with a certain thickness. Therefore, the prior art mostly passivates the surface of crystalline silicon. One more advanced technology is the tunnel oxide passivation contact (TOPCon) technology; the passivation tunneling technology adopts an N-type silicon wafer as a substrate, and a tunneling layer is deposited on the front surface and the back surface of the silicon wafer; then covering a layer of phosphorus-doped thin film silicon layer; thereby forming a tunnel oxide passivation contact. The tunneling oxide layer passivation technology can form a tunneling film between the electrode and the substrate, so that the metal electrode is isolated from being in contact with the substrate, the contact recombination loss is reduced, and the current transmission cannot be influenced by the electron energy tunneling film.
The passivation of the N surface is solved by the N-type passivation contact battery structure, but the recombination of the surface of the emitter is still high, which becomes the bottleneck of improving the efficiency, and the two factors of passivation and contact resistance need to be considered for reducing the recombination of the surface of the emitter. The current mainstream technical route is to select laser doping and combine boron diffusion to form a selective emitter. Boron selective emitter preparation is also a worldwide problem because boron is much more difficult to activate than phosphorus. In addition, in the prior technical scheme, both front boron diffusion and back phosphorus doping need to be carried out through high-temperature steps, and the two high-temperature steps are independently carried out for a long time. The method also comprises the steps of directly printing patterned doped amorphous silicon, using acid-base resistant slurry as a patterned mask and the like, and the method introduces the printing of chemical slurry, the preparation of the mask, the cleaning of the mask and the like in the preparation process, has complex process and is easy to cause pollution. Therefore, how to simply and quickly prepare the front surface local passivation contact structure is a major concern of researchers at present.
The prior patent CN111952409A, entitled a method for manufacturing a passivated contact cell with a selective emitter structure, describes that front side boron diffusion P + and P + + are prepared using two-step diffusion annealing, which takes 120-300min; the prior printing of doping pastes in selective areas is prone to introduce contamination.
In the prior patent CN2020103393987, the name is a method for preparing a selective emitter, the emitter described in the patent is prepared by high temperature twice boron diffusion, the steps are many, and a sample after boron diffusion needs to be edged.
The above two patents have the following technical drawbacks:
1) When the front boron diffusion layer and the back doped thin film silicon layer need to be prepared separately, the preparation process can be carried out at high temperature, and the time is long;
2) The boron diffusion process can generate the winding plating, the winding plating is carried out on the diffusion layer on the back, and the edge carving process is needed;
3) The boron selective emitter is difficult to activate during preparation.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a preparation method of a TOPCon battery selective emitter and passivation contact structure.
The technical scheme for realizing the purpose of the invention is as follows: a preparation method of a TOPCon battery selective emitter and passivation contact structure comprises the following steps:
s1, preprocessing crystalline silicon and texturing on two sides, sequentially preparing a boron-doped crystalline silicon layer and a silicon nitride layer on the front side of the crystalline silicon,
s2, performing alkali polishing treatment on the back surface of the crystalline silicon, and sequentially preparing a tunneling oxide layer and a phosphorus-doped crystalline silicon layer on the back surface of the crystalline silicon;
and S3, carrying out graphical scanning on the amorphous silicon layer on the front surface of the crystalline silicon by using a laser, wherein the scanning area is consistent with the metalized area, and finishing the selective preparation.
S4, stacking the samples subjected to the step S3 in a back-to-back mode, allowing the stacked samples to enter a high-temperature annealing furnace for annealing, introducing one or more of nitrogen, dry oxygen and wet oxygen in the annealing process, promoting impurity diffusion in the annealing process by using the introduced gas, facilitating subsequent cleaning of products, and preparing a layer of silicon oxide on the front surface of crystalline silicon;
s5: and cleaning the front-side oxide layer (namely the annealed boron-doped crystalline silicon layer and the annealed silicon nitride layer), the silicon nitride layer and the diffusion-around oxide layer (namely the annealed tunneling oxide layer and the annealed phosphorus-doped crystalline silicon layer) on the back side of the crystalline silicon.
In S2, the thickness of the boron-doped crystalline silicon layer is 10-35nm, and the thickness of the silicon nitride layer is 5-10nm; the thickness of the tunneling oxide layer is 0.6-2nm, and the thickness of the phosphorus-doped crystalline silicon layer is 60-160nm.
In the above technical solution S2, the boron-doped silicon layer is prepared by PVD, and includes the following steps:
step 1a, the silicon wafer processed in the step 1 is laid on a support plate and enters a vacuum reaction cavity along with the support plate, a doped silicon target is placed in the vacuum reaction cavity, silicon on the silicon target is sputtered off in a magnetron sputtering mode, and amorphous silicon is formed on the surface of the silicon wafer;
step 1b, in the step 1a, doped amorphous silicon is formed by dropping the doping elements in the silicon target together, the surface is bombarded by adopting inert gas in magnetron sputtering, the doping elements are boron,
step 1c, if the doping concentration in step 1b is insufficient, additionally introducing doping gas or mixed gas of the doping gas and argon gas to further increase the doping concentration;
wherein, the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the inert gas is argon, the doping gas is borane, and the process temperature is 100-500 ℃.
In the above technical scheme S2, the silicon nitride layer is prepared by PVD, and the following method is adopted: the silicon chip is placed on a support plate in a flat manner and enters a vacuum reaction chamber along with the support plate, a doped silicon target is placed in the vacuum reaction chamber, silicon on the silicon target is sputtered in a magnetron sputtering mode, nitrogen is introduced at the same time, and one or a plurality of mixed gases of ammonia, hydrogen and silane are introduced along with the introduction of the nitrogen, wherein the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the sputtering gas is argon, and the process temperature is 100-500 ℃.
In the above technical scheme S2, the tunneling oxide layer is prepared by ion oxidation, and is prepared by the following method: the silicon chip is laid on the support plate and enters the vacuum reaction cavity along with the support plate, oxygen is ionized by the linear ion source and then is introduced into the vacuum process cavity, the power supply adopts a radio frequency power supply, the process pressure is 3-50pa, and the process temperature is 50-400 ℃.
In the above technical solution S2, the phosphorus-doped silicon crystal layer is prepared by PVD, and includes the following steps:
step 2a, the silicon wafer processed in the step 1 is laid on a support plate and enters a vacuum reaction cavity along with the support plate, a doped silicon target is placed in the vacuum reaction cavity, silicon on the silicon target is sputtered off in a magnetron sputtering mode, and amorphous silicon is formed on the surface of the silicon wafer;
step 2b, in the step 2a, doped amorphous silicon is formed by dropping the doping elements in the silicon target together, the surface is bombarded by inert gas in magnetron sputtering, the doping elements are phosphorus,
step 2c, if the doping concentration in the step 2b is insufficient, additionally introducing doping gas or mixed gas of the doping gas and argon gas to further increase the doping concentration;
wherein, the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the inert gas is argon, the doping gas is phosphane, and the process temperature is 100-500 ℃.
In the above technical solution S3, the power of the laser is 10-50W, and the scanning speed is 1500-20000 mm/S.
In the technical scheme S4, the peak temperature is 750-950 ℃, and the time duration is 30-90min.
In the above technical solution S4, the thickness of the silicon oxide layer is greater than or equal to the sum of the thickness of the silicon nitride layer on the front surface of the crystalline silicon and the thickness of the boron-doped crystalline silicon layer.
In the technical scheme S5, an oxide layer generated in the annealing process is cleaned by a wet method, and the sheet resistance of a front lightly doped region in a cleaned sample is 90-200 omega/sq; the sheet resistance of the laser selective heavy area is 30-70 omega/sq; the sheet resistance of the back phosphorus doped layer is 20-100 omega/sq.
After the technical scheme is adopted, the invention has the following positive effects:
(1) According to the invention, a plate type process is used for preparing a boron doped layer and a phosphorus doped layer on the front side and the back side of the battery respectively, the boron doped layer of the front side emitter, the silicon nitride covering layer and the tunneling oxide layer of the back side passivation structure and the phosphorus doped silicon thin layer can be processed by the same equipment, and the high-temperature impurity activation of the boron doped layer and the phosphorus doped silicon thin layer can be synchronously carried out; the doping layer prepared by plating under the plate-type process has good selectivity and avoids plating around; and a silicon nitride layer is covered outside the boron doped layer, so that the problem that boron is difficult to activate is solved.
(2) The invention can reduce the production cost of TOPCon and shorten the production time: the high-temperature steps necessary for preparing the selective emitter on the front side of the battery and doping the polycrystalline silicon layer on the back side are combined into one, and the time of the high-temperature steps is shortened to be within 90 min; and (4) incorporating the front and back doped layers of the battery into the same platform for production.
(3) The invention can solve the problem that selective boron doping is difficult to activate: a boron-doped and silicon nitride covering thin layer is prepared on the front side of the cell by using a plate type process, and the square resistance of a local area can be reduced to be below 50 omega after the procedures of laser selective doping and high-temperature annealing. The boron doped layer is easy to activate after being covered with the silicon nitride, high temperature is not needed for long-time diffusion, and oxygen intervention in a laser process is reduced.
(4) The invention adopts a plate type process, the periphery of the selective silicon chip is not required to be carved, and the texturing and the polishing can be integrated into a procedure.
Drawings
FIG. 1 is a schematic view of S1 of the present invention;
FIG. 2 is a schematic view of S2 of the present invention;
FIG. 3 is a schematic view of S3 of the present invention;
FIG. 4 is a schematic view of S4 of the present invention;
FIG. 5 is a schematic view of S5 of the present invention; .
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1 to 5, the present invention provides a method for preparing a TOPCon cell selective emitter and passivation contact structure, comprising the following steps:
s1, preprocessing crystalline silicon, and sequentially preparing a boron-doped crystalline silicon layer and a silicon nitride layer on the front side of the crystalline silicon.
S2, performing alkali polishing treatment on the back surface of the crystalline silicon, wherein the texturing and the polishing can be integrated into a same process, and a tunneling oxide layer and a phosphorus-doped crystalline silicon layer are sequentially prepared on the back surface of the crystalline silicon; the OPCon battery front doping and the passivation contact structure are integrated on the same platform for processing.
And S3, carrying out graphical scanning on the amorphous silicon layers (namely the boron-doped crystalline silicon layer and the silicon nitride layer) on the front surface of the crystalline silicon by using a laser, wherein the scanning area is consistent with the metalized area, and finishing the selective preparation.
S4, stacking the samples subjected to the step S3 in a back-to-back mode, and annealing the stacked samples in a high-temperature annealing furnace, wherein one or more of nitrogen, dry oxygen and wet oxygen are introduced in the annealing process, and a layer of silicon oxide is prepared on the front side of the crystalline silicon; the TOPCon cell is prepared with a front boron doped crystalline silicon layer and a phosphorus doped crystalline silicon layer in advance, and is annealed uniformly to activate and redistribute impurities. And preparing silicon oxide in the high-temperature annealing process, and oxidizing the silicon nitride layer and the boron-doped crystalline silicon layer on the front surface to ensure that the silicon oxide is easy to clean. The back-to-back mode can reduce the influence of the silicon oxide prepared on the front side on the back side in the annealing process.
Front annealing process: impurities are distributed from the boron doped layer to the depth of the silicon wafer, and the front silicon nitride layer and the boron doped crystalline silicon layer are oxidized at high temperature, so that the subsequent cleaning is facilitated;
and a back annealing process for activating the impurities in the phosphorus-doped crystalline silicon layer. The crystalline silicon is converted into polycrystal at high temperature.
S5: and cleaning the front-side oxide layer (namely the annealed boron-doped crystalline silicon layer and the annealed silicon nitride layer), the silicon nitride layer and the diffusion-around oxide layer (namely the annealed tunneling oxide layer and the annealed phosphorus-doped crystalline silicon layer) on the back side of the crystalline silicon.
In S2, the thickness of the boron-doped crystalline silicon layer is 10-35nm, and the thickness of the silicon nitride layer is 5-10nm; the thickness of the tunneling oxide layer is 0.6-2nm, and the thickness of the phosphorus-doped crystalline silicon layer is 60-160nm.
In S2, the boron-doped crystalline silicon layer is prepared in a PVD mode and comprises the following preparation steps:
step 1a, the silicon wafer processed in the step 1 is laid on a support plate and enters a vacuum reaction cavity along with the support plate, a doped silicon target is placed in the vacuum reaction cavity, silicon on the silicon target is sputtered off in a magnetron sputtering mode, and amorphous silicon is formed on the surface of the silicon wafer;
step 1b, in the step 1a, doped amorphous silicon is formed by dropping the doping elements in the silicon target together, the surface is bombarded by inert gas in magnetron sputtering, the doping elements are boron,
step 1c, if the doping concentration in step 1b is insufficient, additionally introducing a doping gas or a mixed gas of the doping gas and argon gas to further increase the doping concentration;
wherein, the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the inert gas is argon, the doping gas is borane, and the process temperature is 100-500 ℃.
In S2, the silicon nitride layer is prepared in a PVD mode and is prepared by the following method: the silicon chip is placed on a support plate in a flat manner and enters a vacuum reaction chamber along with the support plate, a doped silicon target is placed in the vacuum reaction chamber, silicon on the silicon target is sputtered in a magnetron sputtering mode, nitrogen is introduced at the same time, and one or a plurality of mixed gases of ammonia, hydrogen and silane are introduced along with the introduction of the nitrogen, wherein the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the sputtering gas is argon, and the process temperature is 100-500 ℃.
In S2, the tunneling oxide layer is prepared in an ion oxidation mode by the following method: the silicon chip is laid on the support plate and enters the vacuum reaction cavity along with the support plate, oxygen is ionized by the linear ion source and then is introduced into the vacuum process cavity, the power supply adopts a radio frequency power supply, the process pressure is 3-50pa, and the process temperature is 50-400 ℃.
In S2, the phosphorus-doped crystalline silicon layer is prepared in a PVD mode and comprises the following preparation steps:
step 2a, the silicon wafer processed in the step 1 is laid on a support plate and enters a vacuum reaction cavity along with the support plate, a doped silicon target is placed in the vacuum reaction cavity, silicon on the silicon target is sputtered off in a magnetron sputtering mode, and amorphous silicon is formed on the surface of the silicon wafer;
step 2b, in the step 2a, doped amorphous silicon is formed by dropping the doping elements in the silicon target together, the surface is bombarded by inert gas in magnetron sputtering, the doping elements are phosphorus,
step 2c, if the doping concentration in the step 2b is insufficient, additionally introducing doping gas or mixed gas of the doping gas and argon gas to further increase the doping concentration;
wherein, the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the inert gas is argon, the doping gas is phosphane, and the process temperature is 100-500 ℃.
In S3, the power of the laser is 10-50W, and the scanning speed is 1500-20000 mm/S.
And in S4, the peak temperature is 750-950 ℃, and the time duration is 30-90min.
In S4, the thickness of the silicon oxide layer is greater than or equal to the sum of the thickness of the silicon nitride layer on the front surface of the crystalline silicon and the thickness of the boron-doped crystalline silicon layer.
S5, an oxide layer generated in the annealing process is cleaned by a wet method, and the sheet resistance of a front lightly doped region in the cleaned sample is 90-200 omega/sq; the sheet resistance of the laser selective heavy area is 30-70 omega/sq; the sheet resistance of the back phosphorus doped layer is 20-100 omega/sq.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A preparation method of a TOPCon battery selective emitter and passivation contact structure is characterized by comprising the following steps:
s1, preprocessing crystalline silicon, and sequentially preparing a boron-doped crystalline silicon layer and a silicon nitride layer on the front side of the crystalline silicon;
s2, performing alkali polishing treatment on the back surface of the crystalline silicon, and sequentially preparing a tunneling oxidation layer and a phosphorus-doped crystalline silicon layer on the back surface of the crystalline silicon;
and S3, carrying out graphical scanning on the amorphous silicon layer on the front surface of the crystalline silicon by using a laser, wherein the scanning area is consistent with the metalized area, and finishing the selective preparation.
S4, stacking the samples subjected to the step S3 in a back-to-back mode, and annealing the stacked samples in a high-temperature annealing furnace, wherein one or more of nitrogen, dry oxygen and wet oxygen are introduced in the annealing process, and a layer of silicon oxide is prepared on the front side of the crystalline silicon;
s5: and cleaning the front oxide layer and the silicon nitride layer of the crystalline silicon and the winding oxide layer on the back surface of the crystalline silicon.
2. The method of claim 1, wherein the method comprises steps of: in S2, the thickness of the boron-doped crystalline silicon layer is 10-35nm, and the thickness of the silicon nitride layer is 5-10nm; the thickness of the tunneling oxide layer is 0.6-2nm, and the thickness of the phosphorus-doped crystalline silicon layer is 60-160nm.
3. The method as claimed in claim 1, wherein in S2, the boron-doped crystalline silicon layer is formed by PVD, and the method comprises the following steps:
step 1a, the silicon wafer processed in the step 1 is laid on a support plate and enters a vacuum reaction cavity along with the support plate, a doped silicon target is placed in the vacuum reaction cavity, silicon on the silicon target is sputtered off in a magnetron sputtering mode, and amorphous silicon is formed on the surface of the silicon wafer;
step 1b, in the step 1a, doped amorphous silicon is formed by dropping the doping elements in the silicon target together, the surface is bombarded by inert gas in magnetron sputtering, the doping elements are boron,
step 1c, if the doping concentration in step 1b is insufficient, additionally introducing a doping gas or a mixed gas of the doping gas and argon gas to further increase the doping concentration;
wherein, the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the inert gas is argon, the doping gas is borane, and the process temperature is 100-500 ℃.
4. The method as claimed in claim 1, wherein in S2, the silicon nitride layer is formed by PVD, and the method comprises: the silicon chip is placed on a support plate in a flat manner and enters a vacuum reaction chamber along with the support plate, a doped silicon target is placed in the vacuum reaction chamber, silicon on the silicon target is sputtered in a magnetron sputtering mode, nitrogen is introduced at the same time, and one or a plurality of mixed gases of ammonia, hydrogen and silane are introduced along with the introduction of the nitrogen, wherein the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the sputtering gas is argon, and the process temperature is 100-500 ℃.
5. The method as claimed in claim 1, wherein in S2, the tunneling oxide layer is formed by ion oxidation, and the method includes: the silicon chip is laid on the support plate, and enters the vacuum reaction cavity along with the support plate, oxygen is ionized by the linear ion source and then is introduced into the vacuum process cavity, the power supply adopts a radio frequency power supply, the process pressure is 3-50pa, and the process temperature is 50-400 ℃.
6. The method as claimed in claim 1, wherein the phosphorous doped crystalline silicon layer in S2 is prepared by PVD method, and comprises the following steps:
step 2a, the silicon wafer processed in the step 1 is laid on a support plate and enters a vacuum reaction cavity along with the support plate, a doped silicon target is placed in the vacuum reaction cavity, silicon on the silicon target is sputtered off in a magnetron sputtering mode, and amorphous silicon is formed on the surface of the silicon wafer;
step 2b, in the step 2a, doped amorphous silicon is formed by dropping the doping elements in the silicon target together, the surface is bombarded by inert gas in magnetron sputtering, the doping elements are phosphorus,
step 2c, if the doping concentration in the step 2b is insufficient, doping gas or mixed gas of the doping gas and argon gas can be additionally introduced, and the doping concentration is further increased;
wherein, the power supply adopts one of a direct current power supply, an alternating current power supply and a pulse direct/alternating current power supply, the working pressure is 0.1-2Pa, the inert gas is argon, the doping gas is phosphane, and the process temperature is 100-500 ℃.
7. The method as claimed in claim 1, wherein in S3, the power of the laser is 10-50W, and the scanning speed is 1500-20000 mm/S.
8. The method as claimed in claim 1, wherein the peak temperature of S4 is 750-950 ℃ for 30-90min.
9. The method of claim 8, wherein the method comprises the steps of: in S4, the thickness of the silicon oxide layer is greater than or equal to the sum of the thickness of the silicon nitride layer on the front surface of the crystalline silicon and the thickness of the boron-doped crystalline silicon layer.
10. The method of claim 1, wherein the method comprises the steps of: s5, an oxide layer generated in the annealing process is cleaned by a wet method, and the sheet resistance of a front lightly doped region in the cleaned sample is 90-200 omega/sq; the sheet resistance of the laser selective heavy region is 30-70 omega/sq; the sheet resistance of the back phosphorus doped layer is 20-100 omega/sq.
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