CN113948607A - Selective diffusion method for preparing N-type selective emitter crystalline silicon battery and application thereof - Google Patents
Selective diffusion method for preparing N-type selective emitter crystalline silicon battery and application thereof Download PDFInfo
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 115
- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 55
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 93
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 69
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 69
- 239000010703 silicon Substances 0.000 claims abstract description 69
- 238000000151 deposition Methods 0.000 claims abstract description 64
- 229910052796 boron Inorganic materials 0.000 claims abstract description 59
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000004140 cleaning Methods 0.000 claims abstract description 27
- 229910052755 nonmetal Inorganic materials 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 48
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 28
- 238000002161 passivation Methods 0.000 claims description 24
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000005388 borosilicate glass Substances 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 238000005245 sintering Methods 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000004804 winding Methods 0.000 claims 1
- 238000011049 filling Methods 0.000 abstract description 10
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 31
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 18
- 238000007650 screen-printing Methods 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 9
- 239000000969 carrier Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 239000002002 slurry Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 230000001795 light effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The invention relates to the technical field of N-type crystalline silicon batteries, and discloses a selective diffusion method for preparing an N-type selective emitter crystalline silicon battery, which comprises the following steps: (1) performing low-concentration boron diffusion on the front surface of the textured silicon wafer to form a light doping layer; (2) depositing amorphous silicon on the lightly doped layer to form an amorphous silicon layer; (3) performing laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area; (4) performing high-concentration boron diffusion on the metal contact area after the amorphous silicon is removed to form a heavily doped layer; (5) and cleaning to remove the amorphous silicon in the non-metal area. The selective diffusion method of the invention adopts the amorphous silicon layer as the mask, can prevent the concentration of boron in the formed doped layer from being uncontrollable, and is beneficial to improving the open-circuit voltage, the short-circuit current and the filling factor of the N-type crystalline silicon battery.
Description
Technical Field
The invention relates to the technical field of N-type crystalline silicon batteries, in particular to a selective diffusion method for preparing an N-type selective emitter crystalline silicon battery.
Background
Compared with a P-type crystalline silicon battery, the N-type crystalline silicon battery has the advantages of long minority carrier lifetime, no light attenuation, good weak light effect, small temperature coefficient and the like, and is hopeful that the crystalline silicon solar battery advances to the theoretical highest efficiency. Boron diffusion is a core technology of N-type crystalline silicon batteries, the boron diffusion of the existing mass production N-type crystalline silicon batteries adopts a uniform junction process, the square resistance control range is 80-120 ohm, and the structure of the uniform junction battery is mainly limited by the characteristics of metal slurry. The low-concentration doping and shallow junction diffusion can effectively reduce the body and surface recombination probability of minority carriers, improve the collection rate of the carriers, reduce the reverse saturation current of the battery, and improve the open-circuit voltage Voc and the short-circuit current Isc of the battery, thereby effectively improving the conversion efficiency of the battery. However, the low-concentration shallow junction structure can provide new challenges for metal electrode paste, and low-concentration doping easily causes poor contact resistance, high series resistance of the battery, and low fill factor FF. Meanwhile, shallow junction diffusion easily increases the probability of electrode metal permeating into a PN junction region, thereby reducing the conversion efficiency of the battery.
Selective emitter technology has evolved for higher cell conversion efficiency. The low-concentration shallow junction is adopted in the non-metal contact area, the high-concentration deep junction is adopted in the metal contact area, the open-circuit voltage and the short-circuit current of the battery are improved, meanwhile, the series resistance of the battery is reduced, the filling factor of the battery is improved, and therefore the conversion efficiency of the battery is effectively improved. At present, the laser SE technology for mass production of P-type crystalline silicon batteries is mature, but due to the difference between the diffusion speed of boron and phosphorus, the laser SE technology for preparing the selective emitter of the P-type crystalline silicon battery is not suitable for the N-type crystalline silicon battery, and the selective emitter technology for boron diffusion becomes the problem to be solved urgently for improving the efficiency of the N-type crystalline silicon battery.
For example, patent CN200910029673.9 discloses a selective diffusion process for a crystalline silicon solar cell, which includes high concentration phosphorus diffusion in the front electrode grid line region and low concentration phosphorus diffusion outside the front electrode grid line region, and includes the following steps: firstly, cleaning and texturing a silicon wafer, preparing a layer of compact silicon dioxide film on the silicon wafer as a diffusion barrier layer, then selectively removing an oxide film in an electrode grid line region by adopting a laser grooving technology and forming a groove with a certain depth, then performing high-concentration phosphorus diffusion to form heavy doping in the electrode region, and simultaneously forming light doping outside the electrode region. When the method is applied to the preparation of the N-type selective emitter crystalline silicon battery, the diffusion speed of boron in silicon oxide is higher than that of crystalline silicon, so that the surface concentration is uncontrollable easily, and the performance of a selective emitter is influenced.
Disclosure of Invention
In order to solve the technical problem, the invention provides a selective diffusion method for preparing an N-type selective emitter crystalline silicon battery. The method adopts the amorphous silicon layer as a mask, can prevent the concentration of boron in the formed doped layer from being uncontrollable, and is beneficial to improving the open-circuit voltage, the short-circuit current and the filling factor of the N-type crystalline silicon battery.
The specific technical scheme of the invention is as follows:
a selective diffusion method for preparing an N-type selective emitter crystalline silicon cell comprises the following steps:
(1) performing low-concentration boron diffusion on the front surface of the textured silicon wafer to form a light doping layer;
(2) depositing amorphous silicon on the lightly doped layer to form an amorphous silicon layer;
(3) performing laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(4) performing high-concentration boron diffusion on the metal contact area after the amorphous silicon is removed to form a heavily doped layer;
(5) and cleaning to remove the amorphous silicon in the non-metal area.
By adopting the method, selective diffusion can be realized, an emitter with low surface concentration and shallow PN junction is formed in the nonmetal contact region, the recombination probability of minority carriers can be reduced, the collection rate of the carriers is improved, the reverse saturation current of the battery is reduced, the open-circuit voltage Voc and the short-circuit current Isc of the battery are improved, the contact resistance with metal paste is reduced, and the filling factor FF of the battery is improved; an emitter of a high-concentration and deep PN junction is formed in the metal contact area, so that the contact resistance of the metal slurry contact area can be reduced, the risk of burning through PN of slurry is reduced, and the fill factor FF of the battery is improved.
In addition, the amorphous silicon layer is used as a mask, and boron is slowly diffused in the amorphous silicon, so that the boron concentration in a formed doped layer can be prevented from being uncontrollable due to the fact that the boron penetrates through the amorphous silicon layer, and the open-circuit voltage, the short-circuit current and the filling factor of the N-type crystalline silicon battery can be improved; in addition, the polysilicon mask can be removed by cleaning, and the polysilicon mask cannot remain in the selective emitter to influence the performance of the cell.
Preferably, in the step (1), the diffusion sheet resistance of the low-concentration boron diffusion is 140-200 ohm, and the surface concentration (boron atoms) is 1.0e19～1.5e19 atoms/cm3The junction depth is 0.3 to 0.6 μm.
Preferably, in the step (4), the diffusion sheet resistance of the high-concentration boron diffusion is 60-100 ohm, and the surface concentration (boron atoms) is 2.0e19～3.0e19 atoms/cm3The junction depth is 0.6 to 1.0 μm.
Preferably, in the step (2), the thickness of the amorphous silicon layer is 80 to 200 nm.
Preferably, in step (2), amorphous silicon is deposited on the lightly doped layer using a Low Pressure Chemical Vapor Deposition (LPCVD) method.
A selective diffusion method for preparing an N-type selective emitter crystalline silicon cell comprises the following steps:
(I) depositing amorphous silicon on the front surface of the textured silicon wafer to form an amorphous silicon layer;
(II) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(III) carrying out high-concentration boron diffusion on the metal contact area after the amorphous silicon is removed to form a heavily doped layer;
(IV) cleaning to remove the amorphous silicon in the non-metal area;
and (V) performing low-concentration boron diffusion on the front surface of the cleaned silicon wafer to form a light doping layer.
Compared with the method of forming the light doping layer → depositing the mask → laser grooving → forming the heavy doping layer → removing the mask, the method of depositing the mask → laser grooving → forming the heavy doping layer → removing the mask → forming the light doping layer is adopted, the scheme forms the light doping in the last step, has the advantages of more controllable doping concentration and junction depth of the light doping region, can further improve the open-circuit voltage and the short-circuit current, and has better process stability.
Preferably, in the step (I), the thickness of the amorphous silicon layer is 80 to 200 nm.
Preferably, in step (I), amorphous silicon is deposited on the lightly doped layer using Low Pressure Chemical Vapor Deposition (LPCVD).
Preferably, in the step (III), the diffusion sheet resistance of the high-concentration boron diffusion is 60-100 ohm, and the surface concentration (boron atoms) is 2.0e19～3.0e19 atoms/cm3The junction depth is 0.6 to 1.0 μm.
Preferably, in the step (V), the diffusion sheet resistance of the low-concentration boron diffusion is 140-200 ohm, and the surface concentration (boron atoms) is 1.0e19～1.5e19 atoms/cm3The junction depth is 0.3 to 0.6 μm.
A method for preparing an N-type selective emitter crystalline silicon battery by using the selective diffusion method comprises the following steps: after the selective diffusion is completed by adopting the selective diffusion method, removing borosilicate glass (BSG) on the back and the edge by etching, depositing a silicon oxide layer and a phosphorus-doped polycrystalline silicon layer on the back, annealing and decoating, sequentially depositing an aluminum oxide passivation layer and a front silicon nitride layer on the front of a silicon wafer, depositing a back silicon nitride layer on the back of the silicon wafer, and obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Preferably, the thickness of the aluminum oxide passivation layer is 3-10 nm, the thickness of the front silicon nitride layer is 70-90 nm, and the thickness of the back silicon nitride layer is 70-90 nm.
Compared with the prior art, the invention has the following advantages:
(1) according to the invention, the emitter with low surface concentration and shallow PN junction is formed in the nonmetal contact region, and the emitter with high concentration and deep PN junction is formed in the metal contact region, so that the open-circuit voltage, the short-circuit current and the filling factor of the N-type crystalline silicon battery can be improved;
(2) the invention adopts the amorphous silicon layer as the mask to realize selective diffusion, can prevent the concentration of boron in the formed doped layer from being uncontrollable, and is beneficial to improving the open-circuit voltage, the short-circuit current and the filling factor of the N-type crystalline silicon battery.
Drawings
Fig. 1 is a schematic front side structure view of an N-type selective emitter crystalline silicon cell obtained by the present invention.
Detailed Description
The present invention will be further described with reference to the following examples.
General examples
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
the first scheme is as follows:
(2.1) performing low-concentration boron diffusion on the front surface of the textured silicon wafer, wherein the diffusion sheet resistance is 140-200 ohm, and the surface concentration is 1.0e19～1.5e19 atoms/cm3Deep knot0.3 to 0.6 μm, forming a lightly doped layer (i.e., P)+A layer);
(2.2) depositing amorphous silicon on the lightly doped layer by adopting an LPCVD (low pressure chemical vapor deposition) method to form an amorphous silicon layer with the thickness of 80-200 nm;
(2.3) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(2.4) carrying out high-concentration boron diffusion in the metal contact area after removing the amorphous silicon, wherein the diffusion sheet resistance is 60-100 ohm, and the surface concentration is 2.0e19～3.0e19 atoms/cm3The junction depth is 0.6-1.0 μm, forming a heavily doped layer (i.e. P)++A layer);
(2.5) cleaning to remove the amorphous silicon in the non-metal area;
scheme II:
(2.1) depositing amorphous silicon on the front surface of the textured silicon wafer by adopting an LPCVD (low pressure chemical vapor deposition) method to form an amorphous silicon layer with the thickness of 80-200 nm; (2.2) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(2.3) carrying out high-concentration boron diffusion in the metal contact area after removing the amorphous silicon, wherein the diffusion sheet resistance is 60-100 ohm, and the surface concentration is 2.0e19～3.0e19 atoms/cm3The junction depth is 0.6-1.0 μm, forming a heavily doped layer (i.e. P)++A layer);
(2.4) cleaning to remove the amorphous silicon in the non-metal area;
(2.5) performing low-concentration boron diffusion on the front surface of the cleaned silicon wafer, wherein the diffusion sheet resistance is 140-200 ohm, and the surface concentration is 1.0e19～1.5e19 atoms/cm3The junction depth is 0.3-0.6 μm, forming a lightly doped layer (i.e. P)+A layer);
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer and a phosphorus-doped polycrystalline silicon layer on the back surface of the silicon wafer by adopting an LPCVD (low pressure chemical vapor deposition) method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing aluminum oxide on the front surface of the silicon wafer to form an aluminum oxide passivation layer (AlO) with the thickness of 3-10 nmxA layer);
(8) in thatDepositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer (SiN) with a thickness of 70-90 nmxA layer);
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the back silicon nitride layer is 70-90 nm;
(10) after screen printing and sintering, an N-type selective emitter crystalline silicon cell is obtained, and the front structure of the cell is shown in fig. 1.
Example 1
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
(2.1) performing low-concentration boron diffusion on the front surface of the textured silicon wafer, wherein the diffusion sheet resistance is 140ohm, and the surface concentration is 1.2e19atoms/cm3The junction depth is 0.6 μm, and a light doping layer is formed;
(2.2) depositing amorphous silicon on the lightly doped layer by adopting an LPCVD (low pressure chemical vapor deposition) method to form an amorphous silicon layer with the thickness of 80 nm;
(2.3) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(2.4) performing high-concentration boron diffusion in the metal contact area after removing the amorphous silicon, wherein the diffusion sheet resistance is 60ohm, and the surface concentration is 3.0e19 atoms/cm3Forming a heavily doped layer with a junction depth of 1.0 μm;
(2.5) cleaning to remove the amorphous silicon in the non-metal area;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 6 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 70 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the back silicon nitride layer is 70 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Example 2
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
(2.1) performing low-concentration boron diffusion on the front surface of the textured silicon wafer, wherein the diffusion sheet resistance is 170ohm, and the surface concentration is 1.2e19atoms/cm3Forming a lightly doped layer with the junction depth of 0.5 mu m;
(2.2) depositing amorphous silicon on the lightly doped layer by adopting an LPCVD (low pressure chemical vapor deposition) method to form an amorphous silicon layer with the thickness of 140 nm;
(2.3) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(2.4) performing high-concentration boron diffusion in the metal contact area after removing the amorphous silicon, wherein the diffusion sheet resistance is 70ohm, and the surface concentration is 2.5e19 atoms/cm3Forming a heavily doped layer with a junction depth of 0.9 μm;
(2.5) cleaning to remove the amorphous silicon in the non-metal area;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 6 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 80 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the silicon nitride layer is 80 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Example 3
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
(2.1) performing low-concentration boron diffusion on the front surface of the textured silicon wafer, wherein the diffusion sheet resistance is 200ohm, and the surface concentration is 1.0e19atoms/cm3The junction depth is 0.4 μm, and a light doping layer is formed;
(2.2) depositing amorphous silicon on the lightly doped layer by adopting an LPCVD (low pressure chemical vapor deposition) method to form an amorphous silicon layer with the thickness of 200 nm;
(2.3) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(2.4) performing high-concentration boron diffusion in the metal contact area after removing the amorphous silicon, wherein the diffusion sheet resistance is 60ohm, and the surface concentration is 3.0e19 atoms/cm3Forming a heavily doped layer with a junction depth of 1.0 μm;
(2.5) cleaning to remove the amorphous silicon in the non-metal area;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 7 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 80 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the silicon nitride layer is 80 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Example 4
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
(2.1) depositing amorphous silicon on the front surface of the textured silicon wafer by adopting an LPCVD (low pressure chemical vapor deposition) method to form an amorphous silicon layer with the thickness of 80 nm;
(2.2) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(2.3) performing high-concentration boron diffusion in the metal contact area after removing the amorphous silicon, wherein the diffusion sheet resistance is 60ohm, and the surface concentration is 3.0e19 atoms/cm3Forming a heavily doped layer with a junction depth of 1.0 μm;
(2.4) cleaning to remove the amorphous silicon in the non-metal area;
(2.5) performing low-concentration boron diffusion on the front surface of the cleaned silicon wafer, wherein the diffusion sheet resistance is 140ohm, and the surface concentration is 1.2e19atoms/cm3The junction depth is 0.6 μm, and a light doping layer is formed;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 6 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 80 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the silicon nitride layer is 80 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Example 5
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
(2.1) depositing amorphous silicon on the front surface of the textured silicon wafer by adopting an LPCVD (low pressure chemical vapor deposition) method to form an amorphous silicon layer with the thickness of 140 nm;
(2.2) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(2.3) performing high-concentration boron diffusion in the metal contact area after removing the amorphous silicon, wherein the diffusion sheet resistance is 70ohm, and the surface concentration is 2.5e19 atoms/cm3Forming a heavily doped layer with a junction depth of 0.9 μm;
(2.4) cleaning to remove the amorphous silicon in the non-metal area;
(2.5) performing low-concentration boron diffusion on the front surface of the cleaned silicon wafer, wherein the diffusion sheet resistance is 170ohm, and the surface concentration is 1.2e19atoms/cm3Forming a lightly doped layer with the junction depth of 0.5 mu m;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 6 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 80 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the silicon nitride layer is 80 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Example 6
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
(2.1) depositing amorphous silicon on the front surface of the textured silicon wafer by adopting an LPCVD (low pressure chemical vapor deposition) method to form an amorphous silicon layer with the thickness of 200 nm;
(2.2) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(2.3) high concentration boron diffusion is carried out in the metal contact area after removing the amorphous siliconThe sheet resistance was 90ohm, the surface concentration was 2.0e19 atoms/cm3Forming a heavily doped layer with a junction depth of 0.7 μm;
(2.4) cleaning to remove the amorphous silicon in the non-metal area;
(2.5) performing low-concentration boron diffusion on the front surface of the cleaned silicon wafer, wherein the diffusion sheet resistance is 200ohm, and the surface concentration is 1.0e19atoms/cm3The junction depth is 0.4 μm, and a light doping layer is formed;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 10 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 75 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the back silicon nitride layer is 75 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Comparative example 1
A method for preparing an emitter of an N-type crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) performing boron diffusion on the front surface of the textured silicon wafer, wherein the diffusion sheet resistance is 100ohm, and the surface concentration is 1.2e19atoms/cm3Forming a doping layer with the junction depth of 0.8 mu m;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 6 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 70 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the back silicon nitride layer is 70 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Comparative example 2
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
(2.1) performing low-concentration boron diffusion on the front surface of the textured silicon wafer, wherein the diffusion sheet resistance is 140ohm, and the surface concentration is 1.2e19atoms/cm3The junction depth is 0.6 μm, and a light doping layer is formed;
(2.2) depositing silicon oxide on the lightly doped layer by adopting a thermal oxidation method to form a silicon oxide layer with the thickness of 80 nm;
(2.3) carrying out laser grooving on the silicon oxide layer to remove the silicon oxide in the metal contact area;
(2.4) performing high-concentration boron diffusion on the metal contact area after removing the silicon oxide, wherein the diffusion sheet resistance is 60ohm, and the surface concentration is 3.0e19 atoms/cm3Forming a heavily doped layer with a junction depth of 1.0 μm;
(2.5) cleaning to remove the silicon oxide in the non-metal area;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 6 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 70 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the back silicon nitride layer is 70 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Comparative example 3
A method for preparing an N-type selective emitter crystalline silicon battery comprises the following steps:
(1) texturing the surface of the silicon wafer to form a pyramid textured surface;
(2) selective diffusion:
(2.1) depositing silicon oxide on the front surface of the textured silicon wafer by adopting a thermal oxidation method to form a silicon oxide layer with the thickness of 80 nm;
(2.2) carrying out laser grooving on the silicon oxide layer to remove the silicon oxide in the metal contact area;
(2.3) performing high-concentration boron diffusion on the metal contact area after removing the silicon oxide, wherein the diffusion sheet resistance is 60ohm, and the surface concentration is 3.0e19 atoms/cm3Forming a heavily doped layer with a junction depth of 1.0 μm;
(2.4) cleaning to remove the silicon oxide in the non-metal area;
(2.5) performing low-concentration boron diffusion on the front surface of the cleaned silicon wafer, wherein the diffusion sheet resistance is 140ohm, and the surface concentration is 1.2e19atoms/cm3The junction depth is 0.6 μm, and a light doping layer is formed;
(3) etching to remove the borosilicate glass on the back and the edge;
(4) depositing a silicon oxide layer with the thickness of 1.0nm and a phosphorus-doped polycrystalline silicon layer with the thickness of 110nm on the back surface of the silicon wafer by adopting an LPCVD method;
(5) annealing;
(6) removing PSG and RCA cleaning, and removing front surface plating;
(7) depositing alumina on the front surface of the silicon wafer to form an alumina passivation layer with the thickness of 3 nm;
(8) depositing silicon nitride on the aluminum oxide passivation layer to form a front silicon nitride layer with the thickness of 70 nm;
(9) depositing silicon nitride on the back of the silicon wafer, wherein the thickness of the back silicon nitride layer is 70 nm;
(10) and (4) obtaining the N-type selective emitter crystalline silicon battery after screen printing and sintering.
Test example
By adopting a conventional method, the emitters prepared in the examples 1 to 6 and the comparative examples 1 to 3 are prepared into an N-type crystalline silicon battery, and the open-circuit voltage Voc, the short-circuit current Isc and the fill factor FF of the battery are detected, and the results are shown in Table 1.
TABLE 1
Analyzing the data of table 1, the following conclusions can be drawn:
(1) comparative example 1 a common emitter was obtained using primary doping, and examples 1 and 4 a selective emitter was obtained using the method of the present invention. The open circuit voltage, short circuit current, and fill factor of the cells of examples 1 and 4 were increased, and the cell efficiencies were improved by 0.17% and 0.21%, respectively, as compared to comparative example 1. The reason is that: in the selective emitter, the non-metal contact region forms an emitter with low surface concentration and shallow PN junction, so that the recombination probability of minority carriers is reduced, the collection rate of the carriers is improved, the reverse saturation current of the battery is reduced, the open-circuit voltage and the short-circuit current of the battery are improved, the contact resistance with metal paste is reduced, and the filling factor of the battery is improved; the metal contact area forms the emitter of high concentration, dark PN junction, reduces the contact resistance of metal thick liquids contact area, reduces the risk that the thick liquids burn through PN simultaneously, promotes the fill factor of battery.
(2) Examples 1 and 4 used amorphous silicon as a mask, and comparative examples 2 and 3 used silicon oxide as a mask. Compared with the comparative example 2, the open-circuit voltage, the short-circuit current and the filling factor of the battery of the example 1 are increased, so that the battery efficiency is improved by 0.09%; compared with the comparative example 3, the open-circuit voltage, the short-circuit current and the filling factor of the battery of the example 4 are increased, and the efficiency is improved by 0.05%. The reason is that: when silicon oxide is used as a mask, the diffusion speed of boron in the silicon oxide is higher than that of boron in crystalline silicon, so that the surface concentration is uncontrollable, and the performance of a selective emitter is influenced; when the amorphous silicon layer is used as a mask, because the diffusion of boron in the amorphous silicon is slow, the concentration of boron in a formed doped layer can be prevented from being uncontrollable due to the fact that boron penetrates through the amorphous silicon layer, and the performance of the battery is improved.
(3) Example 1 employs the sequence of "forming a lightly doped layer → depositing a mask → laser trenching → forming a heavily doped layer → removing a mask" for selective diffusion, and example 4 employs the sequence of "depositing a mask → laser trenching → forming a heavily doped layer → removing a mask → forming a lightly doped layer". Compared with example 1, the open-circuit voltage and the short-circuit current of the battery of example 4 are increased, and the battery efficiency is improved by 0.17%. The reason is that: by adopting the sequence in the embodiment 4, the method has the advantages of more controllable doping concentration and junction depth of the lightly doped region, can further improve the open-circuit voltage and the short-circuit current, and has better process stability.
The raw materials and equipment used in the invention are common raw materials and equipment in the field if not specified; the methods used in the present invention are conventional in the art unless otherwise specified.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all simple modifications, alterations and equivalents of the above embodiments according to the technical spirit of the present invention are still within the protection scope of the technical solution of the present invention.
Claims (10)
1. A selective diffusion method for preparing an N-type selective emitter crystalline silicon cell is characterized by comprising the following steps:
(1) performing low-concentration boron diffusion on the front surface of the textured silicon wafer to form a light doping layer;
(2) depositing amorphous silicon on the lightly doped layer to form an amorphous silicon layer;
(3) performing laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(4) performing high-concentration boron diffusion on the metal contact area after the amorphous silicon is removed to form a heavily doped layer;
(5) and cleaning to remove the amorphous silicon in the non-metal area.
2. The selective diffusion process of claim 1, wherein in step (1), the diffusion sheet resistance of the low concentration boron diffusion is 140-200 ohm, and the surface concentration is 1.0e19~1.5e19 atoms/cm3The junction depth is 0.3 to 0.6 μm.
3. The selective diffusion method according to claim 1 or 2, wherein in the step (4), the diffusion sheet resistance of the high concentration boron diffusion is 60 to 100ohm, and the surface concentration is 2.0e19~3.0e19 atoms/cm3The junction depth is 0.6 to 1.0 μm.
4. The selective diffusion method according to claim 1, wherein in the step (2), the thickness of the amorphous silicon layer is 80 to 200 nm.
5. A selective diffusion method for preparing an N-type selective emitter crystalline silicon cell is characterized by comprising the following steps:
(I) depositing amorphous silicon on the front surface of the textured silicon wafer to form an amorphous silicon layer;
(II) carrying out laser grooving on the amorphous silicon layer to remove the amorphous silicon in the metal contact area;
(III) carrying out high-concentration boron diffusion on the metal contact area after the amorphous silicon is removed to form a heavily doped layer;
(IV) cleaning to remove the amorphous silicon in the non-metal area;
and (V) performing low-concentration boron diffusion on the front surface of the cleaned silicon wafer to form a light doping layer.
6. The selective diffusion method of claim 5, wherein in step (I), the amorphous silicon layer has a thickness of 80 to 200 nm.
7. Selectivity as claimed in claim 5The diffusion method is characterized in that in the step (III), the diffusion sheet resistance of the high-concentration boron diffusion is 60-100 ohm, and the surface concentration is 2.0e19~3.0e19 atoms/cm3The junction depth is 0.6 to 1.0 μm.
8. The selective diffusion process of claim 5 or 7, wherein in step (V), the diffusion sheet resistance of the low concentration boron diffusion is 140-200 ohm, and the surface concentration is 1.0e19~1.5e19 atoms/cm3The junction depth is 0.3 to 0.6 μm.
9. A method for manufacturing an N-type selective emitter crystalline silicon battery by using the selective diffusion method as claimed in any one of claims 1 to 8, comprising the following steps: after the selective diffusion is completed by adopting the selective diffusion method, removing borosilicate glass on the back and the edge by etching, depositing a silicon oxide layer and a phosphorus-doped polycrystalline silicon layer on the back, annealing and removing winding plating, sequentially depositing an aluminum oxide passivation layer and a front silicon nitride layer on the front of a silicon wafer, depositing a back silicon nitride layer on the back of the silicon wafer, and printing and sintering by a screen to obtain the N-type selective emitter crystalline silicon battery.
10. The method of claim 9, wherein the aluminum oxide passivation layer has a thickness of 3 to 10nm, the front silicon nitride layer has a thickness of 70 to 90nm, and the back silicon nitride layer has a thickness of 70 to 90 nm.
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