CN111370539A - A kind of preparation method of solar cell with selective emitter - Google Patents

Abstract

The invention relates to a method for preparing a solar cell with a selective emitter, comprising: (1) growing a mask layer on one side of a silicon substrate as the front side of the silicon substrate; (2) locally printing and etching on the mask layer (3) Diffusion treatment of boron on the silicon substrate to form a heavily doped area in the area without the mask layer, and form a lightly doped area in the area with the mask layer, so as to form the front boron Selective emitter (4), etching the textured surface on the backside of the silicon substrate into a flat surface, and removing the borosilicate glass layer on the front side at the same time; (5), growing a tunnel oxide layer and doped amorphous silicon on the backside of the silicon substrate (6) deposit a back passivation film on the back of the silicon substrate, and deposit a front passivation anti-reflection film on the front of the silicon substrate; (7) print a front busbar on the front of the silicon substrate and front sub-grid, the back busbar and back sub-grid are printed on the back of the silicon substrate, and dried.

Description

A kind of preparation method of solar cell with selective emitter

technical field

The invention relates to the technical field of solar cells, in particular to a preparation method of a solar cell with a selective emitter.

Background technique

Solar cells are basic devices that convert solar energy into electrical energy. With the continuous progress of solar cells, high efficiency and cost reduction have become an important direction for the current industrialization of solar cells. High-efficiency structural design and improvement of manufacturing yield are the keys to achieve this goal. Among them, the selective emitter structure has been widely studied and used due to its unique technical advantages. Selective emitter technology is to perform heavy doping under the electrode of the battery and shallow doping in the non-metallic contact emitter region. This technology can not only reduce the rate of minority carrier recombination in the diffusion layer, but also improve the short-wave response and open-circuit voltage of the battery. , it can also reduce the series resistance of the battery, improve the short-circuit current and fill factor of the battery, and thus improve the conversion efficiency.

The common preparation method of boron-doped selective emitter is the double diffusion method. This method is to deposit a boron source at a high temperature, then dope it with a laser, and then perform high-temperature oxidation after cleaning to form a selective emitter. The substrate will enter the high-temperature boron expansion furnace twice, causing high-temperature damage to the silicon substrate. In addition, laser doping will also introduce laser damage. In addition, the preparation method of boron-doped selective emitter also includes wet chemical etching method. This method is to first prepare deep junction boron diffusion, and then prepare a patterned mask on the boron expanded surface, and use etching slurry after the mask. The area without mask is etched into a lightly doped area to form a selective emitter. This method uses chemical etching slurry to directly etch the boron expansion area, which will destroy the pyramid structure on the surface and increase the reflectivity. cause current loss.

In view of this, it is very necessary to provide a method for preparing a solar cell with a selective emitter with simple process, short time-consuming and low cost.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies of the prior art, and to provide a method for preparing a solar cell with a simple process, short time-consuming and low cost, and capable of precisely having a selective emitter.

A preparation method of a solar cell with a selective emitter of the present invention, the technical scheme is as follows: comprising the following steps:

(1), a mask layer is grown on any side of the silicon substrate after the double-sided texturing treatment, and one side of the growth mask layer is used as the front side of the silicon substrate;

(2), partially print the etching slurry layer on the mask layer on the front side of the silicon substrate, and dry it; during the drying process, the etching slurry layer reacts with the mask layer, so that the printing etching The mask layer in the area of the etching paste layer is etched away, and the mask layer in the area where the etching paste layer is not printed is retained; wherein, the etching paste layer only reacts with the mask layer;

(3), perform boron diffusion treatment on the silicon substrate to form a heavily doped region in the region without the mask layer, and form a lightly doped region in the region containing the mask layer, thereby forming a front boron selective emitter; During the diffusion process, the lightly doped region and the heavily doped region will be covered with a borosilicate glass layer to form a front borosilicate glass layer, and at the same time some doping sources are extended to the back edge region to form a back borosilicate glass layer;

(4), etching the textured surface on the back of the silicon substrate into a plane, while removing the front borosilicate glass layer;

(5), growing a tunnel oxide layer and a doped amorphous silicon layer on the back of the silicon substrate, and performing annealing treatment to activate the doping atoms on the back of the silicon substrate, complete crystallization, and form a doped polysilicon layer;

(6), deposit the back passivation film on the back of the silicon substrate, and deposit the front passivation anti-reflection film on the front of the silicon substrate;

(7) printing the front busbar and the front subgrid on the front of the silicon substrate, printing the back busbar and the back subgrid on the backside of the silicon substrate, and performing drying treatment.

A preparation method of a solar cell with a selective emitter provided by the present invention also includes the following subsidiary technical solutions:

Wherein, in step (2), the printing pattern of the partially printed etching paste layer is the same as the pattern of the front sub-grid.

Wherein, before step (3), the method also includes:

(3)', cleaning the silicon substrate processed in step (2) to remove the etching slurry layer and the mask layer below the etching slurry layer.

Wherein, in step (2), the mask layer is a SiO ₂ dielectric film or a SiN _X dielectric film, or a laminated film formed by SiO ₂ and SiN _X , the thickness of which is 20-100 nm, and the preparation method is PECVD or ALD .

Wherein, in step (3), the boron source for boron diffusion is boron tribromide, the diffusion temperature is 900-1070°C, the diffusion time is 90-240min, and the square resistance value after diffusion is 50-200Ω/sqr.

Wherein, in step (3)', the silicon substrate processed in step (2) is cleaned with clean water to remove the etching slurry layer and the mask layer below the etching slurry layer, and the temperature of the clean water is 40- 80°C.

Wherein, in step (5); the tunnel oxide layer is made of silicon dioxide, and its thickness is 0.5-2 nm, and the preparation method is nitric acid oxidation method, high temperature thermal oxidation method, ozone oxidation method or atomic layer deposition method;

Wherein, when the preparation method is a high temperature thermal oxidation method, the reaction is carried out for 10 to 20 minutes under the conditions of normal pressure, pure oxygen, and a temperature of 500 to 700 °C;

When the preparation method is a nitric acid oxidation method, a nitric acid solution with a mass fraction of 60-68% is used, and the reaction is carried out at a reaction temperature of 80-100° C. for 4-10 minutes.

Wherein, in step (5), the method of growing the doped amorphous silicon layer on the back surface of the silicon substrate is a magnetron sputtering method, placing the silicon substrate in an argon atmosphere, adjusting the reaction pressure to 0.1-0.7Pa, and reacting The temperature is 100～300℃, and the reaction is performed for 10min～3h.

Wherein, the front passivation anti-reflection film is one or any combination of SiO ₂ , SiN _X or Al ₂ O ₃ dielectric films, and the back passivation anti-reflection film is one of SiO ₂ , SiN _X dielectric films one or any combination.

Wherein, in step (7), the front main grid and the front sub grid are printed with aluminum-doped silver paste, and the back main grid and the rear sub grid are printed with silver paste; wherein, the back sub grid line width is 35-90um, which are arranged parallel to each other ; The width of the front auxiliary grid is 30~90um, and they are arranged parallel to each other.

The implementation of the present invention includes the following technical effects:

The invention adopts one-time boron diffusion to form the selective emitter, avoids the method of forming the selective emitter by the double diffusion method, and the high-temperature damage to the silicon substrate caused by the two high-temperature diffusions, improves the minority carrier lifetime of the silicon substrate, and simplifies the process at the same time. Reduced processes and increased productivity. In addition, the present invention uses the selective etching slurry to etch the mask, avoids the direct etching of the emitter by the commonly used chemical etching method, and the direct damage to the textured surface of the silicon base pyramid when the selective emitter is formed, which can effectively The increase in reflectivity caused by the damage of the pyramid texture is avoided, thereby increasing the current of the solar cell and improving the efficiency, and at the same time avoiding the disadvantage that the etching rate of chemical etching is not easy to control.

Description of drawings

Fig. 1 is a schematic cross-sectional view of the cell structure after step (1)' of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

2 is a schematic cross-sectional view of the cell structure after step (1) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

3 is a schematic cross-sectional view of the cell structure after step (2) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of the cell structure after step (3)' of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

5 is a schematic cross-sectional view of the cell structure after step (3) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

6 is a schematic cross-sectional view of the cell structure after step (4) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

7 is a schematic cross-sectional view of the cell structure after the ultra-thin tunnel oxide layer is prepared in step (5) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

8 is a schematic cross-sectional view of the cell structure after the doped amorphous silicon layer is prepared in step (5) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

9 is a schematic cross-sectional view of the cell structure after annealing in step (5) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

10 is a schematic cross-sectional view of the cell structure after step (6) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

11 is a schematic cross-sectional view of the cell structure after step (7) of a method for preparing a solar cell with a selective emitter according to an embodiment of the present invention.

In the figure, 1-N-type crystalline silicon substrate, 2-mask layer, 3-etching paste layer, 41-lightly doped region, 42-heavy doped region, 5-BSG borosilicate glass layer, 6-super Thin tunneling oxide layer, 7-doped amorphous silicon layer, 8-doped polysilicon layer, 9-back passivation film, 10-front passivation anti-reflection film, 11-front sub-gate, 12-back sub grid.

Detailed ways

The present invention will be described in detail below with reference to examples.

The specific embodiment is only an explanation of the present invention, not a limitation of the present invention. Those skilled in the art can make modifications without creative contribution to the present embodiment as required after reading this specification, but only within the scope of the claims of the present invention are protected inside.

A preparation method of a solar cell with a selective emitter of the present invention,

Include the following steps:

(1), a mask layer is grown on any side of the silicon substrate after the double-sided texturing treatment, and one side of the growth mask layer is used as the front side of the silicon substrate;

(2), partially print the etching slurry layer on the mask layer on the front side of the silicon substrate, and dry it; during the drying process, the etching slurry layer reacts with the mask layer, so that the printing etching The mask layer in the area of the etching paste layer is etched away, and the mask layer in the area where the etching paste layer is not printed is retained; wherein, the etching paste layer only reacts with the mask layer;

(3), perform boron diffusion treatment on the silicon substrate to form a heavily doped region in the region without the mask layer, and form a lightly doped region in the region containing the mask layer, thereby forming a front boron selective emitter; During the diffusion process, the lightly doped region and the heavily doped region will be covered with a borosilicate glass layer to form a front borosilicate glass layer, and at the same time some doping sources are extended to the back edge region to form a back borosilicate glass layer;

(4), etching the textured surface on the back of the silicon substrate into a plane, while removing the front borosilicate glass layer;

(5), growing a tunnel oxide layer and a doped amorphous silicon layer on the back of the silicon substrate, and performing annealing treatment to activate the doping atoms on the back of the silicon substrate, complete crystallization, and form a doped polysilicon layer;

(6), deposit the back passivation film on the back of the silicon substrate, and deposit the front passivation anti-reflection film on the front of the silicon substrate;

(7) printing the front busbar and the front subgrid on the front of the silicon substrate, printing the back busbar and the back subgrid on the backside of the silicon substrate, and performing drying treatment.

In one embodiment, in step (1), the resistivity of the N-type crystalline silicon substrate is 1˜5 Ω·cm, and the thickness is 80˜200 μm.

In one embodiment, in step (2), the printing pattern of the partially printed etching paste layer is the same as the front sub-grid pattern.

Preferably, before step (3), the method further comprises:

(3)', cleaning the silicon substrate processed in step (2) to remove the etching slurry layer and the mask layer below the etching slurry layer.

In one embodiment, in step (2), the mask layer is a SiO ₂ dielectric film or a SiN _X dielectric film, or a laminated film formed by SiO ₂ and SiN _X , the thickness of which is 20-100 nm. Preparation method For PECVD or ALD.

In one embodiment, in step (3), the boron source for boron diffusion is boron tribromide, the diffusion temperature is 900-1070°C, the diffusion time is 90-240min, and the square resistance after diffusion is 50-200Ω/ sqr.

In one embodiment, in step (3)', clean water is used to clean the silicon substrate processed in step (2) to remove the etching slurry layer and the mask layer under the etching slurry layer. The temperature is 40-80°C.

In one embodiment, in step (5), the high temperature annealing temperature is 800-1000° C., and the time is 20-120 min.

In one embodiment, in step (5); the tunnel oxide layer is made of silicon dioxide, the thickness is 0.5-2 nm, and the preparation method is nitric acid oxidation, high temperature thermal oxidation, ozone oxidation or atomic layer deposition method;

Wherein, when the preparation method is a high temperature thermal oxidation method, the reaction is carried out for 10 to 20 minutes under the conditions of normal pressure, pure oxygen, and a temperature of 500 to 700 °C;

When the preparation method is a nitric acid oxidation method, a nitric acid solution with a mass fraction of 60-68% is used, and the reaction is carried out at a reaction temperature of 80-100° C. for 4-10 minutes.

In one embodiment, in step (5), the method of growing the doped amorphous silicon layer on the back surface of the silicon substrate is a magnetron sputtering method, the silicon substrate is placed in an argon atmosphere, and the reaction pressure is adjusted to 0.1～ 0.7Pa, the reaction temperature is 100～300℃, and the reaction is carried out for 10min～3h.

In one embodiment, the front passivation anti-reflection film is one or a combination of any of SiO ₂ , SiN _X or Al ₂ O ₃ dielectric films, and the back passivation anti-reflection film is SiO ₂ , SiN _X One or any combination of dielectric films.

In one embodiment, in step (7), the front busbar and the front subgrid are printed with aluminum-doped silver paste, and the rear busbar and the rear subgrid are printed with silver paste; It is 35~90um, and it is set parallel to each other; the width of the front auxiliary grid is 30~90um, and it is set parallel to each other.

Optionally, before step (1), the method further includes:

Step (1)', selecting an N-type crystalline silicon substrate, and performing texturing on both sides of the N-type crystalline silicon substrate.

The invention adopts one-time boron diffusion to form the selective emitter, avoids the method of forming the selective emitter by the double diffusion method, and the high-temperature damage to the silicon substrate caused by the two high-temperature diffusions, improves the minority carrier lifetime of the silicon substrate, and simplifies the process at the same time. Reduced processes and increased productivity. In addition, the present invention uses the selective etching slurry to etch the mask, avoids the direct etching of the emitter by the commonly used chemical etching method, and the direct damage to the textured surface of the silicon base pyramid when the selective emitter is formed, which can effectively The increase in reflectivity caused by the damage of the pyramid texture is avoided, thereby increasing the current of the solar cell and improving the efficiency, and at the same time avoiding the disadvantage that the etching rate of chemical etching is not easy to control.

The preparation method of the invention will be described in detail below with specific examples.

Example 1

Step (1)', selecting an N-type crystalline silicon substrate 1, and performing double-sided texturing treatment on the N-type crystalline silicon substrate 1; wherein, the resistivity of the N-type crystalline silicon substrate 1 is 5 Ω·cm; 1 has a thickness of 170 μm. The battery structure after this step is completed is shown in FIG. 1 .

In step (1), select any surface of the N-type crystalline silicon substrate 1 processed in step (1)', and grow a mask layer 2 by PECVD. Wherein, the fabrication material of the mask layer 2 is SiO ₂ , and the thickness is 20 nm. The battery structure after this step is completed is shown in FIG. 2 .

In step (2), a patterned etching slurry layer 3 is locally printed on the mask layer 2 of the N-type crystalline silicon substrate 1 processed in step (1). The printing pattern is the same as the fine gate of the metallized pattern. The etching paste only reacts with the mask and does not cause damage to the pyramid texture. The battery structure after this step is completed is shown in FIG. 3 .

Step (3)', put the N-type crystalline silicon substrate processed in step (2) into hot water at 50° C. to clean the slurry, clean the printed etching slurry layer 3, and at the same time the mask under the slurry is removed. Film 2 is etched away. The battery structure after this step is completed is shown in FIG. 4 .

In step (3), the N-type crystalline silicon substrate processed in step (3)' is put into a boron diffusion furnace for diffusion, and the diffusion method is single-sided diffusion. The regions form heavily doped regions 42 . Among them, the source of boron diffusion is boron tribromide, the diffusion temperature is 1020°C, the diffusion time is 240min, the square resistance of the lightly doped area is 200Ω/sqr, and the square resistance of the heavily doped area is 50Ω/sqr. In addition, the lightly doped region and the heavily doped region are covered with a BSG borosilicate glass layer 5 , and part of the doping source is extended to the back surface to form the BSG borosilicate glass layer 5 . The battery structure after this step is completed is shown in FIG. 5 .

In step (4), the backside of the N-type crystalline silicon substrate treated in step (3) is etched to form a flat surface morphology on the backside, and the BSG borosilicate glass layer 5 and the mask layer 2 on the front side are removed at the same time . The battery structure after this step is completed is shown in FIG. 6 .

In step (5), an ultra-thin tunneling oxide layer 6 is grown on the back surface of the N-type crystalline silicon substrate processed in step (4). The composition of the ultra-thin tunneling oxide layer is silicon dioxide. The preparation method is thermal oxidation, and the thickness of the silicon dioxide layer is 2 nm; the battery structure after this step is completed is shown in FIG. 7 . Then, a layer of doped amorphous silicon layer 7 is deposited on the outside of the ultra-thin tunnel oxide layer 6 by PVD. Specifically, the silicon substrate is placed in an argon atmosphere, the reaction pressure is adjusted to 0.1Pa, and the reaction time is 50 min, the reaction temperature is 300 °C, and the battery structure after this step is completed is shown in FIG. 8 . Finally, the N-type crystalline silicon substrate 1 is annealed to activate the dopant atoms on the backside to complete crystallization to form a doped polysilicon layer 8. The annealing temperature is 800°C and the annealing time is 40min. The battery structure after this step is as follows: shown in Figure 9.

(6), deposit a layer of silicon nitride passivation film 9 on the back of the N-type crystalline silicon substrate 1 processed in step (5), with a film thickness of 120 nm, and deposit a layer of aluminum oxide and silicon nitride on the front side of the stack. membrane 10. The battery structure after this step is completed is shown in FIG. 10 .

(7), the N-type crystalline silicon substrate 1 processed in step (6), first use silver paste to print the back main grid and the back sub grid on the back surface and dry, wherein the back sub grid 12 has a line width of 45um and is parallel to each other . The front busbar and the front subgrid 11 are printed on the front surface of the N-type crystalline silicon substrate 1 using Al-doped silver paste, wherein the front subgrid 11 has a line width of 45um and is parallel to each other; the battery structure after this step is shown in FIG. 11 . Then, the N-type crystalline silicon substrate 1 is transferred into a belt sintering furnace for sintering, and the sintering peak temperature is 800° C., thus completing the preparation of a solar cell with a boron-doped selective emitter.

Example 2

Step (1)', selecting an N-type crystalline silicon substrate 1, and performing double-sided texturing treatment on the N-type crystalline silicon substrate 1; wherein, the resistivity of the N-type crystalline silicon substrate 1 is 1Ω·cm; the N-type crystalline silicon substrate 1 1 has a thickness of 100 μm. The battery structure after this step is completed is shown in FIG. 1 .

In step (1), select any surface of the N-type crystalline silicon substrate 1 processed in step (1)', and grow a mask layer 2 by PECVD. Wherein, the fabrication material of the mask layer 2 is SiN _X , and the thickness is 50 nm. The battery structure after this step is completed is shown in FIG. 2 .

In step (2), a patterned etching slurry layer 3 is locally printed on the mask layer 2 of the N-type crystalline silicon substrate 1 processed in step (1). The printing pattern is the same as the fine gate of the metallized pattern. The etching paste only reacts with the mask and does not cause damage to the pyramid texture. The battery structure after this step is completed is shown in FIG. 3 .

Step (3)', put the N-type crystalline silicon substrate processed in step (2) into hot water at 40° C. to clean the slurry, clean the printed etching slurry layer 3, and at the same time, the mask under the slurry is removed. Film 2 is etched away. The battery structure after this step is completed is shown in FIG. 4 .

In step (3), the N-type crystalline silicon substrate processed in step (3)' is put into a boron diffusion furnace for diffusion, and the diffusion method is single-sided diffusion. The regions form heavily doped regions 42 . Among them, the source of boron diffusion is boron tribromide, the diffusion temperature is 900°C, the diffusion time is 90min, the square resistance of the lightly doped area is 50Ω/sqr, and the square resistance of the heavily doped area is 50Ω/sqr. During the boron diffusion process, the lightly doped region and the heavily doped region are covered with a BSG borosilicate glass layer 5 , and part of the doping source is extended to the backside to form the BSG borosilicate glass layer 5 . The battery structure after this step is completed is shown in FIG. 5 .

In step (4), the backside of the N-type crystalline silicon substrate treated in step (3) is etched to form a flat surface morphology on the backside, and the BSG borosilicate glass layer 5 and the mask layer 2 on the front side are removed at the same time . The battery structure after this step is completed is shown in FIG. 6 .

In step (5), an ultra-thin tunneling oxide layer 6 is grown on the back surface of the N-type crystalline silicon substrate processed in step (4). The composition of the ultra-thin tunneling oxide layer is silicon dioxide. The preparation method is a high-temperature thermal oxidation method. Specifically, the N-type crystalline silicon substrate treated in step (6) is placed under the conditions of normal pressure, pure oxygen, and a temperature of 500° C., and reacted for 10 minutes to form a silicon dioxide layer with a thickness of 3 nm; The battery structure after this step is completed is shown in FIG. 7 . Then, a layer of doped amorphous silicon layer 7 is deposited on the outside of the ultra-thin tunnel oxide layer 6 by magnetron sputtering. Specifically, the silicon substrate was placed in an argon atmosphere, the reaction pressure was adjusted to 0.4 Pa, the reaction time was 50 min, and the reaction temperature was 100° C. The battery structure after this step was completed is shown in FIG. 8 . Finally, the N-type crystalline silicon substrate 1 is annealed to activate the doping atoms on the backside to complete crystallization to form a doped polysilicon layer 8. The annealing temperature is 1000° C. and the annealing time is 20 minutes. The battery structure after this step is as follows shown in Figure 9.

(6), deposit a layer of composite film of silicon nitride and silicon dioxide on the back of the N-type crystalline silicon substrate 1 processed in step (5) as a passivation film 9 with a film thickness of 120 nm, and deposit a layer of oxide on its front Laminated film 10 of aluminum and silicon dioxide. The battery structure after this step is completed is shown in FIG. 10 .

(7), the N-type crystalline silicon substrate 1 processed in step (6), first use silver paste on the back surface to print the back main grid and the back sub grid and dry, wherein the back sub grid 12 has a line width of 90um and is parallel to each other . The front busbar and the front subgrid 11 are printed on the front surface of the N-type crystalline silicon substrate 1 using Al-doped silver paste, wherein the front subgrid 11 has a line width of 90um and is parallel to each other; the battery structure after this step is shown in FIG. 11 . Then, the N-type crystalline silicon substrate 1 is transferred into a belt sintering furnace for sintering, and the sintering peak temperature is 800° C., thus completing the preparation of a solar cell with a boron-doped selective emitter.

Example 3

Step (1)', selecting an N-type crystalline silicon substrate 1, and performing double-sided texturing treatment on the N-type crystalline silicon substrate 1; wherein, the resistivity of the N-type crystalline silicon substrate 1 is 3 Ω·cm; the N-type crystalline silicon substrate 1 1 has a thickness of 170 μm. The battery structure after this step is completed is shown in FIG. 1 .

In step (1), select any surface of the N-type crystalline silicon substrate 1 processed in step (1)', and grow a mask layer 2 by PECVD. Wherein, the fabrication material of the mask layer 2 is a laminated film formed of SiO ₂ and SiN _X , and the thickness is 100 nm. The battery structure after this step is completed is shown in FIG. 2 .

In step (2), a patterned etching slurry layer 3 is locally printed on the mask layer 2 of the N-type crystalline silicon substrate 1 processed in step (1). The printing pattern is the same as the fine gate of the metallized pattern. The etching paste only reacts with the mask and does not cause damage to the pyramid texture. The battery structure after this step is completed is shown in FIG. 3 .

Step (3)', put the N-type crystalline silicon substrate processed in step (2) into hot water at 80° C. to clean the slurry, clean the printed etching slurry layer 3, and at the same time the mask under the slurry is removed. Film 2 is etched away. The battery structure after this step is completed is shown in FIG. 4 .

In step (3), the N-type crystalline silicon substrate processed in step (3)' is put into a boron diffusion furnace for diffusion, and the diffusion method is single-sided diffusion. The regions form heavily doped regions 42 . Among them, the source of boron diffusion is boron tribromide, the diffusion temperature is 1070°C, the diffusion time is 220min, the square resistance of the lightly doped area is 100Ω/sqr, and the square resistance of the heavily doped area is 70Ω/sqr. In addition, the lightly doped region and the heavily doped region are covered with a BSG borosilicate glass layer 5 , and part of the doping source is extended to the back surface to form the BSG borosilicate glass layer 5 . The battery structure after this step is completed is shown in FIG. 5 .

In step (4), the backside of the N-type crystalline silicon substrate treated in step (3) is etched to form a flat surface morphology on the backside, and the BSG borosilicate glass layer 5 and the mask layer 2 on the front side are removed at the same time . The battery structure after this step is completed is shown in FIG. 6 .

In step (5), an ultra-thin tunneling oxide layer 6 is grown on the back surface of the N-type crystalline silicon substrate processed in step (4). The composition of the ultra-thin tunneling oxide layer is silicon dioxide. The preparation method is a nitric acid oxidation method. Specifically, the N-type crystalline silicon substrate treated in step (6) is placed in a nitric acid solution with a mass fraction of 60 to 68%, and at a reaction temperature of 80 to 100 ° C. A silicon dioxide layer with a thickness of 2 nm is formed in 10 minutes; the battery structure after this step is completed is shown in FIG. 7 . Then, a layer of doped amorphous silicon layer 7 is deposited on the outside of the ultra-thin tunnel oxide layer 6 by PVD. The silicon substrate is placed in an argon atmosphere, the reaction pressure is adjusted to 0.7Pa, and the reaction time is 50min, the reaction temperature is 300°C, and the battery structure after this step is completed is shown in FIG. 8 . Finally, the N-type crystalline silicon substrate 1 is annealed to activate the dopant atoms on the backside to complete crystallization to form a doped polysilicon layer 8. The annealing temperature is 900° C. and the annealing time is 60 minutes. The battery structure after this step is as follows: shown in Figure 9.

(6), deposit a passivation film 9 of silicon dioxide on the back of the N-type crystalline silicon substrate 1 processed in step (5), with a film thickness of 100 nm, and deposit a layer of silicon dioxide and silicon nitride on its front side. Laminated film 10 . The battery structure after this step is completed is shown in FIG. 10 .

(7), the N-type crystalline silicon substrate 1 processed in step (6), first use silver paste on the back surface to print the back main grid and the back sub grid and dry, wherein the back sub grid 12 has a line width of 90um and is parallel to each other . The front busbar and the front subgrid 11 are printed on the front surface of the N-type crystalline silicon substrate 1 using Al-doped silver paste, wherein the front subgrid 11 has a line width of 90um and is parallel to each other; the battery structure after this step is shown in FIG. 11 . Then, the N-type crystalline silicon substrate 1 is transferred into a belt sintering furnace for sintering, and the sintering peak temperature is 800° C., thus completing the preparation of a solar cell with a boron-doped selective emitter.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit the protection scope of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that , the technical solutions of the present invention may be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims (10)

1. A method for preparing a solar cell with a selective emitter is characterized in that: the method comprises the following steps:

(1) growing a mask layer on any side of the silicon substrate subjected to the double-side texturing treatment, wherein one side of the grown mask layer is used as the front side of the silicon substrate;

(2) locally printing an etching slurry layer on the mask layer on the front surface of the silicon substrate, and drying to etch the mask layer in the area of the printing etching slurry layer and retain the mask layer in the area of the etching slurry layer which is not printed;

(3) carrying out boron diffusion treatment on the silicon substrate to form a heavily doped region in a region without the mask layer, and forming a lightly doped region in a region containing the mask layer so as to form a front boron selective emitter; in the boron diffusion process, the light doping area and the heavy doping area are covered with borosilicate glass layers to form a front borosilicate glass layer, and meanwhile, part of doping sources extend to the edge area of the back to form a back borosilicate glass layer;

(4) etching the texturing surface on the back surface of the silicon substrate into a plane, and simultaneously removing the borosilicate glass layer on the front surface;

(5) growing a tunneling oxide layer and a doped amorphous silicon layer on the back surface of the silicon substrate, and carrying out annealing treatment to activate doped atoms on the back surface of the silicon substrate to complete crystallization and form a doped polycrystalline silicon layer;

(6) depositing a back passivation film on the back of the silicon substrate, and depositing a front passivation antireflection film on the front of the silicon substrate;

(7) and printing a front main grid and a front auxiliary grid on the front surface of the silicon substrate, printing a back main grid and a back auxiliary grid on the back surface of the silicon substrate, and drying.

2. The production method according to claim 1, wherein in the step (2), the locally printed pattern of the etching paste layer is the same as the front side sub-gate pattern.

3. The method of claim 1 or 2, wherein prior to step (3), the method further comprises:

(3) and', cleaning the silicon substrate processed in the step (2) to remove the etching slurry layer and the mask layer below the etching slurry layer.

4. The production method according to claim 1 or 2, wherein in the step (2), the mask layer is SiO₂Dielectric film or SiN_XDielectric film, or SiO₂And SiN_XThe formed laminated film has a thickness of 20-100nm and is prepared by PECVD or ALD.

5. The production method according to claim 1 or 2, wherein in the step (3), a boron source for boron diffusion is boron tribromide, the diffusion temperature is 900 to 1070 ℃, the diffusion time is 90 to 240min, and the diffused square resistance is 50 to 200 Ω/sqr.

6. The method according to claim 3, wherein in the step (3)', the silicon substrate processed in the step (2) is cleaned with clear water to remove the etching slurry layer and the mask layer under the etching slurry layer, and the temperature of the clear water is 40-80 ℃.

7. The production method according to claim 1 or 2, wherein, in step (5); the tunneling oxide layer is made of silicon dioxide, the thickness of the tunneling oxide layer is 0.5-2 nm, and the preparation method is a nitric acid oxidation method, a high-temperature thermal oxidation method, an ozone oxidation method or an atomic layer deposition method;

wherein, when the preparation method is a high-temperature thermal oxidation method, the reaction is carried out for 10-20 min under the conditions of normal pressure, pure oxygen and the temperature of 500-700 ℃;

when the preparation method is a nitric acid oxidation method, a nitric acid solution with the mass fraction of 60-68% is adopted to react for 4-10 min at the reaction temperature of 80-100 ℃.

8. The method of claim 7, wherein in the step (5), the doped amorphous silicon layer is grown on the back surface of the silicon substrate by magnetron sputtering, the silicon substrate is placed in an argon atmosphere, the reaction pressure is adjusted to 0.1 to 0.7Pa, the reaction temperature is adjusted to 100 to 300 ℃, and the reaction time is 10min to 3 h.

9. The production method according to claim 1 or 2, wherein the front passivation anti-reflective film is SiO₂、SiN_XOr Al₂O₃One or a combination of any several of the dielectric films, and the back passivation antireflection film is SiO₂、SiN_XOne or a combination of any several of the dielectric films.

10. The preparation method according to claim 1 or 2, characterized in that, in the step (7), the front main grid and the front auxiliary grid are printed by adopting aluminum-doped silver paste, and the back main grid and the back auxiliary grid are printed by adopting silver paste; wherein, the line width of the back side auxiliary grid is 35-90 um and the back side auxiliary grid are arranged in parallel; the line width of the front side auxiliary grid is 30-90 um and the front side auxiliary grid are arranged in parallel.

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