CN111370539A - Preparation method of solar cell with selective emitter - Google Patents
Preparation method of solar cell with selective emitter Download PDFInfo
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- CN111370539A CN111370539A CN202010196429.8A CN202010196429A CN111370539A CN 111370539 A CN111370539 A CN 111370539A CN 202010196429 A CN202010196429 A CN 202010196429A CN 111370539 A CN111370539 A CN 111370539A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 119
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 86
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 86
- 239000010703 silicon Substances 0.000 claims abstract description 86
- 238000005530 etching Methods 0.000 claims abstract description 55
- 238000009792 diffusion process Methods 0.000 claims abstract description 48
- 239000002002 slurry Substances 0.000 claims abstract description 46
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052796 boron Inorganic materials 0.000 claims abstract description 30
- 239000005388 borosilicate glass Substances 0.000 claims abstract description 23
- 230000005641 tunneling Effects 0.000 claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000001035 drying Methods 0.000 claims abstract description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 63
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 52
- 239000000377 silicon dioxide Substances 0.000 claims description 30
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 19
- 238000007254 oxidation reaction Methods 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 16
- 229910004205 SiNX Inorganic materials 0.000 claims description 14
- 229910052681 coesite Inorganic materials 0.000 claims description 14
- 229910052906 cristobalite Inorganic materials 0.000 claims description 14
- 229910052682 stishovite Inorganic materials 0.000 claims description 14
- 229910052905 tridymite Inorganic materials 0.000 claims description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 12
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 11
- 229910017604 nitric acid Inorganic materials 0.000 claims description 11
- 238000004140 cleaning Methods 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 9
- 239000012300 argon atmosphere Substances 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 238000002425 crystallisation Methods 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 6
- 230000035484 reaction time Effects 0.000 claims description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 33
- 239000013078 crystal Substances 0.000 description 21
- 238000005245 sintering Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000003213 activating effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022433—Particular geometry of the grid contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention relates to a preparation method of a solar cell with a selective emitter, which comprises the following steps: (1) growing a mask layer on one surface of the silicon substrate to be used as the front surface of the silicon substrate; (2) locally printing an etching slurry layer on the mask layer, and drying; (3) carrying out boron diffusion treatment on the silicon substrate to form a heavily doped region in a region without the mask layer and a lightly doped region in a region containing the mask layer, so as to form a front boron selective emitter (4), etching the texturing surface on the back of the silicon substrate into a plane, and removing the front borosilicate glass layer; (5) growing a tunneling oxide layer and a doped amorphous silicon layer on the back surface of the silicon substrate, and carrying out annealing treatment to form a doped polycrystalline silicon layer; (6) depositing a back passivation film on the back of the silicon substrate, and depositing a front passivation antireflection film on the front of the silicon substrate; (7) and printing a front main grid and a front auxiliary grid on the front surface of the silicon substrate, printing a back main grid and a back auxiliary grid on the back surface of the silicon substrate, and drying.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a solar cell with a selective emitter.
Background
Solar cells are the fundamental devices for converting solar energy into electrical energy. With the continuous progress of solar cells, high efficiency and cost reduction become important directions for the current industrialization development of solar cells, and the key for realizing the goal is high-efficiency structural design and improving the manufacturing yield. Wherein selective emitter structures are widely studied and used due to their unique technical advantages. The selective emitter technology is characterized in that heavy doping is carried out below an electrode of a battery, and shallow doping is carried out in an emitter region in non-metal contact.
The common preparation method of the boron-doped selective emitter is a two-time diffusion method, the method comprises the steps of depositing a boron source at a high temperature, doping by using laser, cleaning and then carrying out high-temperature oxidation, so that the selective emitter is formed, a silicon substrate enters a high-temperature boron diffusion furnace tube twice to cause high-temperature damage to the silicon substrate, and laser doping can also cause laser damage. In addition, the preparation method of the boron-doped selective emitter also comprises a wet chemical etching method, the method comprises the steps of preparing deep junction boron diffusion, preparing a graphical mask on a boron diffusion surface, etching the area without the mask into a light-doped area by using etching slurry after the mask is prepared, and forming the selective emitter.
In view of this, it is necessary to provide a method for manufacturing a solar cell with a selective emitter, which has a simple process, short time consumption, and low cost.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a preparation method of a solar cell which is simple in process, short in time consumption, low in cost and capable of accurately having a selective emitter.
The invention discloses a preparation method of a solar cell with a selective emitter, which adopts the technical scheme that: the method comprises the following steps:
(1) growing a mask layer on any side of the silicon substrate subjected to the double-side texturing treatment, wherein one side of the grown mask layer is used as the front side of the silicon substrate;
(2) locally printing an etching slurry layer on the mask layer on the front surface of the silicon substrate, and drying; in the drying process, the etching slurry layer reacts with the mask layer, so that the mask layer in the area of the printing etching slurry layer is etched, and the mask layer in the area of the etching slurry layer which is not printed is reserved; wherein the etching slurry layer only reacts with the mask layer;
(3) carrying out boron diffusion treatment on the silicon substrate to form a heavily doped region in a region without the mask layer, and forming a lightly doped region in a region containing the mask layer so as to form a front boron selective emitter; in the boron diffusion process, the light doping area and the heavy doping area are covered with borosilicate glass layers to form a front borosilicate glass layer, and meanwhile, part of doping sources extend to the edge area of the back to form a back borosilicate glass layer;
(4) etching the texturing surface on the back surface of the silicon substrate into a plane, and simultaneously removing the borosilicate glass layer on the front surface;
(5) growing a tunneling oxide layer and a doped amorphous silicon layer on the back surface of the silicon substrate, and carrying out annealing treatment to activate doped atoms on the back surface of the silicon substrate to complete crystallization and form a doped polycrystalline silicon layer;
(6) depositing a back passivation film on the back of the silicon substrate, and depositing a front passivation antireflection film on the front of the silicon substrate;
(7) and printing a front main grid and a front auxiliary grid on the front surface of the silicon substrate, printing a back main grid and a back auxiliary grid on the back surface of the silicon substrate, and drying.
The invention provides a preparation method of a solar cell with a selective emitter, which also comprises the following subsidiary technical scheme:
in the step (2), the printed pattern of the etching slurry layer printed locally is the same as the front side sub-grid pattern.
Wherein, prior to step (3), the method further comprises:
(3) and', cleaning the silicon substrate processed in the step (2) to remove the etching slurry layer and the mask layer below the etching slurry layer.
Wherein, in the step (2), the mask layer is SiO2Dielectric film or SiNXDielectric film, or SiO2And SiNXThe formed laminated film has a thickness of 20-100nm and is prepared by PECVD or ALD.
In the step (3), a boron source for boron diffusion is boron tribromide, the diffusion temperature is 900-1070 ℃, the diffusion time is 90-240 min, and the diffused square resistance value is 50-200 omega/sqr.
In the step (3)', the silicon substrate processed in the step (2) is cleaned by clear water to remove the etching slurry layer and the mask layer below the etching slurry layer, and the temperature of the clear water is 40-80 ℃.
Wherein, in step (5); the tunneling oxide layer is made of silicon dioxide, the thickness of the tunneling oxide layer is 0.5-2 nm, and the preparation method is a nitric acid oxidation method, a high-temperature thermal oxidation method, an ozone oxidation method or an atomic layer deposition method;
wherein, when the preparation method is a high-temperature thermal oxidation method, the reaction is carried out for 10-20 min under the conditions of normal pressure, pure oxygen and the temperature of 500-700 ℃;
when the preparation method is a nitric acid oxidation method, a nitric acid solution with the mass fraction of 60-68% is adopted to react for 4-10 min at the reaction temperature of 80-100 ℃.
In the step (5), the method for growing the doped amorphous silicon layer on the back surface of the silicon substrate is a magnetron sputtering method, the silicon substrate is placed in an argon atmosphere, the reaction pressure is adjusted to be 0.1-0.7 Pa, the reaction temperature is 100-300 ℃, and the reaction lasts for 10 min-3 h.
Wherein the front passivation anti-reflection film is SiO2、SiNXOr Al2O3One or a combination of any several of the dielectric films, and the back passivation antireflection film is SiO2、SiNXOne or a combination of any several of the dielectric films.
In the step (7), the front main grid and the front auxiliary grid are printed by adopting aluminum-doped silver paste, and the back main grid and the back auxiliary grid are printed by adopting silver paste; wherein, the line width of the back side auxiliary grid is 35-90 um and the back side auxiliary grid are arranged in parallel; the line width of the front side auxiliary grid is 30-90 um and the front side auxiliary grid are arranged in parallel.
The implementation of the invention comprises the following technical effects:
the invention adopts the boron diffusion for one time to form the selective emitter, thereby avoiding the method of forming the selective emitter by a two-time diffusion method, improving the minority carrier lifetime of the silicon substrate by the high-temperature damage of the two-time high-temperature diffusion to the silicon substrate, simplifying the process, reducing the working procedures and improving the productivity. In addition, the mask is etched by using the selective etching slurry, so that the direct damage to the pyramid suede of the silicon substrate when the selective emitter is formed by directly etching the emitter by using a common chemical etching method is avoided, the increase of the reflectivity caused by the damage of the pyramid suede can be effectively avoided, the current of the solar cell is improved, the efficiency is improved, and the defect that the etching rate of chemical etching is difficult to control is also avoided.
Drawings
Fig. 1 is a schematic cross-sectional view of a cell structure after step (1)' of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a cell structure after step (1) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a cell structure after step (2) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a cell structure after step (3)' of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a cell structure after step (3) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a cell structure after step (4) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a cell structure after an ultra-thin tunnel oxide layer is prepared in step (5) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of a cell structure after a doped amorphous silicon layer is prepared in step (5) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of a cell structure after annealing treatment in step (5) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of a cell structure after step (6) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view of a cell structure after step (7) of a method for manufacturing a solar cell with a selective emitter according to an embodiment of the present invention.
In the figure, 1-N type crystal silicon substrate, 2-mask layer, 3-etching slurry layer, 41-lightly doped region, 42-heavily doped region, 5-BSG borosilicate glass layer, 6-ultrathin tunneling oxide layer, 7-doped amorphous silicon layer, 8-doped polycrystalline silicon layer, 9-back passivation film, 10-front passivation antireflection film, 11-front side auxiliary gate and 12-back side auxiliary gate.
Detailed Description
The present invention will be described in detail with reference to examples.
The present invention is not limited to the above-described embodiments, and those skilled in the art can make modifications to the embodiments without any inventive contribution as required after reading the present specification, but only protected within the scope of the appended claims.
The invention relates to a preparation method of a solar cell with a selective emitter,
the method comprises the following steps:
(1) growing a mask layer on any side of the silicon substrate subjected to the double-side texturing treatment, wherein one side of the grown mask layer is used as the front side of the silicon substrate;
(2) locally printing an etching slurry layer on the mask layer on the front surface of the silicon substrate, and drying; in the drying process, the etching slurry layer reacts with the mask layer, so that the mask layer in the area of the printing etching slurry layer is etched, and the mask layer in the area of the etching slurry layer which is not printed is reserved; wherein the etching slurry layer only reacts with the mask layer;
(3) carrying out boron diffusion treatment on the silicon substrate to form a heavily doped region in a region without the mask layer, and forming a lightly doped region in a region containing the mask layer so as to form a front boron selective emitter; in the boron diffusion process, the light doping area and the heavy doping area are covered with borosilicate glass layers to form a front borosilicate glass layer, and meanwhile, part of doping sources extend to the edge area of the back to form a back borosilicate glass layer;
(4) etching the texturing surface on the back surface of the silicon substrate into a plane, and simultaneously removing the borosilicate glass layer on the front surface;
(5) growing a tunneling oxide layer and a doped amorphous silicon layer on the back surface of the silicon substrate, and carrying out annealing treatment to activate doped atoms on the back surface of the silicon substrate to complete crystallization and form a doped polycrystalline silicon layer;
(6) depositing a back passivation film on the back of the silicon substrate, and depositing a front passivation antireflection film on the front of the silicon substrate;
(7) and printing a front main grid and a front auxiliary grid on the front surface of the silicon substrate, printing a back main grid and a back auxiliary grid on the back surface of the silicon substrate, and drying.
In one embodiment, in the step (1), the N-type crystalline silicon substrate has a resistivity of 1 to 5. omega. cm and a thickness of 80 to 200. mu.m.
In one embodiment, in the step (2), the printed pattern of the etching paste layer printed locally is the same as the front side sub-gate pattern.
Preferably, before step (3), the method further comprises:
(3) and', cleaning the silicon substrate processed in the step (2) to remove the etching slurry layer and the mask layer below the etching slurry layer.
In one embodiment, in the step (2), the mask layer is SiO2Dielectric film or SiNXDielectric film, or SiO2And SiNXThe formed laminated film has a thickness of 20-100nm and is prepared by PECVD or ALD.
In one embodiment, in the step (3), the boron source for boron diffusion is boron tribromide, the diffusion temperature is 900 to 1070 ℃, the diffusion time is 90 to 240min, and the diffused square resistance value is 50 to 200 Ω/sqr.
In one embodiment, in the step (3)', the silicon substrate processed in the step (2) is cleaned by using clean water to remove the etching slurry layer and the mask layer below the etching slurry layer, wherein the temperature of the clean water is 40-80 ℃.
In one embodiment, in step (5), the temperature of the high temperature annealing is 800-.
In one embodiment, in step (5); the tunneling oxide layer is made of silicon dioxide, the thickness of the tunneling oxide layer is 0.5-2 nm, and the preparation method is a nitric acid oxidation method, a high-temperature thermal oxidation method, an ozone oxidation method or an atomic layer deposition method;
wherein, when the preparation method is a high-temperature thermal oxidation method, the reaction is carried out for 10-20 min under the conditions of normal pressure, pure oxygen and the temperature of 500-700 ℃;
when the preparation method is a nitric acid oxidation method, a nitric acid solution with the mass fraction of 60-68% is adopted to react for 4-10 min at the reaction temperature of 80-100 ℃.
In one embodiment, in the step (5), the method for growing the doped amorphous silicon layer on the back surface of the silicon substrate is a magnetron sputtering method, the silicon substrate is placed in an argon atmosphere, the reaction pressure is adjusted to be 0.1-0.7 Pa, the reaction temperature is adjusted to be 100-300 ℃, and the reaction time is 10 min-3 h.
In one embodiment, the front passivation antireflective film is SiO2、SiNXOr Al2O3One or a combination of any several of the dielectric films, and the back passivation antireflection film is SiO2、SiNXOne or a combination of any several of the dielectric films.
In one embodiment, in the step (7), the front main grid and the front auxiliary grid are printed by adopting aluminum-doped silver paste, and the back main grid and the back auxiliary grid are printed by adopting silver paste; in one embodiment, the back side sub-gate line width is 35-90 um and the back side sub-gate line widths are arranged in parallel; the line width of the front side auxiliary grid is 30-90 um and the front side auxiliary grid are arranged in parallel.
Optionally, before step (1), the method further comprises:
and (1)', selecting an N-type crystal silicon substrate, and performing two-side texturing treatment on the N-type crystal silicon substrate.
The invention adopts the boron diffusion for one time to form the selective emitter, thereby avoiding the method of forming the selective emitter by a two-time diffusion method, improving the minority carrier lifetime of the silicon substrate by the high-temperature damage of the two-time high-temperature diffusion to the silicon substrate, simplifying the process, reducing the working procedures and improving the productivity. In addition, the mask is etched by using the selective etching slurry, so that the direct damage to the pyramid suede of the silicon substrate when the selective emitter is formed by directly etching the emitter by using a common chemical etching method is avoided, the increase of the reflectivity caused by the damage of the pyramid suede can be effectively avoided, the current of the solar cell is improved, the efficiency is improved, and the defect that the etching rate of chemical etching is difficult to control is also avoided.
The production process of the invention will be described in detail below with specific examples.
Example 1
Step (1)', selecting an N-type crystalline silicon substrate 1, and carrying out double-sided texturing treatment on the N-type crystalline silicon substrate 1; wherein the resistivity of the N-type crystal silicon substrate 1 is 5 Ω · cm; the thickness of the N-type crystalline silicon substrate 1 was 170. mu.m. The cell structure after this step is completed is shown in fig. 1.
And (1) selecting any one surface of the N-type crystalline silicon substrate 1 processed in the step (1)' and growing a mask layer 2 by using a PECVD (plasma enhanced chemical vapor deposition) mode. Wherein, the mask layer 2 is made of SiO2And the thickness is 20 nm. The cell structure after this step is completed is shown in fig. 2.
And (2) locally printing a patterned etching slurry layer 3 on the mask layer 2 of the N-type crystalline silicon substrate 1 processed in the step (1), wherein the printed pattern is the same as the fine grid of the metallized pattern, and the etching slurry only reacts with the mask and does not damage the pyramid texture. The cell structure after this step is completed is shown in fig. 3.
And (3)', putting the N-type crystal silicon substrate processed in the step (2) into hot water at 50 ℃ for cleaning slurry, cleaning the printed etching slurry layer 3, and simultaneously etching the mask layer 2 below the slurry. The cell structure after this step is completed is shown in fig. 4.
And (3) placing the N-type crystalline silicon substrate processed in the step (3)' into a boron diffusion furnace for diffusion, wherein the diffusion mode is single-side diffusion, a light doped region 41 is formed in a region with a mask, and a heavy doped region 42 is formed in a region without the mask. Wherein the source of boron diffusion is boron tribromide, the diffusion temperature is 1020 ℃, the diffusion time is 240min, the sheet resistance of a lightly doped region is 200 omega/sqr, and the sheet resistance of a heavily doped region is 50 omega/sqr. And a BSG borosilicate glass layer 5 is covered on the lightly doped region and the heavily doped region, and part of the doping source winds and expands to the back surface to form the BSG borosilicate glass layer 5. The cell structure after this step is completed is shown in fig. 5.
And (4) etching the back surface of the N-type crystal silicon substrate processed in the step (3), forming a flat surface appearance on the back surface, and removing the BSG borosilicate glass layer 5 and the mask layer 2 on the front surface. The cell structure after this step is completed is shown in fig. 6.
Step (5), growing an ultrathin tunneling oxide layer 6 on the back surface of the N-type crystal silicon substrate processed in the step (4), wherein the ultrathin tunneling oxide layer is made of silicon dioxide, the preparation method of the silicon dioxide is thermal oxidation, and the thickness of the silicon dioxide layer is 2 nm; the cell structure after this step is completed is shown in fig. 7. And depositing a doped amorphous silicon layer 7 outside the ultrathin tunneling oxide layer 6 by using a PVD (physical vapor deposition) method, specifically, placing the silicon substrate in an argon atmosphere, adjusting the reaction pressure to be 0.1Pa, the reaction time to be 50min, and the reaction temperature to be 300 ℃, wherein the structure of the cell after the step is finished is shown in FIG. 8. And finally, annealing the N-type crystal silicon substrate 1, activating the doping atoms on the back to finish crystallization to form a doped polycrystalline silicon layer 8, wherein the annealing temperature is 800 ℃, the annealing time is 40min, and the structure of the cell after the step is finished is shown in fig. 9.
(6) And (3) depositing a silicon nitride passivation film 9 on the back surface of the N-type crystalline silicon substrate 1 treated in the step (5) to form a film with the thickness of 120nm, and depositing a laminated film 10 of aluminum oxide and silicon nitride on the front surface of the N-type crystalline silicon substrate. The structure of the cell after this step is completed is shown in fig. 10.
(7) And (3) firstly printing the back main grid and the back auxiliary grid on the back surface of the N-type crystalline silicon substrate 1 processed in the step (6) by using silver paste, and drying, wherein the line width of the back auxiliary grid is 12 microns, and the back auxiliary grid are parallel to each other. Printing a front main grid and a front auxiliary grid 11 on the front surface of the N-type crystalline silicon substrate 1 by using aluminum-doped silver paste, wherein the line width of the front auxiliary grid 11 is 45 mu m and the front auxiliary grid is parallel to each other; the cell structure after this step is completed is shown in fig. 11. And then conveying the N-type crystal silicon substrate 1 into a belt type sintering furnace for sintering, wherein the sintering peak temperature is 800 ℃, and thus, the preparation of the solar cell with the boron-doped selective emitter is completed.
Example 2
Step (1)', selecting an N-type crystalline silicon substrate 1, and carrying out double-sided texturing treatment on the N-type crystalline silicon substrate 1; wherein the resistivity of the N-type crystal silicon substrate 1 is 1. omega. cm; the thickness of the N-type crystalline silicon substrate 1 was 100. mu.m. The cell structure after this step is completed is shown in fig. 1.
And (1) selecting any one surface of the N-type crystalline silicon substrate 1 processed in the step (1)' and growing a mask layer 2 by using a PECVD (plasma enhanced chemical vapor deposition) mode. Wherein, the mask layer 2 is made of SiNXAnd the thickness is 50 nm. The cell structure after this step is completed is shown in fig. 2.
And (2) locally printing a patterned etching slurry layer 3 on the mask layer 2 of the N-type crystalline silicon substrate 1 processed in the step (1), wherein the printed pattern is the same as the fine grid of the metallized pattern, and the etching slurry only reacts with the mask and does not damage the pyramid texture. The cell structure after this step is completed is shown in fig. 3.
And (3)', putting the N-type crystalline silicon substrate treated in the step (2) into hot water at 40 ℃ for cleaning slurry, cleaning the printed etching slurry layer 3, and simultaneously corroding the mask layer 2 below the slurry. The cell structure after this step is completed is shown in fig. 4.
And (3) placing the N-type crystalline silicon substrate processed in the step (3)' into a boron diffusion furnace for diffusion, wherein the diffusion mode is single-side diffusion, a light doped region 41 is formed in a region with a mask, and a heavy doped region 42 is formed in a region without the mask. Wherein, the source of boron diffusion is boron tribromide, the diffusion temperature is 900 ℃, the diffusion time is 90min, the sheet resistance of a lightly doped region is 50 omega/sqr, and the sheet resistance of a heavily doped region is 50 omega/sqr. In the boron diffusion process, a BSG borosilicate glass layer 5 is covered on the lightly doped region and the heavily doped region, and part of the doping source winds and expands to the back side to form the BSG borosilicate glass layer 5. The cell structure after this step is completed is shown in fig. 5.
And (4) etching the back surface of the N-type crystal silicon substrate processed in the step (3), forming a flat surface appearance on the back surface, and removing the BSG borosilicate glass layer 5 and the mask layer 2 on the front surface. The cell structure after this step is completed is shown in fig. 6.
Step (5) growing an ultrathin tunneling oxide layer 6 on the back surface of the N-type crystal silicon substrate treated in the step (4), wherein the ultrathin tunneling oxide layer is made of silicon dioxide, the preparation method of the silicon dioxide is a high-temperature thermal oxidation method, specifically, the N-type crystal silicon substrate treated in the step (6) is placed under the conditions of normal pressure, pure oxygen and 500 ℃, and reacts for 10min to form a silicon dioxide layer with the thickness of 3 nm; the cell structure after this step is completed is shown in fig. 7. And depositing a doped amorphous silicon layer 7 outside the ultrathin tunneling oxide layer 6 by using a magnetron sputtering method. Specifically, the silicon substrate was placed in an argon atmosphere, the reaction pressure was adjusted to 0.4Pa, the reaction time was 50min, the reaction temperature was 100 ℃, and the cell structure after completion of this step is shown in fig. 8. And finally, annealing the N-type crystal silicon substrate 1, activating the doping atoms on the back to finish crystallization to form a doped polycrystalline silicon layer 8, wherein the annealing temperature is 1000 ℃, the annealing time is 20min, and the structure of the cell after the step is finished is shown in figure 9.
(6) And (3) depositing a layer of silicon nitride and silicon dioxide composite film as a passivation film 9 on the back surface of the N-type crystalline silicon substrate 1 treated in the step (5), wherein the film thickness is 120nm, and depositing a layer of aluminum oxide and silicon dioxide laminated film 10 on the front surface of the N-type crystalline silicon substrate. The structure of the cell after this step is completed is shown in fig. 10.
(7) And (3) firstly printing the back main grid and the back auxiliary grid on the back surface of the N-type crystalline silicon substrate 1 processed in the step (6) by using silver paste, and drying, wherein the line width of the back auxiliary grid is 12 um, and the back auxiliary grid are parallel to each other. Printing a front main grid and a front auxiliary grid 11 on the front surface of the N-type crystalline silicon substrate 1 by using aluminum-doped silver paste, wherein the line width of the front auxiliary grid 11 is 90 mu m and the front auxiliary grid is parallel to each other; the cell structure after this step is completed is shown in fig. 11. And then conveying the N-type crystal silicon substrate 1 into a belt type sintering furnace for sintering, wherein the sintering peak temperature is 800 ℃, and thus, the preparation of the solar cell with the boron-doped selective emitter is completed.
Example 3
Step (1)', selecting an N-type crystalline silicon substrate 1, and carrying out double-sided texturing treatment on the N-type crystalline silicon substrate 1; wherein the resistivity of the N-type crystal silicon substrate 1 is 3. omega. cm; the thickness of the N-type crystalline silicon substrate 1 was 170. mu.m. The cell structure after this step is completed is shown in fig. 1.
And (1) selecting any one surface of the N-type crystalline silicon substrate 1 processed in the step (1)' and growing a mask layer 2 by using a PECVD (plasma enhanced chemical vapor deposition) mode. Wherein, the mask layer 2 is made of SiO2And SiNXThe thickness of the formed laminated film was 100 nm. The cell structure after this step is completed is shown in fig. 2.
And (2) locally printing a patterned etching slurry layer 3 on the mask layer 2 of the N-type crystalline silicon substrate 1 processed in the step (1), wherein the printed pattern is the same as the fine grid of the metallized pattern, and the etching slurry only reacts with the mask and does not damage the pyramid texture. The cell structure after this step is completed is shown in fig. 3.
And (3)', putting the N-type crystalline silicon substrate treated in the step (2) into hot water at 80 ℃ for cleaning slurry, cleaning the printed etching slurry layer 3, and simultaneously corroding the mask layer 2 below the slurry. The cell structure after this step is completed is shown in fig. 4.
And (3) placing the N-type crystalline silicon substrate processed in the step (3)' into a boron diffusion furnace for diffusion, wherein the diffusion mode is single-side diffusion, a light doped region 41 is formed in a region with a mask, and a heavy doped region 42 is formed in a region without the mask. Wherein, the source of boron diffusion is boron tribromide, the diffusion temperature is 1070 ℃, the diffusion time is 220min, the square resistance of a lightly doped region is 100 omega/sqr, and the square resistance of a heavily doped region is 70 omega/sqr. And a BSG borosilicate glass layer 5 is covered on the lightly doped region and the heavily doped region, and part of the doping source winds and expands to the back surface to form the BSG borosilicate glass layer 5. The cell structure after this step is completed is shown in fig. 5.
And (4) etching the back surface of the N-type crystal silicon substrate processed in the step (3), forming a flat surface appearance on the back surface, and removing the BSG borosilicate glass layer 5 and the mask layer 2 on the front surface. The cell structure after this step is completed is shown in fig. 6.
Growing an ultrathin tunneling oxide layer 6 on the back surface of the N-type crystal silicon substrate treated in the step (4), wherein the ultrathin tunneling oxide layer is made of silicon dioxide, the preparation method of the silicon dioxide is a nitric acid oxidation method, and specifically, the N-type crystal silicon substrate treated in the step (6) is placed in a nitric acid solution with the mass fraction of 60-68%, and is reacted at the reaction temperature of 80-100 ℃ for 4-10 min to form a silicon dioxide layer with the thickness of 2 nm; the cell structure after this step is completed is shown in fig. 7. And depositing a doped amorphous silicon layer 7 outside the ultrathin tunneling oxide layer 6 by using a PVD (physical vapor deposition) method, wherein the silicon substrate is placed in an argon atmosphere, the reaction pressure is adjusted to be 0.7Pa, the reaction time is 50min, the reaction temperature is 300 ℃, and the structure of the cell after the step is finished is shown in fig. 8. And finally, annealing the N-type crystal silicon substrate 1, activating the doping atoms on the back to finish crystallization to form a doped polycrystalline silicon layer 8, wherein the annealing temperature is 900 ℃, the annealing time is 60min, and the structure of the cell after the step is finished is shown in fig. 9.
(6) And (3) depositing a layer of silicon dioxide passivation film 9 on the back surface of the N-type crystalline silicon substrate 1 treated in the step (5) to form a film with the thickness of 100nm, and depositing a layer of silicon dioxide and silicon nitride laminated film 10 on the front surface of the N-type crystalline silicon substrate. The structure of the cell after this step is completed is shown in fig. 10.
(7) And (3) firstly printing the back main grid and the back auxiliary grid on the back surface of the N-type crystalline silicon substrate 1 processed in the step (6) by using silver paste, and drying, wherein the line width of the back auxiliary grid is 12 um, and the back auxiliary grid are parallel to each other. Printing a front main grid and a front auxiliary grid 11 on the front surface of the N-type crystalline silicon substrate 1 by using aluminum-doped silver paste, wherein the line width of the front auxiliary grid 11 is 90 mu m and the front auxiliary grid is parallel to each other; the cell structure after this step is completed is shown in fig. 11. And then conveying the N-type crystal silicon substrate 1 into a belt type sintering furnace for sintering, wherein the sintering peak temperature is 800 ℃, and thus, the preparation of the solar cell with the boron-doped selective emitter is completed.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (10)
1. A method for preparing a solar cell with a selective emitter is characterized in that: the method comprises the following steps:
(1) growing a mask layer on any side of the silicon substrate subjected to the double-side texturing treatment, wherein one side of the grown mask layer is used as the front side of the silicon substrate;
(2) locally printing an etching slurry layer on the mask layer on the front surface of the silicon substrate, and drying to etch the mask layer in the area of the printing etching slurry layer and retain the mask layer in the area of the etching slurry layer which is not printed;
(3) carrying out boron diffusion treatment on the silicon substrate to form a heavily doped region in a region without the mask layer, and forming a lightly doped region in a region containing the mask layer so as to form a front boron selective emitter; in the boron diffusion process, the light doping area and the heavy doping area are covered with borosilicate glass layers to form a front borosilicate glass layer, and meanwhile, part of doping sources extend to the edge area of the back to form a back borosilicate glass layer;
(4) etching the texturing surface on the back surface of the silicon substrate into a plane, and simultaneously removing the borosilicate glass layer on the front surface;
(5) growing a tunneling oxide layer and a doped amorphous silicon layer on the back surface of the silicon substrate, and carrying out annealing treatment to activate doped atoms on the back surface of the silicon substrate to complete crystallization and form a doped polycrystalline silicon layer;
(6) depositing a back passivation film on the back of the silicon substrate, and depositing a front passivation antireflection film on the front of the silicon substrate;
(7) and printing a front main grid and a front auxiliary grid on the front surface of the silicon substrate, printing a back main grid and a back auxiliary grid on the back surface of the silicon substrate, and drying.
2. The production method according to claim 1, wherein in the step (2), the locally printed pattern of the etching paste layer is the same as the front side sub-gate pattern.
3. The method of claim 1 or 2, wherein prior to step (3), the method further comprises:
(3) and', cleaning the silicon substrate processed in the step (2) to remove the etching slurry layer and the mask layer below the etching slurry layer.
4. The production method according to claim 1 or 2, wherein in the step (2), the mask layer is SiO2Dielectric film or SiNXDielectric film, or SiO2And SiNXThe formed laminated film has a thickness of 20-100nm and is prepared by PECVD or ALD.
5. The production method according to claim 1 or 2, wherein in the step (3), a boron source for boron diffusion is boron tribromide, the diffusion temperature is 900 to 1070 ℃, the diffusion time is 90 to 240min, and the diffused square resistance is 50 to 200 Ω/sqr.
6. The method according to claim 3, wherein in the step (3)', the silicon substrate processed in the step (2) is cleaned with clear water to remove the etching slurry layer and the mask layer under the etching slurry layer, and the temperature of the clear water is 40-80 ℃.
7. The production method according to claim 1 or 2, wherein, in step (5); the tunneling oxide layer is made of silicon dioxide, the thickness of the tunneling oxide layer is 0.5-2 nm, and the preparation method is a nitric acid oxidation method, a high-temperature thermal oxidation method, an ozone oxidation method or an atomic layer deposition method;
wherein, when the preparation method is a high-temperature thermal oxidation method, the reaction is carried out for 10-20 min under the conditions of normal pressure, pure oxygen and the temperature of 500-700 ℃;
when the preparation method is a nitric acid oxidation method, a nitric acid solution with the mass fraction of 60-68% is adopted to react for 4-10 min at the reaction temperature of 80-100 ℃.
8. The method of claim 7, wherein in the step (5), the doped amorphous silicon layer is grown on the back surface of the silicon substrate by magnetron sputtering, the silicon substrate is placed in an argon atmosphere, the reaction pressure is adjusted to 0.1 to 0.7Pa, the reaction temperature is adjusted to 100 to 300 ℃, and the reaction time is 10min to 3 h.
9. The production method according to claim 1 or 2, wherein the front passivation anti-reflective film is SiO2、SiNXOr Al2O3One or a combination of any several of the dielectric films, and the back passivation antireflection film is SiO2、SiNXOne or a combination of any several of the dielectric films.
10. The preparation method according to claim 1 or 2, characterized in that, in the step (7), the front main grid and the front auxiliary grid are printed by adopting aluminum-doped silver paste, and the back main grid and the back auxiliary grid are printed by adopting silver paste; wherein, the line width of the back side auxiliary grid is 35-90 um and the back side auxiliary grid are arranged in parallel; the line width of the front side auxiliary grid is 30-90 um and the front side auxiliary grid are arranged in parallel.
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