CN219371039U - P-type passivation contact battery - Google Patents
P-type passivation contact battery Download PDFInfo
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- CN219371039U CN219371039U CN202320518362.4U CN202320518362U CN219371039U CN 219371039 U CN219371039 U CN 219371039U CN 202320518362 U CN202320518362 U CN 202320518362U CN 219371039 U CN219371039 U CN 219371039U
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Abstract
The utility model discloses a P-type passivation contact battery, which comprises a P-type silicon wafer, wherein the back surface of the P-type silicon wafer is sequentially provided with a tunneling oxide layer, a boron-doped polysilicon layer and a back surface passivation antireflection layer, a back surface annealing oxide layer is arranged between the boron-doped polysilicon layer and the back surface passivation antireflection layer, the P-type passivation contact battery also comprises a plurality of back surface electrodes positioned on the back surface of the P-type silicon wafer, and one end of each back surface electrode, which is close to the back surface of the P-type silicon wafer, penetrates through the back surface annealing oxide layer and the back surface passivation antireflection layer and is connected with the boron-doped polysilicon layer; the front side of the P-type silicon wafer is sequentially provided with a phosphorus diffusion layer, a front side annealing oxide layer and an ITO film layer. The P-type passivation contact battery has a good passivation contact structure, can promote passivation effect and reduce P+ poly plasma damage, is beneficial to improving open-circuit voltage of the battery, reduces metal contact composite current and improves conversion efficiency of the battery.
Description
Technical Field
The utility model belongs to the technical field of photovoltaic solar cells, and particularly relates to a P-type passivation contact cell.
Background
Currently, the mainstream P-type battery is a PERC (Passivated Emitter and Rear Cell abbreviation, emitter and back passivation battery) battery, which uses an alumina material to form a good passivation layer on the back of the battery piece, so as to play a role in chemical passivation and field passivation. However, in the existing P-type battery, the back electrode penetrating back surface film layer is directly contacted with the back surface of the silicon wafer, the passivation effect is poor, and the open-circuit voltage of the corresponding battery is low, so that the technology almost reaches the bottleneck stage, and further breakthrough of efficiency is difficult to realize through the existing equipment and process optimization. For the P-type PERC battery, there is a technology of laser grooving on the back surface in order to promote contact performance, but this method has many back surface preparation steps and causes a certain degree of laser damage to the back surface.
Disclosure of Invention
In view of the above, in order to overcome the defects of the prior art, the utility model aims to provide a P-type passivation contact battery, which is used for solving the problem of poor passivation effect of the P-type battery in the prior art, greatly improving chemical passivation and field passivation and reducing metal contact composite current.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
the P-type passivation contact battery comprises a P-type silicon wafer, wherein a tunneling oxide layer, a boron-doped polysilicon layer and a back passivation anti-reflection layer are sequentially arranged on the back surface of the P-type silicon wafer, a back annealing oxide layer is arranged between the boron-doped polysilicon layer and the back passivation anti-reflection layer, the P-type passivation contact battery also comprises a plurality of back electrodes positioned on the back surface of the P-type silicon wafer, and one end of each back electrode, which is close to the back surface of the P-type silicon wafer, penetrates through the back annealing oxide layer and the back passivation anti-reflection layer and is connected with the boron-doped polysilicon layer; and a phosphorus diffusion layer, a front annealing oxide layer and an ITO (indium tin oxide) film layer are sequentially arranged on the front of the P-type silicon wafer.
The passivation effect is improved and the plasma damage of P+ poly is reduced by adding a back annealing oxide layer on the back of the P-type silicon wafer; the back electrode and the boron doped polysilicon layer are arranged to form ohmic contact, so that the direct contact between the back electrode and the silicon wafer is effectively avoided, and the tunneling and barrier effect is utilized, carriers are selectively transmitted, a good passivation contact structure is formed, and the open-circuit voltage of the battery is improved; in addition, the ITO film is arranged on the front surface, so that the uniformity is good, the process is stable, the conductivity is strong, and the transverse transmission resistance can be effectively reduced.
According to some preferred embodiments of the present utility model, the material of the back annealing oxide layer and the front annealing oxide layer is SiO x 。
According to some preferred embodiments of the present utility model, the front-side electrode further comprises a plurality of front-side electrodes located on the front-side of the P-type silicon wafer, and one end of the front-side electrode, which is close to the front-side of the P-type silicon wafer, penetrates through the phosphorus diffusion layer, the front-side annealing oxide layer and the ITO film layer and is connected with the front-side of the P-type silicon wafer.
According to some preferred embodiments of the utility model, the front and back electrodes are sintered from silver paste or silver aluminum paste. By the arrangement, laser grooving is not needed on the back surface, and laser damage can be avoided.
According to some preferred embodiments of the present utility model, the ends of the back electrodes away from the back surface of the P-type silicon wafer extend outwards to the same height, and the ends of the front electrodes away from the front surface of the P-type silicon wafer extend outwards to the same height.
According to some preferred embodiments of the present utility model, the back passivation anti-reflection layer has a thickness of 5-200nm, and comprises a first back passivation anti-reflection layer and a second back passivation anti-reflection layer, wherein the material of the first back passivation anti-reflection layer is AlO x . In some embodiments of the present utility model, the second backside passivation anti-reflection layer is made of SiN x Layer, siO x N y Layer, siO x A dielectric layer comprising a combination of one or more of the layers.
According to some preferred embodiments of the utility model, the thickness of the ITO film layer is 5-200nm.
According to some preferred embodiments of the present utility model, the tunneling oxide layer is made of SiO 2 The thickness of the tunneling oxide layer is 1-6nm.
According to some preferred embodiments of the present utility model, the P-type silicon wafer has a resistivity of 0.4 to 3 Ω -cm and a thickness of 50 to 300 μm.
According to some preferred embodiments of the present utility model, the sheet resistance of the boron doped polysilicon layer is 60-300ohm/sq and the sheet resistance of the phosphorus diffusion layer is 60-200ohm/sq.
Compared with the prior art, the utility model has the following advantages: according to the P-type passivation contact battery, the back annealing oxide layer is added to the back of the P-type silicon wafer, so that the passivation effect can be improved, and the plasma damage of P+ poly can be reduced; the back electrode is connected with the boron doped polysilicon layer (ohmic contact), so that the direct contact between the back electrode and silicon can be effectively avoided, and a good passivation contact structure is formed by utilizing tunneling and barrier effect and carrier selective transmission; the positive film layer of the P-type silicon wafer adopts an ITO film, so that the uniformity is good, the process is stable, the conductivity is strong, and the transverse transmission resistance is effectively reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural view of a P-type passivation contact cell in an embodiment of the utility model;
wherein, the reference numerals include: the semiconductor device comprises a P-type silicon wafer-1, a tunneling oxide layer-2, a boron doped polysilicon layer-3, a back annealing oxide layer-4, a first back passivation anti-reflection layer-5, a second back passivation anti-reflection layer-6, a phosphorus diffusion layer-7, a front annealing oxide layer-8, an ITO film layer-9, a front electrode-10 and a back electrode-11.
Detailed Description
In order to make the technical solution of the present utility model better understood by those skilled in the art, the technical solution of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.
Example 1P-type passivation contact Battery
As shown in fig. 1, the P-type passivation contact cell in this embodiment includes a P-type silicon wafer 1, the resistivity of the P-type silicon wafer 1 being 0.4-3Ω·cm; the thickness of the P-type silicon wafer 1 is 50-300 mu m.
The front surface of the P-type silicon wafer 1 is provided with a phosphorus diffusion layer 7, a front surface annealing oxide layer 8, an ITO film layer 9 and a front surface electrode 10; the front electrode 10 penetrates through the phosphorus diffusion layer 7, the front annealing oxide layer 8, the ITO film layer 9 and the front surface of the P-type silicon wafer 1 to form ohmic contact. The sheet resistance of the phosphorus diffusion layer 7 is 60-200ohm/sq; the material of the front annealing oxide layer 8 is SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the ITO film layer 9 is 5-200nm.
The back of the P-type silicon wafer 1 is provided with a tunneling oxide layer 2, a boron doped polysilicon layer 3, a back annealing oxide layer 4, a first back passivation antireflection layer 5, a second back passivation antireflection layer 6 and a back electrode 11; the back electrode 11 penetrates the second back passivation anti-reflection layer 6, the first back passivation anti-reflection layer 5, the back annealing oxide layer 4 and forms an ohmic contact with the boron doped polysilicon layer 3. Wherein the tunneling oxide layer 2 is made of SiO 2 The thickness is 1-6nm; the sheet resistance of the boron doped polysilicon layer 3 is 60-300ohm/sq; the material of the back annealing oxide layer 4 is SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the The material of the first back passivation anti-reflection layer 5 is AlO x The material of the second back passivation anti-reflection layer 6 is SiN x Layer, siO x N y Layer, siO x Dielectric layers formed by a combination of one or more of the layers, i.e. SiN alone x Layer, siO x N y Layer, siO x A layer of, or SiN x Layer, siO x N y Layer, siO x And if the dielectric films are in multiple layers, the deposition is not sequential, and the thickness of the whole back passivation anti-reflection layer is 5-200nm.
Specifically, the front surface of the P-type silicon wafer 1 is provided with a plurality of front surface electrodes 10, the back surface of the P-type silicon wafer 1 is provided with a plurality of back surface electrodes 11, one ends of the plurality of front surface electrodes 10 far away from the front surface of the P-type silicon wafer 1 extend outwards to the same height, and one ends of the plurality of back surface electrodes 11 far away from the back surface of the P-type silicon wafer 1 also extend outwards to the same height. And the back electrode 11 and the front electrode 10 are formed by sintering silver paste or silver-aluminum paste, so that laser grooving is not needed, and laser damage is avoided.
Specifically, in a preferred embodiment, the resistivity of the P-type silicon wafer 1 is 0.6Ω·cm; the thickness of the P-type silicon wafer 1 is 160 μm. The tunneling oxide layer 2 on the back of the P-type silicon wafer 1 is made of SiO 2 The thickness is 2nm; the sheet resistance of the boron doped polysilicon layer 3 is 200ohm/sq; the material of the back annealing oxide layer 4 is SiO 2 The thickness is 6nm; the material of the first back passivation anti-reflection layer 5 is AlO x The second back passivation anti-reflection layer 6 is made of SiN with the thickness of 5nm x Layer and SiO x N y A layer of SiN x The thickness of the layer is 65nm, siO x N y The layer thickness of (2) was 20nm, and deposition was not performed sequentially. The square resistance of the phosphorus diffusion layer 7 on the front side of the P-type silicon wafer 1 is 160ohm/sq; the material of the front annealing oxide layer 8 is SiO 2 The thickness is 6nm; the thickness of the ITO film layer 9 was 95nm.
The front ITO film of the P-type passivation contact battery has good uniformity, stable process and strong conductivity, and can effectively reduce transverse transmission resistance; the back annealing oxide layer 4 is added on the back, passivation effect is improved, plasma damage of P+ poly is reduced, laser grooving is not needed on the back, laser damage can be avoided, the interface state density between a silicon substrate and poly-Si is reduced through chemical passivation by the tunneling oxide layer 2, majority carrier holes are transported through a tunneling principle, minority carrier electrons are difficult to tunnel through the oxide layer due to potential barriers and poly-Si field effects, chemical passivation and field passivation are improved, metal contact composite current is reduced, and conversion efficiency of a battery is improved; and the back electrode 11 and the boron doped polysilicon layer 3 form ohmic contact, so that the direct contact between the back electrode 11 and silicon can be effectively avoided, and a good passivation contact structure is finally formed by utilizing tunneling and barrier effect and carrier selective transmission.
Example 2 preparation method of P-type passivation contact Battery
The embodiment provides a preparation method of a P-type passivation contact battery based on embodiment 1, which specifically comprises the following steps:
(1) Texturing
The P-type silicon wafer 1 is selected, and is subjected to texturing cleaning through a wet alkali solution to form a pyramid textured structure, wherein the resistivity of the substrate of the P-type silicon wafer 11 selected in the embodiment is 0.60 Ω & cm, the thickness is 160 μm, and the size is 182mm x 182mm.
The thickness of the single side of the P-type silicon wafer 1 after texturing is reduced to 2.5 mu m.
(2) Phosphorus expansion
And (3) performing phosphorus diffusion on the front surface of the P-type silicon wafer 1 processed in the step (1) to form an n+ layer. The phosphorus diffusion n+ layer can be prepared by using a low-pressure or normal-pressure diffusion furnace, in this embodiment, a low-pressure diffusion furnace, wherein POCl 3 The flow rate of the catalyst is 2000sccm, N 2 Flow rate is 12000sccm, O 2 The flow rate of (2) was 1200sccm, the phosphorus doping temperature was 890℃and the sheet resistance of the phosphorus diffusion layer 7 was 160ohm/sq.
(3) Back polishing
Alkaline polishing is carried out on the back surface of the P-type silicon wafer 1 treated in the step (2) by adopting KOH and an additive or adopting HF and HNO 3 The back of the P-type silicon wafer 1 is subjected to acid polishing, and wet chemical polishing is carried out, so that the weight is reduced to 0.25g.
(4) Preparation of tunneling oxide layer 2 and intrinsic poly layer
And (3) carrying out tunneling oxidation and amorphous silicon deposition on the front side and the back side of the P-type silicon wafer 1 processed in the step (3) to form a tunneling oxide layer 2 and an intrinsic poly layer. In the present embodiment, the thickness of the tunneling oxide layer 22 is 2nm, the intrinsic amorphous silicon is produced by PECVD or LPCVD, and SiH is used 4 、N 2 As a reaction gas, a gas such as methanol is used,SiH 4 is 600sccm, N 2 The flow rate of (C) was 6000sccm. Wherein the thickness of the intrinsic amorphous silicon is 160nm.
(5) Boron doping
And (3) performing boron doping on the back surface of the P-type silicon wafer 1 processed in the step (4) to form a boron doped polysilicon layer 3 (P+ poly layer). The boron doping temperature in this example was 920℃and BCl 3 The flow rate of (2) is 180sccm, N 2 Flow rate is 6000sccm, O 2 The flow rate of (2) was 1000sccm. The sheet resistance of the boron doped polysilicon layer 3 was 200ohm/sq.
(6) Wet chemical cleaning
And (3) carrying out wet cleaning on the P-type silicon wafer 1 processed in the step (5) to remove the front-side round-expanded borosilicate glass, the front-side poly, the front-side phosphosilicate glass and the back-side borosilicate glass. Firstly, removing borosilicate glass which is wound and expanded on the front surface by chain HF, and then alkaline polishing or HF and HNO by trough KOH and additive 3 And (3) acid polishing is carried out to remove the front poly, and finally, groove type HF is used to remove the front phosphosilicate glass and the back borosilicate glass.
(7) Front and back oxidation annealing
And (3) carrying out front and back oxidation annealing treatment on the P-type silicon wafer 1 treated in the step (6), and passivating the surface and repairing dangling bonds by using a tubular annealing furnace at 680 ℃ to form a front annealing oxide layer 8 and a back annealing oxide layer 4, wherein the thickness of each front annealing oxide layer is 6nm.
(8) Backside passivation
And (3) carrying out back passivation process treatment on the back surface of the P-type silicon wafer 1 treated in the step (7) to form a first back passivation antireflection layer 5 and a second back passivation antireflection layer 6.
(9) Front passivation
And (3) carrying out passivation process treatment on the front side of the P-type silicon wafer 1 treated in the step (8), and depositing by adopting a low-voltage magnetron sputtering mode to form an ITO film layer 9 on the front side.
(10) Preparation of metal electrodes
And (3) preparing metal electrodes on the front side and the back side of the P-type silicon wafer 1 processed in the step (9), forming a front electrode 10 on the front side, forming a back electrode 11 on the back side, sintering to form ohmic contact, and performing light injection treatment to complete the manufacture of the battery to obtain the P-type passivation contact battery shown in figure 1. The front electrode 10 and the back electrode 11 of the battery are formed by sintering silver paste, and laser grooving is not needed in the preparation method, so that the battery can be prevented from being damaged by laser.
In the preparation process, the back annealing oxide layer 4 is added on the back of the P-type silicon wafer 1, so that the passivation effect can be improved and the plasma damage of P+ poly can be reduced; the back electrode 11 is connected (ohmic contact) with the boron doped polysilicon layer 3, so that the direct contact between the back electrode 11 and silicon can be effectively avoided, and a good passivation contact structure is formed by utilizing tunneling and barrier effect and carrier selective transmission; the ITO film layer 9 is deposited on the front side of the P-type silicon wafer 1 through low-voltage magnetron sputtering, so that the uniformity is good, the process is stable, the conductivity is strong, and the transverse transmission resistance can be effectively reduced.
The above embodiments are only for illustrating the technical concept and features of the present utility model, and are intended to enable those skilled in the art to understand the present utility model and to implement the same, but are not intended to limit the scope of the present utility model, and all equivalent changes or modifications made according to the spirit of the present utility model should be included in the scope of the present utility model.
Claims (10)
1. The P-type passivation contact battery comprises a P-type silicon wafer, wherein a tunneling oxide layer, a boron-doped polysilicon layer and a back passivation antireflection layer are sequentially arranged on the back surface of the P-type silicon wafer, and the P-type passivation contact battery is characterized in that a back annealing oxide layer is arranged between the boron-doped polysilicon layer and the back passivation antireflection layer, and the P-type passivation contact battery further comprises a plurality of back electrodes positioned on the back surface of the P-type silicon wafer, and one end of each back electrode, which is close to the back surface of the P-type silicon wafer, penetrates through the back annealing oxide layer and the back passivation antireflection layer and is connected with the boron-doped polysilicon layer; and the front surface of the P-type silicon wafer is sequentially provided with a phosphorus diffusion layer, a front surface annealing oxide layer and an ITO film layer.
2. The P-type passivated contact cell of claim 1 wherein the backside annealed oxide layer and the front side annealed oxide layerThe materials of (a) are SiO x 。
3. The P-type passivation contact battery of claim 1, further comprising a plurality of front-side electrodes positioned on the front-side of the P-type silicon wafer, wherein one end of the front-side electrodes, which is close to the front-side of the P-type silicon wafer, penetrates through the phosphorus diffusion layer, the front-side annealing oxide layer and the ITO film layer and is connected with the front-side of the P-type silicon wafer.
4. A P-type passivation contact battery according to claim 3, wherein the front and back electrodes are formed by sintering silver paste or silver aluminum paste.
5. A P-type passivation contact cell according to claim 3, wherein the plurality of back electrodes extend outwardly to the same height from an end of the back surface of the P-type silicon wafer and the plurality of front electrodes extend outwardly to the same height from an end of the front surface of the P-type silicon wafer.
6. The P-type passivation contact cell of claim 1, wherein the back side passivation anti-reflection layer has a thickness of 5-200nm, the back side passivation anti-reflection layer comprises a first back side passivation anti-reflection layer and a second back side passivation anti-reflection layer, and the first back side passivation anti-reflection layer is made of AlO x 。
7. The P-type passivation contact battery of claim 1, wherein the thickness of the ITO film layer is 5-200nm.
8. The P-type passivation contact battery of claim 1, wherein the tunneling oxide layer is made of SiO 2 The thickness of the tunneling oxide layer is 1-6nm.
9. The P-type passivation contact battery of claim 1, wherein the P-type silicon wafer has a resistivity of 0.4-3 Ω -cm and a thickness of 50-300 μm.
10. The P-type passivated contact cell of claim 1 wherein the boron doped polysilicon layer has a sheet resistance of 60-300ohm/sq and the phosphorus diffusion layer has a sheet resistance of 60-200ohm/sq.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320518362.4U CN219371039U (en) | 2023-03-16 | 2023-03-16 | P-type passivation contact battery |
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| CN202320518362.4U CN219371039U (en) | 2023-03-16 | 2023-03-16 | P-type passivation contact battery |
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