CN115101621B - P-topcon battery and preparation method thereof - Google Patents
P-topcon battery and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 31
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 238000005498 polishing Methods 0.000 claims abstract description 21
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 17
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052709 silver Inorganic materials 0.000 claims abstract description 17
- 239000004332 silver Substances 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 230000005641 tunneling Effects 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 238000005245 sintering Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000001465 metallisation Methods 0.000 claims abstract description 6
- 238000007747 plating Methods 0.000 claims abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 12
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000000654 additive Substances 0.000 claims description 6
- 239000003513 alkali Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical group ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052796 boron Inorganic materials 0.000 abstract description 13
- 238000004140 cleaning Methods 0.000 abstract description 10
- 235000012431 wafers Nutrition 0.000 description 22
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 230000000996 additive effect Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- -1 silver aluminum Chemical compound 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000011056 performance test Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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Abstract
The application provides a P-topcon battery and a preparation method thereof, wherein the method comprises the following steps: (1) polishing a P-type monocrystalline silicon wafer; (2) Tunneling an oxide layer and a polycrystalline silicon layer on the back surface of the P-type monocrystalline silicon wafer, and etching and texturing the front surface of the P-type monocrystalline silicon wafer; (3) depositing alumina on the front surface of the P-type monocrystalline silicon piece; carrying out laser doping on the front side and plating a passivation layer and/or an antireflection layer on the front side and the back side according to any sequence; the laser doping forms a patterned p+ doped front surface field with alumina; (4) And printing a silver paste main grid and an auxiliary grid on the back surface of the P-type monocrystalline silicon wafer, printing the silver paste main grid and the silver paste or aluminum paste auxiliary grid on the front surface and the corresponding positions of the laser doping area, and sintering to obtain the P-topcon battery. The deposited passivation layer alumina is used as a doping source to dope the area needing printing metallization by laser, so that the heavily doping of the position is realized, the complex process of high-temperature boron expansion, mask and cleaning is not needed, and the process complexity and cost are greatly reduced.
Description
Technical Field
The application belongs to the technical field of batteries, and particularly relates to a P-topcon battery and a preparation method thereof.
Background
The TOPCON (tunnel oxide passivated contact cell) cell is a tunneling oxide passivation contact cell prepared based on a selective carrier principle, and specifically comprises the steps of preparing an ultrathin oxide layer on a silicon substrate, then depositing doped polysilicon, and forming a passivation structure by the ultrathin oxide layer and the doped polysilicon, so that surface recombination and metal lower contact recombination are effectively reduced. An N-type or P-type topcon cell can be made depending on the type of silicon wafer, which is more cost-advantageous than an N-type silicon wafer. At present, most of used silicon substrates are N-type silicon, and the mass production efficiency of the N-topcon battery prepared by the method can reach 24.8 percent due to the fact that the service life of the N-type silicon is high and boron oxide attenuation does not exist. However, the preparation process of the N-topcon battery is complex (13 steps are taken), the cost is high (3 steps of high temperature and multi-step cleaning steps), and the production yield is affected.
The existing N-type topcon battery has the following disadvantages:
1. multiple process steps, complex flow and higher cost
2. Boron expansion at high temperature, easy warping of the chip, high chip rate and incapability of thinning the chip; the high temperature causes the silicon wafer with higher oxygen content to generate concentric circles, which affects the yield of the battery
3. The wet cleaning process has a plurality of procedures, and the pollution problem easily occurs to influence the yield of the battery
The existing P-type topcon battery has the following disadvantages:
the use of boron diffusion or printing of boron paste to form the full or partial front surface requires high temperatures; the efficiency of directly printing aluminum paste is lower.
Therefore, there is a lack of a P-topcon battery and a method for manufacturing the same that omits the high temperature process of boron diffusion and many cleaning steps on the P-type substrate, simplifies the process flow and reduces the production energy consumption.
Disclosure of Invention
The application aims to solve the technical problems that the existing N-type and P-type topcon batteries are complex in process and high in energy consumption, overcomes the defects and the shortcomings in the prior art, and provides a P-topcon battery and a preparation method thereof.
In order to solve the technical problems, the technical scheme provided by the application is as follows:
the preparation method of the P-topcon battery comprises the following steps:
(1) Polishing the P-type monocrystalline silicon piece;
(2) Tunneling an oxide layer and a polycrystalline silicon layer on the back surface of the P-type monocrystalline silicon wafer, and etching and texturing the front surface of the P-type monocrystalline silicon wafer;
(3) Depositing alumina on the front side of the P-type monocrystalline silicon piece; carrying out laser doping on the front side and plating a passivation layer and/or an antireflection layer on the front side and the back side according to any sequence; the laser doping is performed, and aluminum oxide is utilized to form a patterned p+ doping front surface field;
(4) And printing a silver paste main grid and an auxiliary grid on the back surface of the P-type monocrystalline silicon wafer, printing the silver paste main grid and the silver paste or aluminum paste auxiliary grid on the front surface and the corresponding positions of the laser doping area, and sintering to obtain the P-topcon battery.
Preferably, the P-type monocrystalline silicon piece in step (1) has a resistivity of 3 to 20 Ω×cm, more preferably a resistivity of 7 to 15 Ω×cm.
The TOPCON battery is applied to N-type silicon wafers in mass production at present, and the scheme of P-type silicon wafers with smaller cost and simpler process is not mature.
Preferably, the polishing in step (1) is an alkali polishing, a double-sided polishing treatment, and a single-sided thinning of 1 to 5 μm, more preferably 1 to 3 μm. The alkali polishing adopts one or more of KOH, naOH and TMAH additives.
Preferably, in the step (2), the back tunneling oxide layer and the polysilicon layer are formed by LPCVD, firstly growing a 1-2 nm ultrathin silicon oxide layer at 550-650 ℃, then depositing intrinsic amorphous silicon, and then performing phosphorus diffusion on the back surface to form an n-poly silicon layer.
Preferably, the intrinsic amorphous silicon thickness in step (2) is between 60nm and 200nm, more preferably 80 to 150nm; the n-poly silicon layer is POCl 3 。
Preferably, in the step (2), the back tunneling oxide layer and the polysilicon layer are grown by any one method of PECVD, PEALD, PVD, and then an n-poly silicon layer is formed by annealing.
Preferably, the front etching and texturing in the step (2) specifically includes: by HF/HNO 3 The front surface is subjected to single-sided acid polishing treatment, the back surface PSG is uniformly covered with a water film, one or more of KOH, naOH and TMAH additives are used for texturing, and the size of the front surface texturing pyramid is 0.5-5 mu m, more preferably 1-3 mu m.
Preferably, the front side deposition of alumina in the step (3) is deposition of alumina by adopting an ALD or PEALD mode, and the thickness is between 3nm and 10nm, more preferably between 4 nm and 7nm; the laser doping is to form patterned p+ doping on the silicon wafer by using a front-side plated aluminum oxide film layer as a doping source in a laser doping mode so as to form a front-side field, the metallization region is doped, the non-metallization region does not need to be doped, and the grid line needs to be positioned at the position of laser doping during printing. The laser doped location and area are matched with the electrode pattern, depending on the design of the electrodes, both require a high degree of registration, the printed electrode pattern falls within the laser doped area, and accurate positioning is typically achieved with a high precision camera.
The laser doped region can realize heavy doping, so that the contact resistance between the region and the electrode is lower, and the carrier recombination of the metalized region is reduced.
Preferably, in the step (3), the front and back surfaces are plated with passivation layers and/or antireflection layers: one or more of a silicon nitride film, a silicon oxynitride film and a silicon oxide film are plated on the front side and the back side as a passivation layer and an anti-reflection layer, and the film thickness of the front side and the back side is 50 nm-120 nm, more preferably 60-90 nm; the sintering temperature in the step (4) is 710-800 ℃.
Under the same technical conception, the application also provides a P-topcon battery, which is prepared by adopting the preparation method of the P-topcon battery, and comprises the following steps: the semiconductor device comprises a P-type monocrystalline silicon wafer substrate, a back silicon oxide layer, a polycrystalline silicon layer, an n-poly silicon layer, a p+ layer, an aluminum oxide layer, a front polycrystalline silicon layer and an electrode.
Compared with the prior art, the application has the beneficial effects that:
(1) The deposited passivation layer alumina is used as a doping source to carry out laser doping on the area needing printing metallization, so that the heavy doping of the position is realized, and the doping can be carried out after the alumina deposition process or after the silicon nitride deposition process.
(2) The heavy doping of the front metal area of the p-topcon battery structure can be realized without the complex process of high-temperature boron expansion, mask and cleaning, and the complex process of printing boron paste and cleaning, thereby greatly reducing the complexity and cost of the process.
(3) Compared with an N-Topcon battery and a conventional P-Topcon process path, the method has the advantages of simplicity and fewer steps.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a P-Topcon cell of example 1;
in the figure: 1. a back side silicon oxide layer; 2. a polysilicon layer; 3. an n-poly silicon layer; 4. a p+ layer; 5. an alumina layer; 6. a front side polysilicon layer; 7. an electrode.
Detailed Description
The present application will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments are shown, for the purpose of illustrating the application, but the scope of the application is not limited to the specific embodiments shown.
Unless defined otherwise, all technical and scientific terms used hereinafter have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the scope of the present application.
Unless otherwise specifically indicated, the various raw materials, reagents, instruments, equipment and the like used in the present application are commercially available or may be prepared by existing methods.
Example 1:
the preparation process of the P-topcon battery is as follows:
1. silicon wafer: and a P-type monocrystalline silicon wafer is selected, and the resistivity is 10 omega cm.
2. Rough polishing: performing double-sided alkali polishing treatment by using KOH, naOH or TMAH, and thinning one side by 2 mu m;
3. back tunneling oxide layer preparation + doped polysilicon layer: taking LPCVD as an example, an ultra-thin silicon oxide layer of 1.5nm is grown at 600 deg.C, then intrinsic amorphous silicon (thickness of 120 nm) is deposited, and then phosphorus diffusion is performed on the back surface to form POCl 3 A silicon layer).
4. Front etching: by HF/HNO 3 And (3) carrying out single-sided acid polishing treatment on the front surface, uniformly covering a water film on the back surface PSG, and protecting the back surface tunneling oxide layer +poly structure.
5. Front texturing: the front side is textured with KOH, naOH, or TMAH added with a texturing additive that protects the PSG layer from damage, thereby protecting the backside structure. The size of the front texturing pyramid is 2um.
6. Front side deposition of aluminum oxide: front side ALD or PEALD deposited alumina to a thickness of 5nm.
7. Front laser doping: the aluminum oxide film layer plated on the front surface is used as a doping source, patterned p+ doping is formed on the silicon wafer in a laser doping mode, so that a front surface field is formed, and the position of laser is needed to be aligned during printing.
8. Front and back side plating antireflection layer: the front and back surfaces are plated with silicon nitride film or silicon oxynitride film or silicon oxide or combined film as passivation layer and antireflection layer, and the film thickness of the front and back surfaces is 75nm.
9. Printing and sintering: silver paste is printed on the back surface, silver aluminum paste or silver paste is printed on the front surface and the laser doped region in para position, and the sintering temperature is 750 ℃.
Through electrical performance test, the photoelectric conversion efficiency of the battery prepared in this example was 23.93%, wherein the open circuit voltage was 0.710V, the short circuit current was 18.00A, and the fill factor was 82.48%.
FIG. 1 is a schematic diagram of a P-Topcon cell of example 1; the prepared P-Topcon battery comprises: a P-type monocrystalline silicon wafer substrate, a back silicon oxide layer 1, a polysilicon layer 2, an n-poly silicon layer 3, a p+ layer 4, an aluminum oxide layer 5, a front polysilicon layer 6 and an Ag electrode 7.
Example 2:
a P-topcon battery comprising: the device comprises a P-type monocrystalline silicon wafer substrate, a back silicon oxide layer, a polycrystalline silicon layer, an n-poly silicon layer, a p+ layer, an aluminum oxide layer, a front polycrystalline silicon layer and an Ag/Al electrode.
The preparation process is as follows:
1. silicon wafer: and a P-type monocrystalline silicon wafer is selected, and the resistivity is 10 omega cm.
2. Rough polishing: performing double-sided alkali polishing treatment by using KOH, naOH or TMAH, and thinning one side by 2 mu m;
3. back tunneling oxide layer preparation + doped polysilicon layer: and growing tunneling silicon oxide and n-doped amorphous silicon by utilizing a PECVD/PEALD/PVD mode, and then performing annealing treatment to form an n-poly silicon layer.
4. Front etching: by HF/HNO 3 And (3) carrying out single-sided acid polishing treatment on the front surface, uniformly covering a water film on the back surface PSG, and protecting the back surface tunneling oxide layer +poly structure.
5. Front texturing: the front side is textured with KOH, naOH, or TMAH added with a texturing additive that protects the PSG layer from damage, thereby protecting the backside structure. The size of the front texturing pyramid is 2um.
6. Front side deposition of aluminum oxide: front side ALD or PEALD deposited alumina to a thickness of 5nm. The layer of alumina serves as a passivation layer on the one hand and as a laser doped source layer on the other hand.
7. Front and back side plating antireflection layer: the front and back surfaces are plated with silicon nitride film or silicon oxynitride film or silicon oxide or combined film as passivation layer and antireflection layer, and the film thickness of the front and back surfaces is 75nm.
8. Front laser doping: and forming patterned p+ doping (the metalized region is doped, the non-metalized region is not doped) on the front surface in a laser doping mode so as to form a front surface field, and the grid line needs to be positioned at the laser doping position during printing.
9. Printing and sintering: silver paste is printed on the back, silver aluminum paste or silver paste is printed on the front laser doped region in an alignment mode, front main grids and fine grids are printed separately, and the main grids are silver paste. Sintering temperature is 750 ℃.
Through electrical performance test, the photoelectric conversion efficiency of the battery manufactured in this example was 23.91%, wherein the open circuit voltage was 0.710V, the short circuit current was 17.98A, and the fill factor was 82.36%.
Comparative example 1:
a P-topcon battery comprising: the device comprises a P-type monocrystalline silicon wafer substrate, a back silicon oxide layer, a polycrystalline silicon layer, an n-poly silicon layer, a p+ layer, an aluminum oxide layer, a front polycrystalline silicon layer and an Ag/Al electrode.
The preparation process is as follows:
1. silicon wafer: and a P-type monocrystalline silicon wafer is selected, and the resistivity is 10 omega cm.
2. Rough polishing: performing double-sided alkali polishing treatment by using KOH, naOH or TMAH, and thinning one side by 2 mu m;
3. front texturing: texturing the front surface by KOH, naOH or TMAH added with a texturing additive, wherein the size of a front surface texturing pyramid is 2um;
4. front boron diffusion shallow doping: performing boron diffusion on the textured silicon wafer in a high-temperature mode to form a shallow doped region;
5. front boron diffusion heavy doping: printing boron paste on the front side of the silicon wafer according to the electrode pattern, printing a mask on the rest of the front side, and performing high-temperature treatment to form a heavily doped region;
6. cleaning: by HF/HNO 3 Carrying out single-sided acid polishing treatment on the back surface, and uniformly covering a water film on the front borosilicate glass layer BSG;
7. back tunneling oxide layer preparation + doped polysilicon layer: growing tunneling silicon oxide and n-doped amorphous silicon by utilizing a PECVD/PEALD/PVD mode, and then performing annealing treatment to form an n-poly silicon layer;
8. and (3) secondary cleaning: cleaning the front borosilicate glass layer and the back phosphosilicate glass layer by using HF;
9. front side deposition of aluminum oxide: front side ALD or PEALD mode to deposit alumina with thickness of 5nm;
10. front and back side plating antireflection layer: the front and back surfaces are plated with silicon nitride films or silicon oxynitride films or silicon oxide or combined films as passivation layers and antireflection layers, and the film thickness of the front and back surfaces is 75nm;
11. printing and sintering: silver paste is printed on the back, silver aluminum paste or silver paste is printed on the front laser doped region in an alignment mode, front main grids and fine grids are printed separately, and the main grids are silver paste. Sintering temperature is 750 ℃.
Through an electrical property test, the photoelectric conversion efficiency of the battery manufactured in this comparative example was 23.81%, in which the open circuit voltage was 0.709V, the short circuit current was 17.92A, and the fill factor was 82.6%.
As can be seen from the experimental and performance data of the examples and the comparative examples, the performance of the P-topcon battery obtained by the example of the application is consistent with that of the P-topcon battery prepared by the conventional high-temperature boron expansion process, but the process flow of the application is simpler and more convenient, the complex process of high-temperature boron expansion + mask + cleaning is not needed, the process cost is greatly reduced, and the application has extremely high market value.
Claims (10)
1. The preparation method of the P-topcon battery is characterized by comprising the following steps of:
(1) Polishing the P-type monocrystalline silicon piece;
(2) Tunneling an oxide layer and a polycrystalline silicon layer on the back surface of the P-type monocrystalline silicon wafer, and etching and texturing the front surface of the P-type monocrystalline silicon wafer;
(3) Depositing alumina on the front side of the P-type monocrystalline silicon piece; carrying out laser doping on the front side and plating a passivation layer and/or an antireflection layer on the front side and the back side according to any sequence; the laser doping forms a patterned p+ doped front surface field with alumina;
(4) And printing a silver paste main grid and an auxiliary grid on the back surface of the P-type monocrystalline silicon wafer, printing the silver paste main grid and the silver paste or aluminum paste auxiliary grid on the front surface and the corresponding positions of the laser doping area, and sintering to obtain the P-topcon battery.
2. The method of claim 1, wherein the P-type monocrystalline silicon piece in step (1) has a resistivity of 3-20 Ω cm.
3. The method for manufacturing a P-topcon battery according to claim 1, wherein the polishing in the step (1) is alkali polishing, double-sided polishing treatment, and single-sided thinning by 1 to 5 μm.
4. The method of fabricating a P-topcon cell according to claim 1, wherein the back tunneling oxide layer and the polysilicon layer in step (2) are formed by LPCVD, growing an ultra-thin silicon oxide layer of 1-2 nm at 550-650 ℃, then depositing intrinsic amorphous silicon, and then performing phosphorus diffusion on the back surface to form an n-poly silicon layer.
5. The method of claim 4, wherein the intrinsic amorphous silicon in step (2) has a thickness of 60nm to 200nm, and the n-poly silicon layer is POCl 3 。
6. The method of claim 1, wherein the back tunnel oxide layer and the polysilicon layer in step (2) are grown by any one of PECVD, PEALD, PVD and then annealed to form an n-poly silicon layer.
7. The method for manufacturing a P-topcon battery according to claim 1, wherein the front etching and texturing in the step (2) is specifically: by HF/HNO 3 And (3) carrying out single-sided acid polishing treatment on the front surface, uniformly covering a water film on the back surface PSG, and carrying out texturing by using one or more of KOH, naOH and TMAH additives, wherein the size of the front surface texturing pyramid is 0.5-5 mu m.
8. The method for preparing a P-topcon battery according to claim 1, wherein the front side deposition of alumina in the step (3) is deposition of alumina by ALD or PEALD, and the thickness is between 3nm and 10 nm; the laser doping is to form patterned p+ doping on the silicon wafer by using a front-side plated aluminum oxide film layer as a doping source in a laser doping mode so as to form a front-side field, the metallization region is doped, the non-metallization region does not need to be doped, and the grid line needs to be positioned at the position of laser doping during printing.
9. The method for manufacturing a P-topcon battery according to claim 1, wherein the front and back surfaces of the P-topcon battery in step (3) are plated with passivation layers and/or anti-reflection layers: one or more of a silicon nitride film, a silicon oxynitride film and silicon oxide are plated on the front side and the back side as a passivation layer and an antireflection layer, and the film thickness of the front side and the back side is 50 nm-120 nm; the sintering temperature in the step (4) is 710-800 ℃.
10. A P-topcon battery prepared by the method of any one of claims 1-9, comprising: the semiconductor device comprises a P-type monocrystalline silicon wafer substrate, a back silicon oxide layer, a polycrystalline silicon layer, an n-poly silicon layer, a p+ layer, an aluminum oxide layer, a front polycrystalline silicon layer and an electrode.
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