CN115101621B - A kind of P-topcon battery and its preparation method - Google Patents

Abstract

The application provides a P-topcon battery and a preparation method thereof, wherein the method comprises the following steps: (1) polishing a P-type monocrystalline silicon wafer; (2) Tunneling an oxide layer and a polycrystalline silicon layer on the back surface of the P-type monocrystalline silicon wafer, and etching and texturing the front surface of the P-type monocrystalline silicon wafer; (3) depositing alumina on the front surface of the P-type monocrystalline silicon piece; carrying out laser doping on the front side and plating a passivation layer and/or an antireflection layer on the front side and the back side according to any sequence; the laser doping forms a patterned p+ doped front surface field with alumina; (4) And printing a silver paste main grid and an auxiliary grid on the back surface of the P-type monocrystalline silicon wafer, printing the silver paste main grid and the silver paste or aluminum paste auxiliary grid on the front surface and the corresponding positions of the laser doping area, and sintering to obtain the P-topcon battery. The deposited passivation layer alumina is used as a doping source to dope the area needing printing metallization by laser, so that the heavily doping of the position is realized, the complex process of high-temperature boron expansion, mask and cleaning is not needed, and the process complexity and cost are greatly reduced.

Description

A kind of P-topcon battery and its preparation method

Technical field

The invention belongs to the field of battery technology, and in particular relates to a P-topcon battery and a preparation method thereof.

Background technique

TOPCON (tunnel oxide passivated contact cell) battery is a tunnel oxide passivated contact cell prepared based on the selective carrier principle. The specific method is to prepare an ultra-thin oxide layer on a silicon substrate, and then deposit doped polysilicon. The two together form a passivation structure, effectively reducing surface recombination and under-metal contact recombination. Depending on the type of silicon wafer, N-type or P-type topcon cells can be made. P-type silicon wafers have more cost advantages than n-type silicon wafers. Currently, most of the silicon substrates used are N-type silicon. Since N-type silicon has a long life and no boron-oxygen decay, the mass production efficiency of N-topcon cells prepared by this method can reach ~24.8%. However, the preparation process of N-topcon batteries is complicated (13 steps in total) and the cost is high (3 steps of high temperature and multiple cleaning steps), which affects the production yield.

Existing N-type topcon batteries have the following shortcomings:

1. There are many process steps, the process is complex, and the cost is high

2. When boron expands to high temperatures, the wafer is prone to warping and has a high fragmentation rate, making it impossible to make the wafer thin. The high temperature causes concentric circles to appear on silicon wafers with high oxygen content, which affects the battery yield.

3. There are many wet cleaning processes and it is easy to cause pollution problems that affect the battery yield.

Existing P-type topcon batteries have the following shortcomings:

Using boron diffusion or printing boron paste to form the entire or partial front surface requires high temperatures; direct printing of aluminum paste is more inefficient.

Therefore, there is currently a lack of a p-topcon battery and its preparation method that omits the high-temperature process of boron diffusion and many cleaning steps on a P-type substrate, simplifies the process flow, and reduces production energy consumption.

Contents of the invention

The technical problem to be solved by the present invention is that the existing N-type and P-type topcon batteries have complex processes and high energy consumption. The invention overcomes the shortcomings and defects mentioned in the above background technology and provides a P-topcon battery and a preparation method thereof.

In order to solve the above technical problems, the technical solutions proposed by the present invention are:

A preparation method of P-topcon battery, including the following steps:

(1) Polish the P-type single crystal silicon wafer;

(2) Tunnel the oxide layer and polysilicon layer on the back of the P-type monocrystalline silicon wafer, and etch and texture the front side of the P-type monocrystalline silicon wafer;

(3) Deposit aluminum oxide on the front side of the P-type single crystal silicon wafer; perform laser doping on the front side and plating passivation layer and/or antireflection layer on the front and back sides in any order; the laser doping uses aluminum oxide to form patterning The p+ doping front field;

(4) Print the main grid and sub-grid of silver paste on the back of the P-type monocrystalline silicon wafer, print the main grid of silver paste and the sub-grid of silver paste or aluminum paste on the front and corresponding positions of the laser doped area, and sinter to obtain a P-topcon battery.

Preferably, the resistivity of the P-type single crystal silicon wafer in step (1) is 3 to 20Ω*cm, and more preferably, the resistivity is 7 to 15Ω*cm.

The current mass production of TOPCON batteries in the industry is applied to N-type silicon wafers, and the solution for P-type silicon wafers with lower cost and simpler process is not yet mature. This application is developed for P-type silicon wafers and optimizes P-type silicon wafers. The technical process path and cost of silicon wafers.

Preferably, the polishing in step (1) adopts alkali polishing, double-sided polishing, and one side is thinned by 1 to 5 μm, more preferably 1 to 3 μm. The alkali polishing uses one or more of KOH, NaOH and TMAH additives.

Preferably, the back tunnel oxide layer and polysilicon layer in step (2) adopt the LPCVD method. First, a 1-2nm ultra-thin silicon oxide layer is grown at 550-650°C, and then intrinsic amorphous silicon is deposited, and then the back surface is Phosphorus diffusion is performed to form an n-poly silicon layer.

Preferably, the thickness of intrinsic amorphous silicon in step (2) is between 60 nm and 200 nm, more preferably between 80 and 150 nm; the n-poly silicon layer is POCl ₃ .

Preferably, the back tunnel oxide layer and polysilicon layer in step (2) are grown by any method of PECVD, PEALD, or PVD, and then annealed to form n-polymer. silicon layer.

Preferably, the front-side etching and texturing described in step (2) specifically includes: using HF/HNO ₃ to perform a single-side acid polishing treatment on the front side, evenly covering the back PSG with a water film, and using one of KOH, NaOH and TMAH additives. One or more methods are used for texturing, and the size of the front texturing pyramid is 0.5 to 5 μm, and more preferably 1 to 3 μm.

Preferably, the front-side deposited aluminum oxide in step (3) is deposited by ALD or PEALD, with a thickness between 3nm and 10nm, more preferably 4-7nm; the laser doping is front-side plated aluminum oxide. The film layer is used as a doping source, and patterned p+ doping is formed on the silicon wafer through laser doping to form a front-side field. The metallized area is doped, and the non-metalized area does not need to be doped. Gate lines are required during printing. Align the position of laser doping. The position and area of laser doping match the electrode pattern, which depends on the design of the electrode. The two need to be highly coincident. The printed electrode pattern falls within the laser doping area, and a high-precision camera is usually used to achieve precise positioning.

The laser-doped area can be heavily doped, achieving lower contact resistance between the area and the electrode, and reducing carrier recombination in the metallized area.

Preferably, the front and back surfaces in step (3) are plated with a passivation layer and/or an antireflection layer: the front and back surfaces are plated with one or more of silicon nitride film, silicon oxynitride film, and silicon oxide as passivation layer and anti-reflection layer, the film thickness on the front and back is between 50nm and 120nm, more preferably between 60 and 90nm; the sintering temperature in step (4) is 710°C to 800°C.

Under the same technical concept, the present invention also provides a P-topcon battery, which is prepared using a P-topcon battery preparation method. The battery includes: a P-type monocrystalline silicon wafer substrate, a back silicon oxide layer, and a polycrystalline silicon layer. , n-poly silicon layer, p+ layer, aluminum oxide layer, front polysilicon layer and electrode.

Compared with the prior art, the beneficial effects of the present invention are:

(1) Use the deposited passivation layer aluminum oxide as a doping source to laser dope the area that needs to be printed with metallization to achieve heavy doping at this location. The doping can be done after the aluminum oxide deposition process or after the deposition. After the silicon nitride process.

(2) Heavy doping under the front metal area of the p-topcon cell structure can be achieved without the complex process of high-temperature boron expansion + mask + cleaning and the complex process of printing boron paste + cleaning, greatly reducing process complexity and cost.

(3) Compared with N-Topcon batteries and conventional P-Topcon, the process path is simple and has fewer steps.

Description of the drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are: For some embodiments of the present invention, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of the P-Topcon battery of Embodiment 1;

In the picture: 1. Back silicon oxide layer; 2. Polysilicon layer; 3. n-poly silicon layer; 4. p+ layer; 5. Aluminum oxide layer; 6. Front polysilicon layer; 7. Electrode.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more comprehensively and in detail below with reference to the accompanying drawings and preferred embodiments. However, the protection scope of the present invention is not limited to the following specific embodiments.

Unless otherwise defined, all technical terms used below have the same meanings as commonly understood by those skilled in the art. The technical terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present invention.

Unless otherwise specified, various raw materials, reagents, instruments and equipment used in the present invention can be purchased in the market or prepared by existing methods.

Example 1:

The preparation process of P-topcon battery is as follows:

1. Silicon wafer: Use P-type monocrystalline silicon wafer with a resistivity of 10Ω*cm.

2. Coarse polishing: Use KOH, NaOH or TMAH for double-sided alkali polishing, and reduce the thickness to 2μm on one side;

3. Preparation of back tunnel oxide layer + doped polysilicon layer: Taking LPCVD as an example, first grow an ultra-thin silicon oxide layer of 1.5nm at 600°C, and then deposit intrinsic amorphous silicon (the thickness of intrinsic amorphous silicon is 120nm). Then phosphorus diffusion is performed on the back to form a POCl ₃ silicon layer).

4. Front-side etching: Use HF/HNO ₃ to perform single-side acid polishing treatment on the front side, and evenly cover the back PSG with a water film to protect the back tunnel oxide layer + poly structure.

5. Front texturing: Use KOH, NaOH or TMAH added with texturing additives to texturize the front. This additive can protect the PSG layer from being damaged, thus protecting the back structure. The size of the front texturing pyramid is 2um.

6. Front-side deposition of aluminum oxide: Front-side ALD or PEALD deposition of aluminum oxide with a thickness of 5nm.

7. Front laser doping: The aluminum oxide film layer coated on the front is used as a doping source. Patterned p+ doping is formed on the silicon wafer through laser doping to form a front field. The position of the laser needs to be aligned during printing. .

8. Anti-reflection layer plating on the front and back: The front and back are coated with silicon nitride film or silicon oxynitride film or silicon oxide or a combination film as the passivation layer and anti-reflection layer. The film thickness on the front and back is 75nm.

9. Printing and sintering: Silver paste is printed on the back, silver aluminum paste or silver paste is printed on the front and laser doped area, and the sintering temperature is 750°C.

After electrical performance testing, the photoelectric conversion efficiency of the battery produced in this embodiment was 23.93%, with an open circuit voltage of 0.710V, a short circuit current of 18.00A, and a filling factor of 82.48%.

Figure 1 is a schematic diagram of the P-Topcon battery in Example 1; the prepared P-Topcon battery includes: P-type monocrystalline silicon wafer substrate, back silicon oxide layer 1, polycrystalline silicon layer 2, n-poly silicon layer 3, p+ Layer 4, aluminum oxide layer 5, front polysilicon layer 6 and Ag electrode 7.

Example 2:

A P-topcon battery includes: P-type monocrystalline silicon wafer substrate, back silicon oxide layer, polysilicon layer, n-poly silicon layer, p+ layer, aluminum oxide layer, front polysilicon layer and Ag/Al electrode.

Its preparation process is as follows:

1. Silicon wafer: Use P-type monocrystalline silicon wafer with a resistivity of 10Ω*cm.

2. Coarse polishing: Use KOH, NaOH or TMAH for double-sided alkali polishing, and reduce the thickness to 2μm on one side;

3. Preparation of back tunnel oxide layer + doped polysilicon layer: Use PECVD\PEALD\PVD to grow tunneling silicon oxide and n-doped amorphous silicon, and then perform annealing treatment to form an n-poly silicon layer.

4. Front-side etching: Use HF/HNO ₃ to perform single-side acid polishing treatment on the front side, and evenly cover the back PSG with a water film to protect the back tunnel oxide layer + poly structure.

5. Front texturing: Use KOH, NaOH or TMAH added with texturing additives to texturize the front. This additive can protect the PSG layer from being damaged, thus protecting the back structure. The size of the front texturing pyramid is 2um.

6. Front-side deposition of aluminum oxide: Front-side ALD or PEALD deposition of aluminum oxide with a thickness of 5nm. This layer of aluminum oxide serves on the one hand as a passivation layer and on the other hand as a laser doping source layer.

7. Antireflection layer plating on the front and back: The front and back are coated with silicon nitride film, silicon oxynitride film, silicon oxide or a combination film as the passivation layer and antireflection layer. The film thickness on the front and back is 75nm.

8. Front-side laser doping: Patterned p+ doping is formed on the front-side by laser doping (the metallized area is doped, and the non-metallized area does not need to be doped) to form a front-side field. Gate lines are required during printing. Align the position of laser doping.

9. Printing and sintering: silver paste is printed on the back, silver aluminum paste or silver paste is printed on the laser doped area on the front, main grid and fine grid are printed separately on the front, and main grid silver paste is printed. The sintering temperature is 750℃.

After electrical performance testing, the photoelectric conversion efficiency of the battery produced in this embodiment was 23.91%, with an open circuit voltage of 0.710V, a short circuit current of 17.98A, and a filling factor of 82.36%.

Comparative example 1:

A P-topcon battery includes: P-type monocrystalline silicon wafer substrate, back silicon oxide layer, polysilicon layer, n-poly silicon layer, p+ layer, aluminum oxide layer, front polysilicon layer and Ag/Al electrode.

Its preparation process is as follows:

1. Silicon wafer: Use P-type monocrystalline silicon wafer with a resistivity of 10Ω*cm.

2. Coarse polishing: Use KOH, NaOH or TMAH for double-sided alkali polishing, and reduce the thickness to 2μm on one side;

3. Front texturing: Use KOH, NaOH or TMAH added with texturing additives to texturize the front surface. The size of the front texturing pyramid is 2um;

4. Front-side boron expansion and shallow doping: Boron is diffused on the textured silicon wafer through high temperature to form a shallow doping area;

5. Front-side boron expansion and heavy doping: print boron paste on the front side of the silicon wafer according to the electrode pattern, print masks on the rest of the front side, and process at high temperatures to form a heavily doped area;

6. Cleaning: Use HF/HNO ₃ to perform single-sided acid polishing treatment on the back, and evenly cover the water film on the front borosilicate glass layer BSG;

7. Preparation of back tunnel oxide layer + doped polysilicon layer: Use PECVD\PEALD\PVD to grow tunneling silicon oxide and n-doped amorphous silicon, and then perform annealing treatment to form an n-poly silicon layer;

8. Secondary cleaning: Use HF to clean the front borosilicate glass layer and the back phosphosilicate glass layer;

9. Front-side deposition of aluminum oxide: Front-side ALD or PEALD deposition of aluminum oxide with a thickness of 5nm;

10. Anti-reflection layer plating on the front and back: The front and back are coated with silicon nitride film or silicon oxynitride film or silicon oxide or a combination film as a passivation layer and anti-reflection layer. The film thickness on the front and back is 75nm;

11. Printing and sintering: silver paste is printed on the back, silver aluminum paste or silver paste is printed on the laser doped area on the front, main grid and fine grid are printed separately on the front, and main grid silver paste is printed. The sintering temperature is 750℃.

After electrical performance testing, the photoelectric conversion efficiency of the battery produced in this comparative example was 23.81%, with an open circuit voltage of 0.709V, a short circuit current of 17.92A, and a filling factor of 82.6%.

It can be seen from the experiments and performance data of the Examples and Comparative Examples that the performance of the P-topcon battery obtained in the Examples of the present application is consistent with that of the P-topcon battery prepared by the conventional high-temperature boron expansion process. However, the process of the present application The process is simpler and more convenient, and there is no need for the complex process of high-temperature boron expansion + masking + cleaning, which greatly reduces the process cost and has extremely high market value.

Claims (10)

1. A preparation method of P-topcon battery, characterized in that it includes the following steps: (1) Polish the P-type single crystal silicon wafer; (2) Tunnel the oxide layer and polysilicon layer on the back of the P-type monocrystalline silicon wafer, and etch and texture the front side of the P-type monocrystalline silicon wafer; (3) Deposit aluminum oxide on the front side of the P-type single crystal silicon wafer; perform front-side laser doping and front and back plating with passivation layers and/or anti-reflection layers in any order; the laser doping uses aluminum oxide to form patterned p+ doped front field; (4) Print the main grid and sub-grid of silver paste on the back of the P-type monocrystalline silicon wafer, print the main grid of silver paste and the sub-grid of silver paste or aluminum paste on the front and corresponding positions of the laser doped area, and sinter to obtain a P-topcon battery. 2. The method for preparing a P-topcon battery according to claim 1, wherein the resistivity of the P-type monocrystalline silicon wafer in step (1) is 3 to 20Ω*cm. 3. The preparation method of P-topcon battery according to claim 1, characterized in that the polishing in step (1) adopts alkali polishing, double-sided polishing treatment, and one side is thinned by 1 to 5 μm. 4. The preparation method of P-topcon battery according to claim 1, characterized in that, the back tunnel oxide layer and the polysilicon layer in step (2) adopt the LPCVD method and are first grown at 550-650°C to a thickness of 1-2 nm. An ultra-thin silicon oxide layer is then deposited with intrinsic amorphous silicon, and then phosphorus diffusion is performed on the back to form an n-poly silicon layer. 5. The preparation method of P-topcon battery according to claim 4, characterized in that the thickness of intrinsic amorphous silicon in step (2) is between 60nm and 200nm, and the n-poly silicon layer is POCl ₃ . 6. The preparation method of P-topcon battery according to claim 1, characterized in that, the back tunneling oxide layer and the polysilicon layer in step (2) are grown by any method among PECVD, PEALD and PVD. Silicon oxide and n-doped amorphous silicon are then annealed to form an n-poly silicon layer. 7. The preparation method of P-topcon battery as claimed in claim 1, characterized in that, the front side etching and texturing in step (2) specifically includes: using HF/HNO ₃ to carry out single-sided acid polishing treatment on the front side, The back PSG is evenly covered with a water film, and one or more of KOH, NaOH, and TMAH additives are used for texturing. The size of the texturing pyramid on the front is 0.5 to 5 μm. 8. The preparation method of P-topcon battery according to claim 1, characterized in that the front-side deposition of aluminum oxide in step (3) adopts ALD or PEALD to deposit aluminum oxide, with a thickness of between 3nm and 10nm; The laser doping uses the aluminum oxide film layer plated on the front as the doping source, and forms patterned p+ doping on the silicon wafer through laser doping to form a front field, and the metallized area is doped, and the non-metallic area is doped The laser doped area does not need to be doped, and the gate lines need to be aligned with the laser doping position during printing. 9. The preparation method of P-topcon battery according to claim 1, characterized in that in step (3), the front and back sides are plated with passivation layer and/or anti-reflection layer: the front and back sides are plated with silicon nitride film One or more of silicon oxynitride film and silicon oxide are used as the passivation layer and anti-reflection layer, and the film thickness on the front and back sides is between 50nm and 120nm; the sintering temperature in step (4) is 710°C to 800°C. 10. A P-topcon battery, characterized in that it is prepared by the preparation method according to any one of claims 1 to 9, and the battery includes: a P-type single crystal silicon wafer substrate, a back silicon oxide layer, Polysilicon layer, n-poly silicon layer, p+ layer, aluminum oxide layer, front polysilicon layer and electrode.