CN115132884B - Manufacturing method of heterojunction solar cell - Google Patents
Manufacturing method of heterojunction solar cell Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
- H01L31/077—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type the devices comprising monocrystalline or polycrystalline materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention belongs to the technical field of solar cells, and relates to a manufacturing method of a heterojunction solar cell, which comprises the following steps of A, forming a tunneling oxide layer on the surface of a semiconductor substrate; b, forming an N-type polycrystalline silicon layer on the tunneling oxide layer; c, forming a mask layer on the N-type polycrystalline silicon layer of the first main surface of the semiconductor substrate; d, performing texturing cleaning on the second main surface of the semiconductor substrate, and then removing the mask layer; e, forming a second intrinsic amorphous silicon layer on the second main surface of the semiconductor substrate; and F, forming a P-type oxygen-doped microcrystalline silicon layer on the second intrinsic amorphous silicon layer. The invention aims to provide a manufacturing method of a heterojunction solar cell, which has a simple process, keeps the advantages of high conductivity of an N-type polycrystalline silicon layer and low equipment investment cost, and also keeps the technical characteristics of good passivation and high open-circuit voltage of a heterojunction.
Description
Technical Field
The invention belongs to the technical field of solar cells, and relates to a manufacturing method of a heterojunction solar cell.
Background
The heterojunction solar cell is more and more favored by the photovoltaic industry because of having the advantages of high conversion efficiency, low process temperature, high stability, low attenuation rate and the like, and is the future development direction of the high conversion efficiency solar cell.
The heterojunction technology has simple process flow, higher conversion efficiency and higher comprehensive generated energy, the attenuation speed of the heterojunction technology is far lower than that of a PERC battery, and the heterojunction technology has larger development potential, but the used plate type PECVD coating equipment of amorphous silicon or microcrystalline silicon is relatively expensive, the comprehensive cost of the equipment does not have larger advantage than that of the PERC battery, the production technology needs to be improved, the investment of equipment fixed assets is further reduced, and the purpose that the comprehensive investment has larger market competitiveness is achieved.
Disclosure of Invention
The invention aims to provide a manufacturing method of a heterojunction solar cell, which has a simple process, keeps the advantages of high conductivity of an N-type polycrystalline silicon layer and low equipment investment cost, and also keeps the technical characteristics of good passivation and high open-circuit voltage of a heterojunction.
The purpose of the invention is realized by the following technical scheme:
a method for manufacturing a heterojunction solar cell comprises the following steps,
a, forming a tunneling oxide layer on the surface of a semiconductor substrate;
b, forming an N-type polycrystalline silicon layer on the tunneling oxide layer;
c, forming a mask layer on the N-type polycrystalline silicon layer of the first main surface of the semiconductor substrate;
d, performing texturing cleaning on the second main surface of the semiconductor substrate, and then removing the mask layer;
e, forming a second intrinsic amorphous silicon layer on the second main surface of the semiconductor substrate;
and F, forming a P-type oxygen-doped microcrystalline silicon layer on the second intrinsic amorphous silicon layer.
Compared with the prior art, the invention has the advantages that:
1. the TOPCON technology consisting of the tunneling oxide layer and the N-type polycrystalline silicon layer has the characteristics of good passivation effect and good conductivity, not only ensures the open-circuit voltage of the battery, but also promotes the filling factor of the battery;
2. the deposition of the silicon nitride protective layer not only prevents the N-type polycrystalline silicon layer from being corroded by solution in the texturing solution, but also plays a role in annealing and hydrogen injection in the process, and further improves the passivation effect of the N-type polycrystalline silicon layer;
3. the introduced process achieves the effect of single-side texturing (polishing), and simultaneously naturally eliminates the plating winding generated in the preparation process of the first semiconductor layer, thereby avoiding the main factors of pure TOPCON technical yield fluctuation and complex process;
4. according to the invention, the silicon nitride protective layer on the back of the silicon wafer is not reserved in the final structure and is replaced by the transparent conductive film layer, so that damage caused by laser ablation or slurry high-temperature reaction is avoided, and the bonding degree with a subsequent heterojunction manufacturing process is good;
5. the P-type oxygen-doped microcrystalline silicon layer is adopted, so that the optical energy gap is widened while the conductivity is ensured, and the defect that the amorphous P layer is serious in light absorption is overcome;
6. the tunneling oxide layer and the N-type polycrystalline silicon layer replace an amorphous N layer or a microcrystalline N layer of the traditional heterojunction, so that the equipment investment of the flat-plate PECVD is reduced, and the total cost of heterojunction equipment can be greatly reduced.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of a high efficiency heterojunction solar cell of the invention;
FIG. 2 is a schematic cross-sectional view of a silicon wafer after double side polishing and cleaning in an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a silicon wafer with a tunneling oxide layer and a first intrinsic polysilicon layer formed thereon in sequence according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a silicon wafer after high temperature diffusion to convert the first intrinsic polycrystalline layer into an N-type polycrystalline silicon layer and form a phosphosilicate glass layer on the surface thereof according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a silicon wafer with a phosphorosilicate glass layer removed from a surface thereof according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view after depositing a silicon nitride protective layer on the backside of a silicon wafer in an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of a pyramidal texture formed on the front side of a silicon wafer by texturing and cleaning in an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of a silicon wafer after removal of a silicon nitride protective layer on the backside of the silicon wafer in an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view of a silicon wafer according to an embodiment of the present invention after a second intrinsic amorphous silicon layer and a P-type oxygen-doped microcrystalline silicon layer are sequentially deposited on the front surface of the silicon wafer;
FIG. 10 is a schematic cross-sectional view after depositing a transparent conductive layer on the front and back surfaces of a silicon wafer in an embodiment of the present invention;
fig. 11 is a schematic cross-sectional view after forming metal gate line electrodes on the front and back sides of a silicon wafer in an embodiment of the present invention;
figure 12 is a flow chart of the fabrication of a high efficiency heterojunction solar cell of the present invention;
fig. 13 is a schematic structural diagram of an embodiment of the high efficiency heterojunction solar cell of the invention.
Description of reference numerals: 1. the solar cell comprises a silicon wafer, 2 parts of a tunneling oxide layer, 3 parts of a first intrinsic polycrystalline silicon layer, 4 parts of an N-type polycrystalline silicon layer, 5 parts of a phosphorosilicate glass layer, 6 parts of a silicon nitride protective layer, 7 parts of a second intrinsic amorphous silicon layer, 8 parts of a P-type oxygen-doped microcrystalline silicon layer, 81 parts of a first non-oxygen-containing microcrystalline layer, 82 parts of an oxygen-containing microcrystalline layer, 83 parts of a second non-oxygen-containing microcrystalline layer, 9 parts of a transparent conducting layer, 10 parts of a metal grid line electrode.
Detailed Description
A method for manufacturing a heterojunction solar cell comprises the following steps,
a, forming a tunneling oxide layer on the surface of a semiconductor substrate;
b, forming an N-type polycrystalline silicon layer on the tunneling oxide layer;
c, forming a mask layer on the N-type polycrystalline silicon layer of the first main surface of the semiconductor substrate;
d, performing texturing cleaning on the second main surface of the semiconductor substrate, and then removing the mask layer;
e, forming a second intrinsic amorphous silicon layer on the second main surface of the semiconductor substrate;
and F, forming a P-type oxygen-doped microcrystalline silicon layer on the second intrinsic amorphous silicon layer.
It also comprises the following steps of,
g, forming a first conductive film layer on the N-type polycrystalline silicon layer, and forming a second conductive film layer on the P-type oxygen-doped microcrystalline silicon layer;
and H, forming a first metal electrode on the first conductive film layer, and forming a second metal electrode on the second conductive film layer.
And polishing and cleaning before the step A, specifically polishing the semiconductor substrate for 1-15min by using an alkaline solution with the temperature of 65-90 ℃, controlling the removal thickness to be 1-20um, and cleaning by using a weak alkaline solution and an acidic solution.
The specific method of the step A is to form a tunneling oxide layer on the surface of the semiconductor substrate by adopting a nitric acid oxidation process, an ozone oxidation process, a vacuum plasma-assisted oxidation process or a thermal oxidation process.
In the step A, the thermal oxidation process is to introduce oxygen for oxidation at 550-650 ℃, mix oxygen and nitrogen for oxidation or utilize atmospheric oxygen for oxidation.
Forming a first intrinsic polycrystalline silicon layer on the tunneling oxide layer, carrying out phosphorus doping on the first intrinsic polycrystalline silicon layer by adopting a diffusion annealing process to form an N-type polycrystalline silicon layer and a phosphorosilicate glass layer, and then removing the phosphorosilicate glass layer by using a fluorine-containing acidic solution; or, introducing a phosphorus source in the atmosphere by adopting an LPCVD (low pressure chemical vapor deposition) process, and carrying out in-situ doping growth to form the N-type polycrystalline silicon layer.
In the step B, the first intrinsic polycrystalline silicon layer is obtained by growing by adopting an LPCVD (low pressure chemical vapor deposition) process, or is obtained by adopting a PECVD (plasma enhanced chemical vapor deposition) process to prepare an amorphous silicon layer and a microcrystalline silicon layer and then carrying out high-temperature annealing, or is obtained by adopting a PVD (physical vapor deposition) sputtering silicon target to prepare a silicon thin film and then carrying out high-temperature annealing.
In a preferable scheme, the specific method of the step A and the step B is that the semiconductor substrate is placed in a tubular LPCVD equipment, and is thermally oxidized for 30min at 550-650 ℃ to form a tunneling oxide layer; then vacuumizing, introducing reaction gas to grow the first intrinsic polycrystalline silicon layer, controlling the growth temperature to be 550-650 ℃, controlling the air pressure to be 5-10000pa, and controlling the thickness of the grown first intrinsic polycrystalline silicon layer to be 20-300nm; and then carrying out phosphorus doping on the first intrinsic polycrystalline silicon layer by adopting a diffusion annealing process to form an N-type polycrystalline silicon layer and a phosphosilicate glass layer, and then removing the phosphosilicate glass layer by using a fluorine-containing acidic solution.
And the diffusion annealing process in the step B is to dope boron into the first intrinsic polycrystalline silicon layer at the diffusion temperature of 780-950 ℃, wherein the sheet resistance is 20-200 omega/\9633afterdiffusion.
The specific method of the step C is to deposit at least one of silicon nitride, silicon oxynitride and silicon oxide on the N-type polycrystalline silicon layer by using a plasma chemical vapor deposition or high-temperature chemical vapor deposition technology to form a mask layer.
The thickness of the mask layer is 30-150nm.
And D, forming a pyramid suede on the second main surface of the semiconductor substrate by etching and cleaning, and removing the mask layer by using a fluorine-containing acidic solution.
The thickness of the tunneling oxide layer is 1-2nm; the thickness of the N-type polycrystalline silicon layer is 20-300nm; the thickness of the P-type oxygen-doped microcrystalline silicon layer is 5-25nm.
And the specific method of the step F is to form the P-type oxygen-doped microcrystalline silicon layer formed by overlapping more than one oxygen-containing microcrystalline layers and more than one non-oxygen-containing microcrystalline layers by adopting a plasma enhanced chemical vapor deposition technology or a hot filament chemical vapor deposition technology. In a preferred embodiment, a first non-oxygen-containing microcrystalline layer, an oxygen-containing microcrystalline layer, and a second non-oxygen-containing microcrystalline layer are sequentially deposited on the second intrinsic amorphous silicon layer.
In the step F, each film layer of the P-type oxygen-doped microcrystalline silicon layer is deposited by adopting a process mode of increasing the ratio of P-type doping gas to silane stage by stage respectively.
The invention is described in detail below with reference to the drawings and examples:
fig. 2 to 10 are schematic diagrams illustrating a method for fabricating a heterojunction solar cell according to an embodiment of the present invention.
A manufacturing method of a heterojunction solar cell comprises the following specific steps:
(1) The method comprises the following steps of carrying out double-sided polishing on an n-type monocrystalline or ingot silicon wafer 1, removing a wire-electrode cutting damage layer on the surface of the silicon wafer by using an alkaline solution, wherein the alkaline solution can be potassium hydroxide, sodium hydroxide or a mixed solution of the potassium hydroxide and the sodium hydroxide, the reaction temperature of the alkaline solution is generally 65-90 ℃, the reaction time is 1-15min, the single-sided removal thickness is controlled to be 1-20 mu m, and then carrying out standard RCA cleaning to remove the alkaline solution remained on the surface of the silicon wafer (as shown in figure 2).
(2) Oxidizing the surface of the silicon wafer 1 after double-side polishing, sequentially forming a tunneling oxide layer 2 and growing a first intrinsic polycrystalline silicon layer 3 (as shown in fig. 3), wherein the surface oxidation can be performed by nitric acid solution oxidation, ozone oxidation or thermal oxidation, preferably, the invention forms the tunneling oxide layer 2 with the thickness of 1.2-2.0nm by thermal oxidation for 30min at 550-650 ℃ in a tubular LPCVD equipment, and the tunneling oxide layer is an ultrathin silicon oxide layer; the silicon oxide film can also be formed by vacuum plasma-assisted oxidation; the formation of the first intrinsic polysilicon layer 3 and the formation of the tunnel oxide layer 2 are performed in the same tube type LPCVD, preferably, after thermal oxidation, gas is evacuated, and gas such as silane is introduced to perform the growth of the first intrinsic polysilicon layer 3, the growth temperature is controlled to be 550-650 ℃, the gas pressure is controlled to be 5-10000pa, and the thickness of the first intrinsic polysilicon layer 3 can be 20-300nm. The first intrinsic polysilicon layer may also be deposited by Plasma Enhanced CVD (PECVD) in combination with a subsequent high temperature anneal. The first intrinsic polycrystalline silicon layer can also be used for preparing a film by sputtering a silicon target material through physical vapor deposition, and then polycrystalline silicon is formed through a subsequent high-temperature annealing mode.
(3) And (3) performing high-temperature diffusion on the silicon wafer with the oxidized and grown polysilicon film to perform phosphorus doping on the first intrinsic polysilicon layer 3 to form an N-type polysilicon layer 4 (as shown in figure 4), wherein the diffusion temperature is 780-950 ℃, and the sheet resistance of the silicon wafer after diffusion is 20-200 omega/\9633. The N-type doping of the polysilicon may also be performed by in-situ doping (i.e., introducing a gas containing a phosphorus source into the atmosphere of the polysilicon preparation gas). By adopting the in-situ doping, the subsequent furnace tube type PSG glass high-temperature diffusion can be avoided.
(4) The phosphosilicate glass layer 5 (phosphosilicate glass layer, PSG) formed on the surface of the silicon wafer 1 after high temperature diffusion is removed (see fig. 5), and the cleaning solution used for the removal is a chemical solution containing fluoride ions (e.g., a diluted hydrofluoric acid or fluorine-containing acidic solution such as BOE solution). If hydrofluoric acid solution is adopted, the mass percent of HF acid is 0.5-8%, the treatment time of the silicon wafer in the HF acid solution is 1-6 minutes, and the treatment temperature is 20-30 ℃.
(5) A silicon nitride protective layer 6 (i.e., a mask layer) is deposited on the back side of the silicon wafer 1 as described above (see fig. 6), wherein the silicon nitride protective layer has a property of being relatively strong against corrosion by an alkaline solution and can resist alkaline corrosion in a texturing solution, preferably wherein the silicon nitride layer has a thickness of 700 a-2000 a and the silicon nitride layer can be formed by a thin film formation method such as a sputtering method or a CVD method, preferably by a PECVD method in this embodiment.
(6) The method comprises the following steps of (1) performing single-side texturing on the silicon wafer (as shown in figure 7), preparing a texturing additive by using an alkali liquor, and texturing the silicon wafer, wherein a silicon nitride protective layer 6 is arranged on the back side of the silicon wafer, so that a pyramid textured surface is formed on the front side of the silicon wafer after a tunneling oxide layer 2 and a first intrinsic polycrystalline silicon layer on the front side of the silicon wafer are removed in a solution, wherein the texturing solution is a mixed solution of potassium hydroxide, the texturing additive and water, wherein the mass percentage of the potassium hydroxide is 1-5%, and the mass percentage of the texturing additive is 0.5-1%. The texturing time is 8-30 minutes, and the texturing temperature is 65-85 ℃.
(7) Removing the silicon nitride protective layer 6 (as shown in fig. 8) on the back surface of the silicon wafer, wherein the solution used for removing the protective layer is a chemical solution (such as diluted hydrofluoric acid or BOE solution) containing fluorine ions, and the removal time is determined according to the corrosion resistance of the silicon nitride;
(8) Depositing a second intrinsic amorphous silicon layer 7 and a P-type oxygen-doped microcrystalline silicon layer 8 on the pyramid texture surface of the front side of the silicon wafer in sequence (as shown in figure 9); the second intrinsic amorphous silicon layer is formed by a PECVD (plasma enhanced chemical vapor deposition) method, the deposition temperature is 150-300 ℃, mixed gas of silane, hydrogen or carbon dioxide is introduced into the reaction cavity, wherein the molar content of the silane is 5-100%, and the thickness of the second intrinsic amorphous silicon layer is 3-11nm; and depositing the P-type oxygen-doped microcrystalline silicon layer by adopting a PECVD (plasma enhanced chemical vapor deposition) method, and introducing silane, hydrogen, carbon dioxide and diborane doping gas for deposition, wherein the deposition thickness is 5-25nm.
(9) Depositing a transparent conductive layer 9 (i.e. a first conductive film layer and a second conductive film layer) on the front and back surfaces of the silicon wafer (see fig. 10), wherein the transparent conductive layer 9 is typically a transparent conductive oxide layer, and the transparent conductive layer 9 may be an indium oxide film layer containing one or more different metal dopants (e.g. tin, tungsten, titanium, etc.), such as ITO, IWO, ITiO, etc.; or zinc oxide film layer doped with one or more different metals (such as aluminum, indium, gallium, etc.), such as AZO, GZO, IZO, IGZO, etc. Preferably, ITO (namely an indium oxide film layer doped with tin) is used, the ITO layer is generally deposited by adopting a PVD (physical vapor deposition) mode, the transmittance of the film layer is controlled to be between 88 and 99 percent, the square resistance is 30 to 400 omega/\ 9633, and the film thickness is 15 to 150nm.
(10) Metal gate line electrodes 10 (i.e., a first metal electrode and a second metal electrode) are formed on the front and back surfaces of the silicon wafer (see fig. 11), so as to facilitate subsequent IV testing.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
The above table shows the process parameters of each stage of the P-type oxygen-doped microcrystalline silicon layer prepared by PECVD, the prepared P-type oxygen-doped microcrystalline silicon layer comprises three stages P1, P2 and P3, and the first non-oxygen-containing microcrystalline layer 81, the oxygen-containing microcrystalline layer 82 and the second non-oxygen-containing microcrystalline layer 83 as shown in FIG. 13 are formed correspondingly. In a preferred scheme, each film layer of the P-type oxygen-doped microcrystalline silicon layer is deposited by adopting a process mode of increasing the ratio of P-type doping gas to silane stage by stage, wherein the ratio of the P-type doping gas to the silane is increased from 1.
The table above is a typical electrical comparison a for three photovoltaic cell technologies: topocon technique, B: heterojunction technology, C: the invention relates to a mixed passivation technology.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A manufacturing method of a heterojunction solar cell is characterized in that: which comprises the following steps of,
a, forming a tunneling oxide layer on the surface of a semiconductor substrate;
b, forming an N-type polycrystalline silicon layer on the tunneling oxide layer;
c, forming a mask layer on the N-type polycrystalline silicon layer of the first main surface of the semiconductor substrate;
d, performing texturing cleaning on the second main surface of the semiconductor substrate, and then removing the mask layer;
e, forming a second intrinsic amorphous silicon layer on the second main surface of the semiconductor substrate;
f, forming a P-type oxygen-doped microcrystalline silicon layer on the second intrinsic amorphous silicon layer;
g, forming a first conductive film layer on the N-type polycrystalline silicon layer and forming a second conductive film layer on the P-type oxygen-doped microcrystalline silicon layer;
and H, forming a first metal electrode on the first conductive film layer, and forming a second metal electrode on the second conductive film layer.
2. The method of fabricating a heterojunction solar cell of claim 1, wherein: forming a first intrinsic polycrystalline silicon layer on the tunneling oxide layer, carrying out phosphorus doping on the first intrinsic polycrystalline silicon layer by adopting a diffusion annealing process to form an N-type polycrystalline silicon layer and a phosphorosilicate glass layer, and then removing the phosphorosilicate glass layer by using a fluorine-containing acidic solution; or, a phosphorus source is introduced into the atmosphere by adopting an LPCVD (low pressure chemical vapor deposition) process, and in-situ doping growth is carried out to form an N-type polycrystalline silicon layer.
3. The method of fabricating a heterojunction solar cell of claim 2, wherein: in the step B, the first intrinsic polycrystalline silicon layer is obtained by growing by adopting an LPCVD (low pressure chemical vapor deposition) process, or is obtained by adopting a PECVD (plasma enhanced chemical vapor deposition) process to prepare an amorphous silicon layer and a microcrystalline silicon layer and then carrying out high-temperature annealing, or is obtained by adopting a PVD (physical vapor deposition) sputtering silicon target to prepare a silicon thin film and then carrying out high-temperature annealing.
4. The method of fabricating a heterojunction solar cell of claim 1, wherein: the specific method of the step C is to deposit at least one of silicon nitride, silicon oxynitride and silicon oxide on the N-type polycrystalline silicon layer by using a plasma chemical vapor deposition or high-temperature chemical vapor deposition technology to form a mask layer.
5. The method of fabricating a heterojunction solar cell of claim 4, wherein: the thickness of the mask layer is 30-150nm.
6. The method of fabricating a heterojunction solar cell of claim 1, wherein: and D, forming a pyramid suede on the second main surface of the semiconductor substrate through wool making and cleaning, and removing the mask layer through a fluorine-containing acidic solution.
7. The method of fabricating a heterojunction solar cell of claim 1, wherein: and the specific method of the step F is to form the P-type oxygen-doped microcrystalline silicon layer formed by overlapping more than one oxygen-containing microcrystalline layer and more than one non-oxygen-containing microcrystalline layer by adopting a plasma enhanced chemical vapor deposition technology or a hot filament chemical vapor deposition technology.
8. The method of claim 7, wherein: in the step F, each film layer of the P-type oxygen-doped microcrystalline silicon layer is deposited by adopting a process mode of increasing the ratio of P-type doping gas to silane stage by stage respectively.
9. The method of fabricating a heterojunction solar cell of any of claims 1 to 8, wherein: the specific method of the step A and the step B comprises the steps of putting a semiconductor substrate into a tubular LPCVD device, and carrying out thermal oxidation for 30min at 550-650 ℃ to form a tunneling oxide layer; then vacuumizing, introducing reaction gas to grow the first intrinsic polycrystalline silicon layer, controlling the growth temperature to be 550-650 ℃, controlling the air pressure to be 5-10000pa, and controlling the thickness of the grown first intrinsic polycrystalline silicon layer to be 20-300nm; and then carrying out phosphorus doping on the first intrinsic polycrystalline silicon layer by adopting a diffusion annealing process to form an N-type polycrystalline silicon layer and a phosphorosilicate glass layer, and then removing the phosphorosilicate glass layer by using a fluorine-containing acidic solution.
10. The method of fabricating a heterojunction solar cell of claim 9, wherein: the thickness of the tunneling oxide layer is 1-2nm; the thickness of the N-type polycrystalline silicon layer is 20-300nm; the thickness of the P-type oxygen-doped microcrystalline silicon layer is 5-25nm.
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