CN218160392U - Solar cell - Google Patents
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- CN218160392U CN218160392U CN202222554518.2U CN202222554518U CN218160392U CN 218160392 U CN218160392 U CN 218160392U CN 202222554518 U CN202222554518 U CN 202222554518U CN 218160392 U CN218160392 U CN 218160392U
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Abstract
The utility model provides a solar cell, include: a silicon wafer; the front side of the silicon wafer is sequentially provided with a borosilicate glass layer and a front passivation layer; the back of the silicon chip is sequentially provided with a tunneling oxidation layer, a polycrystalline silicon layer, an amorphous silicon layer and a back passivation layer. Compared with the prior art, the utility model discloses an ultra-thin oxide layer and polycrystalline silicon layer constitute TOPCon structure jointly, and this structure makes many son electron tunneling get into the polycrystalline silicon layer, blocks few son hole recombination simultaneously, realizes that the electron is at the horizontal transmission of polycrystalline silicon layer and is collected, has greatly reduced metal contact recombination current, has promoted the open circuit voltage and the short-circuit current of battery; meanwhile, unsaturated dangling bonds between the doped polycrystalline silicon layer and the passivation layer are reduced, the passivation effect can be effectively improved, and the conversion efficiency of the battery is improved.
Description
Technical Field
The utility model belongs to the technical field of solar cell, especially, relate to a solar cell.
Background
Solar cells are receiving attention because they convert solar energy into electric energy through photoelectric conversion and are used directly by people. Solar cells can be classified into three types according to their development and the light absorbing layer materials used. The first type is a silicon-based solar cell, which comprises a monocrystalline silicon, a polycrystalline silicon solar cell, an amorphous silicon thin-film solar cell and a silicon laminated solar cell; the second type is a compound solar cell, including solar cells of Copper Indium Gallium Selenide (CIGS), cadmium telluride (CdTe), gallium arsenide (GaAs), perovskite, and the like; the third type is a novel solar cell including a dye-sensitized solar cell, an organic solar cell, a quantum dot solar cell, and the like.
However, in the preparation process of the solar cell, a polycrystalline silicon layer and a back passivation layer are respectively deposited and formed in two different devices, so that a large number of unsaturated dangling bonds are left in a medium layer fusion area; moreover, the preparation of the doped polysilicon layer at present has the following problems: (1) The prepared doped polycrystalline silicon layer can be wound and plated to the front surface, the appearance of the front surface of the silicon chip can be influenced if the doped polycrystalline silicon layer is severe, and the electrical property of a battery can be influenced even if the doped polycrystalline silicon layer is severe; (2) The prepared doped polysilicon layer is thicker, generally 50-150 nm, and the optical parasitic absorption effect is more practical and more obvious along with the increase of the thickness, so that the short-circuit current of the battery can be reduced, and the conversion efficiency of the battery is reduced.
SUMMERY OF THE UTILITY MODEL
In view of this, the to-be-solved technical problem of the present invention is to provide a solar cell, which can effectively improve the passivation effect and improve the battery conversion efficiency by suspending unsaturated bonds between the doped polysilicon layer and the passivation layer.
The utility model provides a preparation method of solar cell, including following step:
s1) carrying out double-sided texturing on the surface of an N-type silicon wafer;
s2) carrying out boron diffusion treatment on the front side of the silicon wafer subjected to double-sided texturing to form a boron diffusion layer and a borosilicate glass layer;
s3) carrying out back etching on the silicon wafer subjected to boron diffusion treatment;
s4) growing a tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the back of the silicon wafer with the etched back by chemical vapor deposition in sequence, and then carrying out high-temperature annealing treatment;
s5) removing the polycrystalline silicon layer wound and plated on the front side and the phosphorosilicate glass layer on the back side;
s6) preparing a passivation layer on the front side and/or the back side of the silicon wafer;
s7) preparing an electrode.
Preferably, the step S1) is specifically to perform double-sided texturing on the surface of the N-type silicon wafer by using a strong alkaline solution; the temperature of the double-sided texturing is 70-90 ℃; the time for double-sided texturing is 5-10 min.
Preferably, the boron source used for the boron diffusion treatment in the step S2) is a boron halide; the temperature of the boron diffusion treatment is 800-860 ℃; the flow rate of nitrogen during the boron diffusion treatment is 650-1050 sccm; the oxygen flow is 600-900 sccm; the time of the boron diffusion treatment is 14-20 min.
Preferably, the back etching in the step S3) adopts a mixed solution of hydrofluoric acid and nitric acid; the mass concentration of the hydrofluoric acid is 40-54%; the mass concentration of the nitric acid is 60-65%; the volume ratio of the hydrofluoric acid to the nitric acid is 1 (2-5); the back etching temperature is 13-20 ℃; the back etching time is 2-4 min.
Preferably, the thickness of the tunneling oxide layer is 1-2 nm; growing a silicon source of a tunneling oxide layer on the back surface of the silicon wafer after back surface etching by using chemical vapor deposition, wherein the silicon source is silane; the flow ratio of the silicon source to the carrier gas is 1 (2-2.5); the time for growing the tunneling oxide layer is 20-30 min.
Preferably, the thickness of the amorphous silicon layer is 100-200 nm; the phosphorus source for depositing the phosphorus-doped amorphous silicon layer is phosphorus oxychloride; the temperature for depositing the amorphous silicon layer doped with phosphorus is 750-850 ℃; the time for depositing the phosphorus-doped amorphous silicon layer is 30-65 min; the flow ratio of the silicon source, the phosphorus source and the carrier is (0.5-1): 1 (10-15) when the phosphorus-doped amorphous silicon layer is deposited.
Preferably, the temperature of the high-temperature annealing treatment is 830-880 ℃; the high-temperature annealing treatment is carried out under the condition of introducing a phosphorus source; the flow ratio of the carrier gas carrying the phosphorus source to the carrier gas is 1 (1.9-3); the proportion of the phosphorus source in the carrier carrying the phosphorus source is 1 (6-10); the pressure of the high-temperature annealing treatment is 0.5-2 mbar; the time of the high-temperature annealing treatment is 20-30 min.
Preferably, the polycrystalline silicon layer which is plated around the front surface in the step S5) is removed and cleaned by using a mixed solution of an additive and a strong alkaline solution; the mass ratio of the additive to the strong alkaline solution is 1 (4-8); the additive is selected from PR21; the mass concentration of the strong alkaline solution is 40-50%; the cleaning temperature is 75-85 ℃; the cleaning time is 5-15 min.
Preferably, the phosphorosilicate glass layer removed from the back surface in the step S5) is cleaned by using 45% -50% hydrofluoric acid.
The utility model also provides a solar cell of above-mentioned preparation method preparation.
The utility model provides a solar cell, include: a silicon wafer; the front side of the silicon wafer is sequentially provided with a borosilicate glass layer and a front passivation layer; the back of the silicon chip is sequentially provided with a tunneling oxide layer, a polycrystalline silicon layer, an amorphous silicon layer and a back passivation layer. Compared with the prior art, the utility model discloses an ultra-thin oxide layer and polycrystalline silicon layer constitute TOPCon structure jointly, and this structure makes many son electron tunneling get into the polycrystalline silicon layer, blocks few son hole recombination simultaneously, realizes that the electron is at the horizontal transmission of polycrystalline silicon layer and is collected, has greatly reduced metal contact recombination current, has promoted the open circuit voltage and the short-circuit current of battery; meanwhile, unsaturated dangling bonds between the doped polycrystalline silicon layer and the passivation layer are reduced, the passivation effect can be effectively improved, and the conversion efficiency of the battery is improved.
Drawings
Fig. 1 is a schematic structural diagram of a solar cell provided by the present invention;
fig. 2 is a schematic view of a manufacturing process of a solar cell according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The utility model provides a solar cell, include: a silicon wafer; the front side of the silicon wafer is sequentially provided with a borosilicate glass layer and a front passivation layer; the back of the silicon chip is sequentially provided with a tunneling oxide layer, a polycrystalline silicon layer, an amorphous silicon layer and a back passivation layer.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a solar cell provided by the present invention, wherein 1 is a silicon wafer after texturing, 2 is a borosilicate glass layer, 41 is a tunneling oxide layer, 42 is an amorphous silicon layer, 61 is an alumina layer, 62 is a silicon nitride layer, 63 is a silicon nitride layer, 71 is a front electrode, and 72 is a back electrode.
The solar cell provided by the utility model takes the silicon wafer as the substrate, preferably the silicon wafer made with wool as the substrate; the silicon wafer is a silicon wafer known to those skilled in the art, and is not particularly limited, and an N-type silicon wafer is preferred in the present invention.
A borosilicate glass layer is arranged on the front side of the silicon wafer; the thickness of the borosilicate glass layer is preferably 100 to 150nm.
A front passivation layer is arranged on the borosilicate glass layer; in the present invention, the front passivation layer preferably includes an aluminum oxide layer and a silicon nitride layer; the thickness of the aluminum oxide layer is preferably 1-10 nm; the thickness of the silicon nitride layer is preferably 75-90 nm; the refractive index of the silicon nitride layer is 2-2.2.
In the utility model, the front side of the silicon wafer is preferably provided with a front electrode; the front electrode is in ohmic contact with the borosilicate glass layer; the front electrode is preferably a silver paste electrode.
The back of the silicon wafer is preferably provided with a tunneling oxide layer; the tunneling oxide layer is an ultrathin silicon oxide layer; the thickness of the tunneling oxide layer is preferably 1-2 nm.
A polysilicon layer is arranged on the back surface of the tunneling oxide layer; in the utility model, the polycrystalline silicon layer is formed by high-temperature annealing of a phosphorus-doped amorphous silicon layer; the thickness of the polysilicon layer is preferably 100 to 150nm, more preferably 100 to 140nm, still more preferably 105 to 130nm, and most preferably 105 to 120nm.
An amorphous silicon layer is arranged on the back of the polycrystalline silicon layer; the concentration of phosphorus doped in the amorphous silicon layer is preferably 1.5-2.5 × 10 21 cm -3 (ii) a The thickness of the amorphous silicon layer is preferably 50 to 100nm, and more preferably 60 to 80nm.
A back passivation layer is arranged on the back of the amorphous silicon layer; the back passivation layer is preferably a silicon nitride layer; the thickness of the back passivation layer is preferably 75-90 nm; the refractive index of the back passivation layer is preferably 2 to 2.2.
In the present invention, the back surface of the silicon wafer is preferably further provided with a back electrode; the back electrode is in ohmic contact with the amorphous silicon layer; the back electrode is not particularly limited as long as it is an electrode known to those skilled in the art, and a silver paste electrode is preferred in the present invention.
The utility model provides a solar cell adopts ultra-thin oxide layer and polycrystalline silicon layer to form and constitutes TOPCon structure jointly, and this structure makes many electron tunneling get into the polycrystalline silicon layer, blocks simultaneously that minority carrier's hole is compound, realizes the horizontal transmission of electron at the polycrystalline silicon layer and is collected, has greatly reduced metal contact recombination current, has promoted the open circuit voltage and the short-circuit current of battery; meanwhile, unsaturated dangling bonds between the doped polycrystalline silicon layer and the passivation layer are reduced, the passivation effect can be effectively improved, and the conversion efficiency of the battery is improved.
The utility model also provides a preparation method of above-mentioned solar cell, including following step: s1) carrying out double-sided texturing on the surface of an N-type silicon wafer; s2) performing boron diffusion treatment on the front side of the silicon wafer subjected to double-sided texturing to form a boron diffusion layer and a borosilicate glass layer; s3) etching the back of the silicon wafer subjected to boron diffusion treatment; s4) growing a tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the back of the silicon wafer with the etched back by chemical vapor deposition in sequence, and then carrying out high-temperature annealing treatment; s5) removing the polysilicon layer wound and plated on the front side and the phosphorosilicate glass layer on the back side; s6) preparing a passivation layer on the front side and/or the back side of the silicon wafer; s7) preparing an electrode.
The utility model provides a preparation method of tunneling oxide layer passivation contact structure is one step with the deposition oxide layer, amorphous silicon layer and the three steps of technologies brief on phosphorosilicate glass layer, realizes the productivity integration, reduces production processes to furthest extension equipment use and maintenance cycle have improved rate of equipment utilization, have effectively avoided the inside problem that produces attachment and foreign matter easily of reaction cavity, reduce the manufacturing cost of TOPCon battery.
Referring to fig. 2, fig. 2 is a schematic view of a manufacturing process of a solar cell according to the present invention.
Wherein, the utility model has no special limitation to the source of all raw materials, and can be sold in the market; in the utility model, the size of the N-type silicon wafer is preferably 166-210 mm; the thickness is preferably 130 to 165 μm.
Carrying out double-sided texturing on the surface of the N-type silicon wafer, and forming a textured surface or a surface texture structure (such as a pyramid structure) on the surface of the N-type silicon wafer through double-sided texturing; the utility model has no special limitation on the method of double-sided texturing, and can be chemical etching, laser etching, mechanical method, plasma etching and the like; the strong alkaline solution has anisotropy in corrosion, so that a pyramid structure suede can be obtained, and the strong alkaline solution is preferably used for double-sided texturing on the surface of the N-type silicon wafer; the strongly alkaline solution is preferably an alkali metal hydroxide solution, more preferably a sodium hydroxide solution and/or a potassium hydroxide solution; the mass concentration of the strong alkaline solution is preferably 40-50%; the temperature of the double-sided texture making is preferably 70-90 ℃, more preferably 70-85 ℃, and further preferably 75-80 ℃; the time for double-sided texture surface making is preferably 5-10 min, more preferably 6-9 min, and further preferably 7-8 min; the amount of thinning in the double-sided texturing is preferably controlled to 0.35 to 0.65g, more preferably 0.39 to 0.55g, and still more preferably 0.39 to 0.45g.
Carrying out boron diffusion treatment on the front side of the silicon wafer subjected to double-sided texturing to form a boron diffusion layer and a borosilicate glass layer; through boron diffusion treatment, a microcrystalline silicon phase of the crystalline silicon is converted into a polycrystalline silicon phase, and boron with higher concentration is arranged on the surface of the silicon wafer to form a borosilicate glass layer (BSG); the boron source used for the boron diffusion treatment is preferably a boron halide, more preferably boron tribromide; the temperature of the boron diffusion treatment is preferably 800-860 ℃, and more preferably 800-830 ℃; the flow rate of nitrogen gas in the boron diffusion treatment is preferably 650 to 1050sccm, more preferably 700 to 1000sccm, still more preferably 750 to 950sccm, and most preferably 750 to 850sccm; the oxygen flow is preferably 600 to 900sccm, more preferably 700 to 900sccm, and further preferably 700 to 850sccm; the time for the boron diffusion treatment is preferably 14 to 20min, more preferably 15 to 20min, and still more preferably 15 to 18min.
Etching the back of the silicon wafer subjected to boron diffusion treatment; in the present invention, the back etching is preferably performed in a chain type cleaning machine; the back etching preferably adopts a mixed solution of hydrofluoric acid and nitric acid; the mass concentration of the hydrofluoric acid is 40-54%; the mass concentration of the nitric acid is 60-65%; the volume ratio of the hydrofluoric acid to the nitric acid is 1 (2-5), and more preferably 1 (3-5); the back etching temperature is preferably 13-20 ℃, and more preferably 13-18 ℃; the back etching time is preferably 2-4 min, and more preferably 3min; the mass reduction of the back etching is preferably controlled to be 0.1 to 2g, more preferably 0.5 to 1.5g, still more preferably 0.5 to 1g, and most preferably 0.8g.
Growing a tunneling oxide layer on the back surface of the silicon wafer with the etched back surface by utilizing chemical vapor deposition; the chemical vapor deposition may be one or more of Low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD) and atmospheric pressure Chemical Vapor Deposition (CVD), and is preferably Low Pressure Chemical Vapor Deposition (LPCVD); growing a silicon source of a tunneling oxide layer on the back surface of the silicon wafer after back surface etching by using chemical vapor deposition, wherein the silicon source is preferably silane; the flow ratio of the silicon source to the carrier gas is preferably 1: (2-2.5); the flow rate of the silicon source is preferably 100 to 250sccm, and more preferably 100 to 230sccm; the time for growing the tunneling oxide layer is preferably 20-30 min, and more preferably 24-27 min; the thickness of the tunneling oxide layer is preferably 1 to 2nm, and more preferably 1.6 to 2nm.
Then depositing a phosphorus-doped amorphous silicon layer; the phosphorus source for depositing the phosphorus-doped amorphous silicon layer is phosphorus oxychloride; the temperature for depositing the phosphorus-doped amorphous silicon layer is preferably 750-850 ℃, more preferably 750-800 ℃, and further preferably 750-790 ℃; the time for depositing the phosphorus-doped amorphous silicon layer is preferably 30-65 min, more preferably 50-65 min, still more preferably 55-65 min, and most preferably 59-65 min; when depositing the amorphous silicon layer doped with phosphorus, the flow ratio of the silicon source, the phosphorus source and the carrier is (0.5-1) to (1) (10-15); in the embodiment provided by the utility model, the flow ratio of the silicon source, the phosphorus source and the carrier is specifically 1; the pressure of the system when the phosphorus-doped amorphous silicon layer is deposited is preferably 0.5-1 mbar, more preferably 0.6-0.9 mbar, and still more preferably 0.8mbar; the thickness of the amorphous silicon layer is preferably 100 to 200nm.
Then carrying out high-temperature annealing treatment; the temperature of the high-temperature annealing treatment is preferably 830-880 ℃, and more preferably 840-880 ℃; the high-temperature annealing treatment is carried out under the condition of introducing a phosphorus source; the flow ratio of the carrier gas carrying the phosphorus source to the carrier gas is preferably 1 (1.9-3); the proportion of the phosphorus source to the carrier gas in the carrier carrying the phosphorus source is 1 (6-10); the pressure of the high-temperature annealing treatment is 0.5-2 mbar, more preferably 0.7-1.5 mbar, and still more preferably 0.7-1.2 mbar; the time of the high-temperature annealing treatment is preferably 20-30 min.
After high-temperature annealing treatment, removing the polysilicon layer wound on the front side and the phosphorosilicate glass layer on the back side, preferably removing the polysilicon layer wound on the front side and the phosphorosilicate glass layer on the back side by adopting a cleaning mode, so that front side borosilicate glass can be prevented from being damaged in the process of removing the winding plating, the influence of front side winding plating is greatly reduced, the reject ratio in the process of manufacturing the solar cell is reduced, and the aim of mass production is fulfilled; the cleaning is preferably carried out in a tank type machine table; in the utility model, the mixed solution of the additive and the strong alkaline solution is preferably adopted to clean and remove the polysilicon layer which is plated to the front side; the mass ratio of the additive to the strong alkaline solution is preferably 1 (4-8), more preferably 1 (5-7), and further preferably 1 (5-6.5); the additive is preferably PR21; the strongly alkaline solution is preferably an alkali metal hydroxide solution, more preferably a sodium hydroxide solution and/or a potassium hydroxide solution; the mass concentration of the strong alkaline solution is preferably 40-50%; the cleaning temperature is preferably 75-85 ℃; the cleaning time is 5-15 min, more preferably 7-12 min, and still more preferably 7-10 min; in the utility model, 5 to 10 percent of hydrofluoric acid is preferably adopted to clean and remove the phosphorosilicate glass layer on the back; after washing, washing and drying are preferred.
Preparing a passivation layer on the front side and/or the back side of the silicon wafer; in the utility model, the passivation layer is prepared on the front and/or back of the silicon wafer preferably by adopting the deposition of the monoatomic layer; the passivation layer on the front side comprises an aluminum oxide layer and a silicon nitride layer; the thickness of the aluminum oxide layer is preferably 1-10 nm; the thickness of the silicon nitride layer is preferably 75-90 nm; the passivation layer on the back side is preferably a silicon nitride layer, the thickness of which is preferably 75 to 90nm.
Finally, preparing an electrode to obtain a solar cell; the preparation method of the electrode is a method well known by the technicians in the field, and no special limitation is provided, the grid lines are preferably printed on the front side and the back side of the silicon wafer by adopting a screen printing mode, and the solar cell is obtained after sintering; the sintering temperature is preferably 780-830 ℃.
The utility model discloses grow the ultra-thin oxide layer of one deck at the silicon chip back earlier and form the tunnel layer, secondly deposit the amorphous silicon film of mixing phosphorus on the oxide layer, anneal under high temperature afterwards, make sedimentary amorphous silicon film crystallize into the polycrystalline silicon layer in order to strengthen the passivation effect, this oxide layer and polycrystalline silicon layer constitute TOPCON structure (tunnel oxide layer passivation contact) jointly, this structure makes many electron tunnels and gets into the polycrystalline silicon layer, block few electron hole recombination simultaneously, realize that the electron is at the lateral transfer of polycrystalline silicon layer and collected, greatly reduced metal contact combined current, the open circuit voltage and the short-circuit current of battery have been promoted; meanwhile, unsaturated dangling bonds between the doped polycrystalline silicon layer and the passivation layer are reduced, the passivation effect can be effectively improved, and the conversion efficiency of the battery is improved.
To further illustrate the present invention, the following detailed description is given to a solar cell and a method for manufacturing the same in combination with the embodiments.
The reagents used in the following examples are all commercially available; the raw materials used in the examples are all N-type silicon wafers with a size of 182mm and a thickness of 140 μm.
Example 1
1.1 texturing: 45% sodium hydroxide solution, temperature is maintained at 75 deg.C, time is 7min, and thinning amount is controlled at 0.39g.
1.2 boron diffusion: the boron source is boron tribromide; the reaction temperature is maintained at 800-830 ℃, the flow rate of low-concentration small nitrogen gas is 750-850 sccm, the time is 18min, and the flow rate of dry oxygen is 700-800 sccm.
1.3 etching: in the chain type cleaning mechanism, HF/HNO is adopted 3 Low-temperature etching with 45% hydrofluoric acid and 60% nitric acid at 13-18 deg.C and HF/HNO 3 Controlling the volume ratio of the solution to be 1; the mass loss was controlled at 0.8g.
1.4 tunneling oxidation: introducing SiH into the same LPCVD equipment 4 The flow is controlled to be 120-200sccm 4 ：N 2 The flow ratio is 1; generating a tunneling oxide layer within 25min, and controlling the thickness to be 2nm; using liquid phosphorus oxychloride POCl 3 Diffusing for 60min at the temperature of 750-780 ℃, keeping the flow ratio of a silicon source, a phosphorus source and a carrier at 1; the volume ratio of the phosphorus source to the nitrogen is 1-1; forming a polycrystalline silicon layer with the thickness of 105nm and an amorphous silicon layer with the thickness of 80nm;
1.5 removing the winding-plated polysilicon layer: removing the amorphous silicon layer on the front surface of the silicon wafer by a groove type machine table by using an additive (PR 21) which is a strong alkaline solution (45% sodium hydroxide solution) with the mass ratio of 1; removing the phosphosilicate glass layer on the back by using HF solution with concentration of 46-48% through a groove type machine, washing and drying;
1.6 preparation of passivation layer: the growth of front side alumina (61) was carried out by monoatomic layer deposition with a thickness of 8nm, and the growth of front and back side silicon nitride (62, 63) was carried out with a thickness of about 85nm (; refractive index 2.08).
1.7 preparation of electrodes: silver paste grid lines (71, a first electrode; 72, a second electrode) are printed on the front side and the back side of the silicon wafer in a screen printing mode, and finished product manufacturing is completed after the sintering temperature is 780-830 ℃.
Example 2
2.1 texturing: 45% sodium hydroxide solution, temperature is maintained at 75 deg.C, time is 7min, and thinning amount is controlled at 0.41g.
2.2 boron diffusion: the boron source is boron tribromide, the reaction temperature is maintained at 800-830 ℃, the flow of low-concentration small nitrogen is introduced at 750-800 sccm for 18min, and the flow of dry oxygen is 700-850 sccm.
2.3 etching: in the chain type cleaning mechanism, HF/HNO is adopted 3 The liquid medicine is corroded at low temperature of 13-18 ℃ and HF/HNO 3 Controlling the volume ratio of the solution to be 1; the mass loss was controlled at 0.8g.
2.4 tunneling oxidation: introducing SiH into the same LPCVD equipment 4 The flow rate is controlled to be 100-190sccm 4 ：N 2 The flow ratio is 1; generating a tunneling oxide layer within 27min, and controlling the thickness to be 1.8nm; using liquid phosphorus oxychloride POCl 3 And diffusing for 59min at the temperature of 750-780 ℃, keeping the flow ratio of the silicon source, the phosphorus source and the carrier at 1; the system pressure is 0.7mbar, and the time is about 25-30 min; the thickness of the formed polysilicon layer is 110nm, and the thickness of the formed amorphous silicon layer is 70nm.
2.5 removing the winding-plated polysilicon layer: removing the amorphous silicon layer wound and plated on the front surface of the silicon wafer by using a groove type machine table and using an additive (PR 21) which is a strong alkaline solution (45% sodium hydroxide solution) with the mass ratio of 1; and removing the phosphosilicate glass layer on the back by using HF with the concentration of 46-50% through a groove type machine, washing and drying.
2.6 preparation of passivation layer: growing aluminum oxide (61) on the front surface in a monoatomic layer deposition mode, controlling the thickness to be 7nm, and then growing silicon nitride (62, 63) on the front surface and the back surface to be about 78nm; the refractive index is 2.03.
2.7 preparation of electrodes: silver paste grid lines (71, a first electrode; 72, a second electrode) are printed on the front side and the back side of the silicon wafer in a screen printing mode, and finished product manufacturing is completed after the sintering temperature is 780-820 ℃.
Example 3
3.1 texturing: 45% sodium hydroxide solution, the temperature is maintained at 78 deg.C, the time is 7min, and the thinning amount is controlled at 0.45g.
3.2 boron diffusion: the boron source is boron tribromide, the reaction temperature is maintained at 800-830 ℃, the flow of low-concentration small nitrogen is introduced at 750-800 sccm for 18min, and the flow of dry oxygen is 700-850 sccm.
3.3 etching: in the chain type cleaning mechanism, HF/HNO is adopted 3 The liquid medicine is corroded at low temperature of 13-18 ℃ and HF/HNO 3 The volume ratio of the solution is controlled to be 1; the mass loss was controlled at 0.8g.
3.4 tunneling oxidation: introducing SiH into the same LPCVD equipment 4 The flow rate is controlled to be 130-230sccm 4 :N 2 The flow ratio is 1; generating a tunneling oxide layer within about 24min, and controlling the thickness to be 1.6nm; using liquid phosphorus oxychloride POCl 3 And diffusing for 65min under the condition of the temperature of 760-790 ℃, keeping the flow ratio of the silicon source, the phosphorus source and the carrier at 1; the system pressure is 0.75mbar, and the time is about 28-30 min; forming a polysilicon layerThe thickness is 120nm, and the thickness of the amorphous silicon layer is 60nm.
3.5 removing the winding-plated polysilicon layer: removing the amorphous silicon layer wound and plated on the front surface of the silicon wafer by using an additive (PR 21) which is a strong alkaline solution (45% sodium hydroxide solution) with the mass ratio of 1-5-1, the temperature of 76-85 ℃ and the time of 7-10 min through a groove type machine table, wherein the ratio of the additive (PR 21) to the strong alkaline solution (45%) is as follows; and removing the phosphosilicate glass layer on the back by using HF with the concentration of 46-47% through a groove type machine, and drying after washing.
3.6 preparation of passivation layer: growing aluminum oxide (61) on the front surface in a monoatomic layer deposition mode, controlling the thickness to be 6nm, and then growing silicon nitride (62, 63) on the front surface and the back surface, wherein the thickness is about 82nm; the refractive index was 2.07.
3.7 preparation of electrode: silver paste grid lines (71, a first electrode; 72, a second electrode) are printed on the front side and the back side of the silicon wafer in a screen printing mode, and finished product manufacturing is completed after the sintering temperature is 790-820 ℃.
Comparative example 1
1.1 texturing: :45% sodium hydroxide solution, the temperature is maintained at 78 deg.C, the time is 7min, and the reduction amount is controlled at 0.51g.
1.2 boron diffusion: the reaction temperature is maintained at 800-830 ℃, the flow rate of low-concentration small nitrogen is 750-810 sccm, the time is 18min, and the flow rate of dry oxygen is 720-850 sccm.
1.3 etching: in the chain type cleaning mechanism, HF/HNO is adopted 3 The liquid medicine is corroded at low temperature of 13-18 ℃ and HF/HNO 3 The volume ratio of the solution is controlled to be 1; the mass loss was controlled at 0.8g.
1.4 tunneling oxidation: introducing SiH by using CVD equipment 4 The flow rate is controlled between 110 sccm and 250sccm 4 :N 2 The flow ratio is 1; generating a tunneling oxide layer within about 30min, and controlling the thickness to be 2.6nm; then sending the silicon chip into a heating diffusion device by using liquid phosphorus oxychloride (POCl) 3 Diffusing for 80min at the temperature of 770-850 ℃, and then performing high-temperature annealing, wherein the temperature is maintained at 830-860 ℃, the flow ratio of nitrogen carrying a phosphorus source to nitrogen is 1.8-1; the system pressure is 0.85mbar, and the time is about 28-35 minLeft and right; the thickness of the formed polysilicon layer is 180nm, and the thickness of the amorphous silicon layer is 60nm.
1.5 removing the winding-plated polysilicon layer: removing the amorphous silicon layer wound and plated on the front surface of the silicon wafer by using a groove type machine table and using an additive (PR 21) and a strong alkaline solution (45% sodium hydroxide solution) with the mass ratio of 1; and removing the phosphosilicate glass layer on the back surface by using a HF solution with the concentration of 46-49% through a groove type machine, and drying after washing.
1.6 preparation of passivation layer: growing aluminum oxide (61) on the front surface in a monoatomic layer deposition mode, controlling the thickness to be 7nm, and growing silicon nitride (62, 63) on the front surface and the back surface to be about 81nm; the refractive index was 2.04.
1.7 preparation of electrodes: silver paste grid lines (71, a first electrode; 72, a second electrode) are printed on the front side and the back side of the silicon chip in a screen printing mode, and finished product manufacturing is completed after the sintering temperature is 795-850 ℃.
The solar cells obtained in examples 1 to 3 and comparative example 1 were tested, and the properties of the N-type bifacial solar cells prepared by different preparation methods are shown in table 1, the test environment is an industry-consistent standard condition, and the illumination intensity: 1000W/m 2 Temperature: 25 ℃, atmospheric mass: and 1.5 of AM.
Table 1 solar cell electrical performance test results
| Item | Eta | VOC | Isc | FF |
| Example 1 | 24.855 | 0.7169 | 13.901 | 82.35 |
| Example 2 | 24.907 | 0.7149 | 13.871 | 82.93 |
| Example 3 | 24.910 | 0.7163 | 13.887 | 82.69 |
| Comparative example 1 | 24.709 | 0.7166 | 13.780 | 82.62 |
As can be seen from table 1, compared to comparative example 1, in examples 1 to 3, the preparation of the tunnel oxide layer was completed by using a simplified method, and the obtained N-type bifacial solar cell has no disadvantages in open circuit voltage and conversion efficiency.
As can be seen from examples 1 to 3, in the present application, the tunneling oxide layer is prepared by a simplified method, and the obtained open-circuit voltage and conversion efficiency of the battery have operability and practical effects.
The embodiments described above are some, but not all embodiments of the present application. The detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (10)
1. A solar cell, comprising:
a silicon wafer;
the front side of the silicon wafer is sequentially provided with a borosilicate glass layer and a front passivation layer;
the back of the silicon chip is sequentially provided with a tunneling oxide layer, a polycrystalline silicon layer, an amorphous silicon layer and a back passivation layer.
2. The solar cell of claim 1, wherein the silicon wafer is an N-type silicon wafer.
3. The solar cell of claim 1, wherein the tunneling oxide layer has a thickness of 1 to 2nm.
4. The solar cell of claim 1, wherein the polysilicon layer has a thickness of 100 to 150nm.
5. The solar cell of claim 1, wherein the amorphous silicon layer has a thickness of 50 to 100nm.
6. The solar cell of claim 1, wherein the concentration of phosphorus doping in the amorphous silicon layer is 1.5-2.5 x 10 21 cm -3 。
7. The solar cell of claim 1, wherein the front passivation layer comprises an aluminum oxide layer and a silicon nitride layer.
8. The solar cell of claim 7, wherein the aluminum oxide layer has a thickness of 1 to 10nm; the thickness of the silicon nitride layer is 75-90 nm; the refractive index of the silicon nitride layer is 2-2.2.
9. The solar cell of claim 1, wherein the backside passivation layer is a silicon nitride layer; the thickness of the back passivation layer is 75-90 nm; the refractive index of the back passivation layer is 2-2.2.
10. The solar cell of claim 1, further comprising a front electrode and a back electrode; the front electrode is in ohmic contact with the borosilicate glass layer; the back electrode is in ohmic contact with the amorphous silicon layer.
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