CN110534614B - Preparation method of P-type crystalline silicon cell - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a preparation method of a P-type crystalline silicon cell, which solves the problem of electric leakage of a P-type crystalline silicon back carrier selective structure cell. It is composed ofThe method sequentially comprises the following steps: A. etching or polishing the back of the textured P-type crystal silicon wafer; B. growing an oxide thin layer on the back of the P-type crystal silicon wafer; C. depositing a polycrystalline silicon layer on the oxide thin layer, and doping III group elements; D. putting the doping surface of the group III element on the P-type crystal silicon wafer upwards into a first solution in a floating mode for treatment, wherein the first solution comprises HF and HNO3、H2SO4At least one of NaOH, KOH, TMAH and ammonia; E. carrying out phosphorus doping on the front side of the P-type crystal silicon wafer treated by the first solution; F. putting the P-type crystal silicon wafer with the phosphorus doped surface facing upwards into a second solution in a floating mode for treatment, wherein the second solution comprises HF and HNO3、H2SO4At least one of; G. and (4) putting the P-type crystal silicon wafer treated by the second solution into an alkaline solution for treatment.
Description
Technical Field
The invention belongs to the field of solar cells, and relates to a preparation method of a P-type crystalline silicon cell.
Background
Conventional fossil fuels are increasingly depleted, and of all sustainable energy sources, solar energy is undoubtedly one of the cleanest, most widespread and most potential alternative energy sources. At present, among all solar cells, a silicon solar cell is one of solar cells which are commercially popularized in a wide range, because silicon materials have an extremely abundant reserve in the earth crust, and simultaneously, the silicon solar cell has excellent electrical and mechanical properties compared with other types of solar cells, and the silicon solar cell plays an important role in the photovoltaic field. Therefore, the development of cost-effective silicon solar cells has become a main research direction of photovoltaic enterprises in various countries.
The existing crystalline silicon solar cell mainly uses a single-sided solar cell, namely only the front side of the cell can absorb sunlight and perform photoelectric conversion. Actually, sunlight also reaches the back of the cell through reflection, scattering and the like. However, the back surface of the traditional single-sided crystalline silicon cell is covered by metal aluminum, and sunlight reaching the back surface of the cell cannot penetrate through the silicon substrate, so that the sunlight reaching the back surface of the cell cannot be effectively absorbed. In order to further improve the absorption of solar light by the crystalline silicon cell, the photovoltaic industry is gradually developing a crystalline silicon solar cell which can absorb solar light on both sides, and is generally called a crystalline silicon double-sided solar cell.
The existing P-type crystalline silicon double-sided cell mainly comprises the following components: the traditional aluminum layer with the fully covered back surface is optimized to be the aluminum layer with the partially covered back surface, so that sunlight reaching the back surface of the cell can be absorbed by the silicon substrate through the region which is not covered by the aluminum layer to generate photon-generated carriers, and the photoelectric conversion capability of the crystalline silicon solar cell is improved.
However, the back surface of the P-type crystalline silicon cell forms a metallized ohmic contact with a silicon substrate by adopting aluminum, and higher carrier recombination exists in a contact area of aluminum-silicon alloy. The higher carrier recombination limits the further improvement of the photoelectric conversion efficiency of the crystalline silicon solar cell. In order to continuously improve the photoelectric conversion efficiency of the crystalline silicon solar cell, a carrier selective structure can be adopted to reduce the carrier recombination of a metalized region on the back surface of the P-type crystalline silicon double-sided cell.
However, when a carrier selective structure is prepared on the back surface of a P-type crystalline silicon cell, whether in-situ doping or thermal diffusion doping is used, doping elements diffract to an un-doped surface (usually a phosphorus-doped surface) in the doping process, so that the anode and the cathode of the cell are directly connected together without insulation, and current leakage is caused. Meanwhile, phosphorus is doped in a thermal diffusion mode, so that phosphorus is wound to a non-phosphorus doped surface, and the positive electrode and the negative electrode of the battery are directly connected together under the non-insulating condition, thereby causing electric leakage.
Disclosure of Invention
Aiming at the technical problems, the invention aims to provide a preparation method of a P-type crystalline silicon cell, which solves the problem of electric leakage of a cell with a P-type crystalline silicon back carrier selective structure.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a preparation method of a P-type crystalline silicon cell sequentially comprises the following steps:
A. etching or polishing the back surface of the textured P-type crystal silicon wafer, and keeping the textured surface on the front surface;
B. growing an oxide thin layer on the back of the P-type crystal silicon wafer;
C. depositing a polycrystalline silicon layer on the oxide thin layer, and doping III group elements;
D. putting the doping surface of the group III element on the P-type crystal silicon wafer upwards into a first solution in a floating mode for treatment, wherein the first solution comprises HF and HNO3、H2SO4At least one of NaOH, KOH, TMAH and ammonia;
E. carrying out phosphorus doping on the front side of the P-type crystal silicon wafer treated by the first solution;
F. putting the P-type crystal silicon wafer with the phosphorus doped surface facing upwards into a second solution in a floating mode for treatment, wherein the second solution comprises HF and HNO3、H2SO4At least one of;
G. putting the P-type crystal silicon wafer treated by the second solution into an alkaline solution for treatment;
H. removing phosphorosilicate glass and III-group silicate glass on the surface of the P-type crystal silicon wafer treated by the alkaline solution;
I. oxidizing the surface of the P-type crystal silicon wafer;
J. depositing a passivation layer and an antireflection layer on a III group diffusion surface on the P type crystal silicon wafer, and depositing the antireflection layer on a phosphorus diffusion surface;
K. and carrying out a metallization process to form a front metal electrode and a back metal electrode.
Preferably, in the step D, a water film is formed on the group III element doped surface of the P-type crystalline silicon wafer, and then the P-type crystalline silicon wafer is placed in the first solution in a floating manner for treatment; and in the step F, a water film is formed on the phosphorus doped surface of the P-type crystal silicon wafer, and then the P-type crystal silicon wafer is placed into a second solution in a floating mode for treatment.
In a preferred embodiment, the step D is implemented as follows: and forming a water film on the III-group element doped surface of the P-type crystal silicon wafer, and conveying the P-type crystal silicon wafer by adopting a chain type conveying device to enable the III-group element doped surface of the P-type crystal silicon wafer to face upwards and pass through the first solution in a floating manner. Specifically, a water film is formed by spraying.
More preferably, the first solution is a solution formed by HF and deionized water, the volume concentration of the HF is 3-7%, and the transmission speed of the chain transmission device is 1.8-2.2 m/s.
In a preferred embodiment, the step F is implemented as follows: and forming a water film on the phosphorus doped surface of the P-type crystal silicon wafer, and conveying the P-type crystal silicon wafer by adopting a chain type conveying device to enable the phosphorus doped surface of the P-type crystal silicon wafer to face upwards and pass through the second solution in a floating manner. Specifically, a water film is formed by spraying.
More preferably, the second solution is a solution formed by HF and deionized water, the volume concentration of the HF is 3-7%, and the transmission speed of the chain type transmission device is 1.6-2.0 m/s.
Preferably, the alkaline solution in step G is NaOH, KOH, TMAH or NH4And (4) OH solution. More preferably, the alkaline solution in the step G is a KOH solution with a volume concentration of 2-5%, and the treatment time is 400-800 s. And the doped layer at the edge of the silicon wafer is removed through the reaction of the alkaline solution and the silicon, so that electric leakage is prevented.
Preferably, the thin oxide layer in step B is a thin silicon oxide layer.
Preferably, in the step C, the group III element is doped during or after the deposition of the polysilicon layer.
Preferably, in the step H, the P-type crystal silicon wafer is put into an HF solution, and phosphorosilicate glass and III-group silicate glass on the surface are removed.
Preferably, the step I is implemented as follows: and oxidizing the P-type crystal silicon wafer, removing the oxide on the surface, and oxidizing the surface of the P-type crystal silicon wafer.
More preferably, in the step I, firstly, the ozone solution or HNO is passed3Oxidizing P-type crystal silicon wafer with the solution, placing the oxidized wafer in HF solution to remove the surface oxide layer, and passing through ozone solution or HNO3The solution oxidizes the surface of the P-type crystal silicon wafer.
Preferably, in the step J, an aluminum oxide layer and a silicon nitride layer are sequentially deposited on the group III diffusion surface on the P-type crystalline silicon wafer, and a silicon nitride layer is deposited on the phosphorus diffusion surface on the P-type crystalline silicon wafer.
In a specific and preferred embodiment, the preparation method comprises the following steps in sequence:
(1) texturing the P-type crystal silicon wafer (forming a pyramid-shaped textured surface on the surface);
(2) etching or polishing the back of the textured P-type silicon wafer, and reserving a pyramid surface on the front;
(3) growing a SiOx thin layer on the back of the P-type silicon wafer;
(4) depositing a Polysilicon polycrystalline silicon layer on the back of the P-type silicon wafer;
(5) doping III group elements in situ in the deposition process of the Polysilicon layer, or doping III group elements after the deposition process of the Polysilicon layer;
(6) doping the silicon wafer with III group element, forming water film on the III group element doping surface, conveying with chain type, making the doping surface upward pass through the first solution in floating manner, wherein the first solution may contain HF, HNO3、H2SO4NaOH, KOH, TMAH, and ammonia;
(7) carrying out phosphorus doping on the front side of the P-type crystalline silicon;
(8) the phosphorus-doped silicon wafer is formed into a water film on the phosphorus-doped surface, and the water film is transported in a chain mode, the phosphorus-doped surface faces upwards and passes through a second solution in a floating mode, wherein the second solution can contain HF and HNO3And H2SO4；
(9) Placing the silicon wafer in alkaline solution, and reacting with silicon to remove doped layer at the edge of the silicon wafer and prevent electric leakage, wherein the alkaline solution may contain NaOH, KOH, TMAH or NH4OH and the like with deionized water;
(10) placing the silicon chip in a mixed solution of HF and deionized water, and removing phosphorosilicate glass and III-group silicate glass on the surface;
(11) oxidizing the silicon wafer by ozone solution or HNO3Solution realization;
(12) placing the silicon wafer in a mixed solution of HF and deionized water to remove an oxide layer on the surface;
(13) oxidizing the surface of the silicon wafer, wherein the oxidation process can be carried out by ozone solution or HNO3Solution realization;
(14) depositing an alumina layer on the III group diffusion surface of the silicon wafer;
(15) depositing SiNx layers on the III-group diffusion surface and the phosphorus diffusion surface of the silicon wafer respectively;
(16) and carrying out a metallization process on the surface of the silicon wafer.
Compared with the prior art, the invention has the following advantages by adopting the scheme:
the preparation method of the P-type crystalline silicon cell can solve the problem of edge leakage of the cell and remarkably reduce reverse voltage leakage of the P-type crystalline silicon cell on the basis of effectively protecting the III-group element diffusion surface and the phosphorus diffusion surface of the P-type crystalline silicon cell; the preparation method is simple and is suitable for popularization and application.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural view of a P-type crystalline silicon cell prepared in example 1.
Wherein, 1, a front metal electrode; 2. a SiNx layer; 3. a phosphorus doped layer; 4. a P-type crystalline silicon substrate; 5. a SiOx layer; 6. a Polysilicon layer; 7. an AlOx layer; 8. a SiNx layer; 9. and a back metal electrode.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the advantages and features of the invention may be more readily understood by those skilled in the art. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
Fig. 1 shows a P-type crystalline silicon cell manufactured in this embodiment, which includes a front metal electrode 1, a SiNx layer 2, a phosphorus doped layer 3, a P-type silicon substrate layer 4, a SiOx layer 5, a Polysilicon layer 6, an AlOx layer 7, a SiNx layer 8, and a back metal electrode 9, wherein the SiNx2 layer, the phosphorus doped layer 3, the P-type silicon substrate layer 4, the SiOx layer 5, the Polysilicon layer 6, the AlOx7 layer, and the SiNx layer 8 are sequentially stacked from top to bottom, the front metal electrode 1 passes through the SiNx layer 2 to form an ohmic contact with the phosphorus doped layer 3, and the back metal electrode 9 passes through the SiNx layer 8 and the AlOx layer 7 to form an ohmic contact with the Polysilicon layer 6.
A P-type crystalline silicon cell as shown in FIG. 1 was prepared by preparing a group of P-type single crystal silicon wafers (50 wafers) as follows:
(1) texturing a P-type crystal silicon wafer, forming a pyramid textured surface on the surface of the silicon wafer, wherein a texturing solution is a mixed solution of KOH, a texturing additive and deionized water, the volume concentration of the KOH is 3%, and the texturing time is 800 seconds;
(2) forming a water film on one surface of the textured P-type crystalline silicon wafer, conveying the silicon wafer in a chain manner, wherein the water film faces upwards and passes through HF and HNO in a floating manner3、H2SO4And deionized water, wherein the HF solution is 30L, HNO3Solution 230L, H2SO460L of solution, 200L of deionized water, the temperature of the solution is 16 ℃, and the speed of a conveying belt is 2 m/s;
(3) growing a SiOx thin layer on the back of the P-type silicon wafer by LPCVD;
(4) depositing a Polysilicon polycrystalline silicon layer on the back of the P-type silicon wafer by LPCVD;
(5) doping a Polysilicon layer on the back of a P-type silicon wafer by using a boron diffusion tube, wherein the doping source is N carrying BBR32In which BBR3 is carried2The flow is 150sccm, the source nitrogen flow is not carried by 30SLM, the oxygen flow is 600sccm, the source connection time is 25min, and the temperature is 900 ℃;
(6) forming a water film on the boron doped surface by using a chain type cleaning machine, and enabling the water film to pass through a mixed solution of HF and deionized water in a floating mode, wherein the volume concentration of the HF is 5%, and the transmission speed is 2 m/s;
(7) doping the front surface of the P-type silicon wafer by using a phosphorus diffusion tube, wherein the doping source is carried with POCl3N of (A)2In which POCl is carried3N of (A)2The flow is 100sccm, the source nitrogen flow is not carried by 5SLM, the oxygen flow is 600sccm, the source connection time is 30min, and the temperature is 880 ℃;
(8) forming a water film on a phosphorus doped surface by using a chain type cleaning machine, and enabling the water film to pass through a mixed solution of HF and deionized water in a floating mode, wherein the volume solubility of the HF is 5%, and the transmission speed is 1.8 m/s;
(9) placing the silicon chip in KOH alkaline solution, wherein the volume concentration of KOH is 3%, and the reaction time is 600 seconds;
(10) placing the silicon chip in an HF solution, wherein the concentration of the HF solution is 5%, and the reaction time is 300 seconds;
(11) placing the silicon wafer in HNO3In solution, HNO3The solution concentration is 67%, and the reaction time is 300 seconds;
(12) placing the silicon chip in an HF solution, wherein the concentration of the HF solution is 5%, and the reaction time is 300 seconds;
(13) placing the silicon wafer in HNO3In solution, HNO3The solution concentration is 67%, and the reaction time is 300 seconds;
(14) depositing an AlOx layer on the boron-doped surface of the silicon wafer by using an Atomic Layer Deposition (ALD), wherein the thickness of the AlOx layer is 6 nm;
(15) depositing SiNx layers on the back and the front of the silicon wafer respectively, wherein the thickness of the SiNx layers is 90nm, and the refractive index is 2.05;
(16) printing silver-aluminum paste on a boron diffusion surface of a silicon wafer, and performing a drying process at the drying temperature of 300 ℃;
(17) printing silver paste on the phosphorus diffusion surface of the silicon wafer, and performing a sintering process, wherein the sintering temperature is 900 ℃.
Comparative example 1
A P-type crystalline silicon cell as shown in FIG. 1 was prepared by preparing a group of P-type single crystal silicon wafers (50 wafers) as follows:
(1) texturing a P-type crystal silicon wafer, forming a pyramid textured surface on the surface of the silicon wafer, wherein a texturing solution is a mixed solution of KOH, a texturing additive and deionized water, the volume concentration of the KOH is 3%, and the texturing time is 800 seconds;
(2) forming a water film on the single surface of the textured P-type silicon wafer, conveying the silicon wafer in a chain manner, wherein the water film faces upwards and passes through HF and HNO in a floating manner3、H2SO4And deionized water, wherein the HF solution is 30L, HNO3Solution 230L, H2SO460L of solution, 200L of deionized water, the temperature of the solution is 16 ℃, and the speed of a conveying belt is 2 m/s;
(3) growing a SiOx thin layer on the back of the P-type silicon wafer by LPCVD;
(4) depositing a Polysilicon polycrystalline silicon layer on the back of the P-type silicon wafer by LPCVD;
(5) doping a Polysilicon layer on the back of a P-type silicon wafer by using a boron diffusion tube, wherein the doping source is N carrying BBR32In which BBR3 is carried2The flow is 150sccm, the source nitrogen flow is not carried by 30SLM, the oxygen flow is 600sccm, the source connection time is 25min, and the temperature is 900 ℃;
(6) doping the front surface of the P-type silicon wafer by using a phosphorus diffusion tube, wherein the doping source is carried with POCl3N of (A)2In which POCl is carried3N of (A)2The flow is 100sccm, the source nitrogen flow is not carried by 5SLM, the oxygen flow is 600sccm, the source connection time is 30min, and the temperature is 880 ℃;
(7) placing the silicon chip in an HF solution, wherein the concentration of the HF solution is 5%, and the reaction time is 300 seconds;
(8) placing the silicon wafer in HNO3In solution, HNO3The solution concentration is 67%, and the reaction time is 300 seconds;
(9) placing the silicon chip in an HF solution, wherein the concentration of the HF solution is 5%, and the reaction time is 300 seconds;
(10) placing the silicon wafer in HNO3In solution, HNO3The solution concentration is 67%, and the reaction time is 300 seconds;
(11) depositing an AlOx layer on the boron-doped surface of the silicon wafer by using an Atomic Layer Deposition (ALD), wherein the thickness of the AlOx layer is 6 nm;
(12) depositing SiNx layers on the back and the front of the silicon wafer respectively, wherein the thickness of the SiNx layers is 90nm, and the refractive index is 2.05;
(13) printing silver-aluminum paste on a boron diffusion surface of a silicon wafer, and performing a drying process at the drying temperature of 300 ℃;
(14) printing silver paste on the phosphorus diffusion surface of the silicon wafer, and performing a sintering process, wherein the sintering temperature is 900 ℃.
After the preparation of the batteries was completed, 5 pieces of the battery pieces obtained in example 1 and comparative example 1 were randomly extracted, and the electric leakage of the two sets of the battery pieces was measured using a battery IV tester, and the obtained electric leakage test data are shown in tables 1 and 2, respectively.
Table 1 leakage test data for the cell of example 1
Table 2 leakage test data for the cell of comparative example 1
| Cell serial number | 12V reverse voltage leakage |
| 6 | 10A |
| 18 | 9.9A |
| 26 | 9.6A |
| 36 | 10A |
| 45 | 10A |
As can be seen from tables 1 and 2, the cell prepared by the preparation method of example 1 has small leakage at 12V reverse voltage, solves the leakage problem, and significantly reduces the leakage at reverse voltage of the P-type crystalline silicon cell.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and are preferred embodiments, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the scope of the present invention. All equivalent changes or modifications made according to the principles of the present invention should be covered within the protection scope of the present invention.
Claims (7)
1. A preparation method of a P-type crystalline silicon cell is characterized by sequentially comprising the following steps:
A. etching or polishing the back surface of the textured P-type crystal silicon wafer, and keeping the textured surface on the front surface;
B. growing an oxide thin layer on the back of the P-type crystal silicon wafer;
C. depositing a polycrystalline silicon layer on the oxide thin layer, and doping III group elements;
D. forming a water film on the III group element doped surface of the P type crystal silicon wafer, and conveying the P type crystal silicon wafer by adopting a chain type conveying device to enable the III group element doped surface of the P type crystal silicon wafer to face upwards and pass through a first solution in a floating mode, wherein the first solution comprises HF and HNO3、H2SO4At least one of NaOH, KOH, TMAH and ammonia;
E. carrying out phosphorus doping on the front side of the P-type crystal silicon wafer treated by the first solution;
F. forming a water film on the phosphorus doped surface of the P-type crystal silicon wafer, and conveying the P-type crystal silicon wafer by adopting a chain type conveying device to enable the phosphorus doped surface of the P-type crystal silicon wafer to face upwards and pass through a second solution in a floating mode, wherein the second solution comprises HF and HNO3、H2SO4At least one of;
G. putting the P-type crystal silicon wafer treated by the second solution into an alkaline solution for treatment;
H. removing phosphorosilicate glass and III-group silicate glass on the surface of the P-type crystal silicon wafer treated by the alkaline solution;
I. oxidizing the surface of the P-type crystal silicon wafer;
J. depositing a passivation layer and an antireflection layer on a III group diffusion surface on the P type crystal silicon wafer, and depositing the antireflection layer on a phosphorus diffusion surface;
K. and carrying out a metallization process to form a front metal electrode and a back metal electrode.
2. The method according to claim 1, wherein the first solution is a solution of HF and deionized water, the HF volume concentration is 3-7%, and the conveying speed of the chain conveyor is 1.8-2.2 m/s.
3. The method according to claim 1, wherein the second solution is a solution of HF and deionized water, the HF volume concentration is 3-7%, and the conveying speed of the chain conveyor is 1.6-2.0 m/s.
4. The preparation method according to claim 1, wherein the alkaline solution in step G is a KOH solution with a volume concentration of 2-5%, and the treatment time is 400-800 s.
5. The production method according to claim 1, wherein the thin oxide layer in step B is a thin silicon oxide layer; and C, doping III group elements in the process of depositing the polycrystalline silicon layer or after depositing the polycrystalline silicon layer.
6. The method according to claim 1, wherein step I is carried out as follows: and oxidizing the P-type crystal silicon wafer, removing the oxide on the surface, and oxidizing the surface of the P-type crystal silicon wafer.
7. The preparation method according to claim 1, wherein in the step J, an aluminum oxide layer and a silicon nitride layer are sequentially deposited on the group III diffusion surface on the P-type crystalline silicon wafer, and a silicon nitride layer is deposited on the phosphorus diffusion surface on the P-type crystalline silicon wafer.
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