CN108365022A - The preparation method of the black policrystalline silicon PERC battery structures of selective emitter - Google Patents

The preparation method of the black policrystalline silicon PERC battery structures of selective emitter Download PDF

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CN108365022A
CN108365022A CN201810090750.0A CN201810090750A CN108365022A CN 108365022 A CN108365022 A CN 108365022A CN 201810090750 A CN201810090750 A CN 201810090750A CN 108365022 A CN108365022 A CN 108365022A
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陈丽萍
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Wuxi Suntech Power Co Ltd
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Abstract

The present invention relates to a kind of preparation methods of the black policrystalline silicon PERC battery structures of selective emitter, characterized in that includes the following steps：（1）Nanometer suede is formed in front side of silicon wafer, the back side is burnishing surface；（2）N-type layer is diffuseed to form in the front of silicon chip, removes front phosphorosilicate glass and back side pn-junction；（3）In front side of silicon wafer deposited silicon nitride antireflection film layer, passivation dielectric layer is overleaf deposited；（4）It is got ready or routing in silicon chip back side, prints silver electrode and aluminium paste；（5）Low-temperature sintering forms local Al-BSF；（6）The mixed solution of phosphoric acid and alcohol is sprayed in front side of silicon wafer, the main gate line after heavy doping and secondary grid region are formed using laser；（7）Front side of silicon wafer immerses electroplating solution, and front side of silicon wafer is electroplated under illumination condition, is annealed after plating.The defect that grid line is precisely aligned with selective emitter is difficult to form the fine grid line of high quality and can not ensured the present invention overcomes silk-screen printing, and masking caused by electrode and leakage current are minimized.

Description

The preparation method of the black policrystalline silicon PERC battery structures of selective emitter
Technical field
The present invention relates to a kind of preparation methods of the black policrystalline silicon PERC battery structures of selective emitter, belong to photoelectric technology Field.
Background technology
Photovoltaic generation still can not replace traditional energy since its cost is too high, reduce cost, improve solar cell conversion Efficiency, which is the key that photovoltaic industry, can gradually replace traditional energy.Photovoltaic generation product is still with polycrystalline sun electricity currently on the market It is to drop this key based on the component of pond, to reduce polycrystalline solar cell cost, improve polycrystalline battery conversion efficiency.
Polycrystalline diamond wire cutting silicon chip is fast with cutting speed, it is thinner that line loss smaller, damaging layer are cut compared to mortar, more The advantages such as environmentally friendly, at low cost, the market share rise year by year, and gradually substitute mortar and cut silicon chip, silicon wafer cut by diamond wire reduces Silicon chip cost will become industry mainstream, but polycrystalline diamond line cuts solar battery surface that reflectivity height constrains battery efficiency It is promoted, making herbs into wool rear surface has aberration to affect the yields that polycrystalline diamond line cuts solar cell, and the black silicon technology of wet method successfully solves It has determined these problems, polycrystalline diamond line can be improved and cut the transfer efficiency of solar cell, yields and reduce battery cost.
Metallic particles of the metal catalytic chemical corrosion method using electronegativity such as silver, copper higher than silicon in the black silicon of wet method is in chemistry Porous structure is formed in silicon chip surface under the action of corrosive liquid, to reduce silicon chip surface reflectivity, simple process and low cost, It is more suitable for industrial production, polycrystalline improved efficiency 0.2-0.3% (absolute value) can be made.It is conventional slurry silicon chip suede as shown in Figure 1 The SEM figures (5000 times of amplification) of face structure, Fig. 2 are the SEM figures (5000 times of amplification) of the black silicon suede structure of diamond wire polycrystalline, Fig. 3 For the reflectivity comparison diagram of black silion cell and conventional batteries.
Black silicon matte is nano-pore, and conventional polycrystalline matte is micron order myrmekitic texture, therefore black silicon specific surface area is more than often Polycrystalline is advised, due to black silicon suede structure particularity, surface impurity concentration is high when front surface phosphorus diffusion prepares PN junction, auger recombination Seriously, it is easier to form diffusion " dead layer ".To promote black silion cell transfer efficiency, surface dopant concentration need to be reduced, photoproduction is reduced The surface recombination of minority carrier.Meanwhile under lower surface impurity concentration, the passivation effect of black silicon face is also more preferable, blunt Surface recombination can be further reduced after change.But after surface dopant concentration reduces, the contact resistance in metal electrode region can increase, and lead Cell series resistance is caused to increase decrease in efficiency.Selective emitting electrode structure sensitive area between battery electrode grid line and grid line The corresponding active region in domain forms low-doped shallow diffusion region, and the gate electrode line lower zone of battery forms highly doped deep diffusion region. The NP knots as conventional solar cell are formed in electrode gap area, lateral N is formed in doped regions and high-doped zone intersection+ N height is tied, and N is formed below gate electrode line+P is tied, compared with conventional solar cell, selective emitter solar battery electrode grid More transverse direction N at line+N height knot and a N+P is tied, and is conducive to improve the collection rate of photo-generated carrier, is reduced solar cell Series resistance, the surface recombination for reducing photogenerated minority carriers and the influence for reducing diffusion death layer.It is superimposed selective emitting electrode Structure, black silion cell efficiency can promote 0.2-0.3% (absolute value) again.
The black silicon nanometer making herbs into wool technology of wet method and selective emitting electrode structure make the transfer efficiency of polycrystalline diamond line solar cell Have and is substantially improved.But the more serious optically and electrically loss of battery back surface has become and restricts the black silion cell efficiency of polycrystalline The bottleneck further promoted.It is multiple that back surface electricity can be not only greatly reduced in passivation emitter back-contact cell (PERC) structure Rate is closed, can also be formed under good internal optics back reflection mechanism, the especially development trend in silicon chip towards sheet, Battery surface is passivated quality and the importance of internal back reflection effect just more highlights.PERC structures make black silion cell improved efficiency 0.7-1.0%.It is illustrated in figure 4 the structural schematic diagram of selective emitter solar battery.
Invention content
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of black policrystalline silicon of selective emitter is provided The preparation method of PERC battery structures solves the problems, such as that surface reflectivity is high, improves black silion cell transfer efficiency, overcomes Silk-screen printing technique is difficult to form the fine grid line of high quality and can not to ensure that grid line is precisely aligned with selective emitter fatal Defect minimizes masking caused by electrode and leakage current.
According to technical solution provided by the invention, the preparation side of the black policrystalline silicon PERC battery structures of selective emitter Method, characterized in that include the following steps：
(1) nanometer suede is formed in front side of silicon wafer, silicon chip back side is burnishing surface；
(2) it spreads：Phosphorus diffusion is carried out in the front of silicon chip and forms N-type layer, and diffusion rear surface square resistance is 120-140 Ω/□；
(3) front side of silicon wafer phosphorosilicate glass and back side pn-junction are removed；
(4) plated film：In front side of silicon wafer deposited silicon nitride antireflection film layer, in silicon chip back side depositing Al Ox/SiNxOverlayer passivation Dielectric layer；
(5) it is got ready or routing in silicon chip back side using laser, makes AlOx/SiNxOverlayer passivation dielectric layer is from silicon chip table It removes in face；
(6) silk-screen printing：Overleaf silk-screen printing silver electrode and aluminium paste；
(7) it is sintered：Carrying out low-temperature sintering makes aluminium paste form local Al-BSF, sintering temperature with the pasc reaction at laser windowing It is 600-650 DEG C；
(8) phosphoric acid is sprayed：In the mixed solution of the phosphoric acid and alcohol of front side of silicon wafer even application 3-8%, used after spraying Hot nitrogen is dried；
(9) laser doping：Front side of silicon wafer is heated using laser, forms the main gate line after heavy doping and secondary grid line area Domain；
(10) nickel copper/silver electrode is electroplated in photoinduction：Front side of silicon wafer is immersed into electroplating solution, to front side of silicon wafer in illumination item It is electroplated under part, deposition plates metal grid lines, silicon chip surface intensity of illumination 15000- at the front gate line of silicon chip 20000lux, 1-2 μm of nickel layer thickness, 10-15 μm of copper layer thickness, 2-4 μm of silver thickness；
(11) it anneals.
Further, the nanometer suede aperture 200-700nm that the step (1) is prepared, reflectivity 14-18%.
Further, in the step (2), in diffusion furnace at a temperature of 880 DEG C, using phosphorus oxychloride silicon chip just Face carries out phosphorus diffusion and forms N-type layer.
Further, in the step (4), the thickness of silicon nitride anti-reflecting film is 75-85nm, and mean refractive index is 2.04-2.14；Aluminum oxide film thickness is 10-30nm, and refractive index 1.55-1.70, silicon nitride film thickness is 120-200nm, folding It is 1.90-2.20 to penetrate rate.
Further, when carrying out routing in the step (5), lines spacing is 0.7-0.9mm, line width 40-60um；It beats When point, point spacing is 0.6-0.8mm, spot diameter 200um.
Further, for the optical maser wavelength used in the step (9) for 355nm or 532nm, the grid line width of formation is 8- 12μm。
Further, in the step (11), silicon chip is annealed in nitrogen or nitrogen and hydrogen mixture atmosphere, annealing temperature It is 300-450 DEG C, annealing time 3-8 minutes.
The present invention has the following advantages：
(1) present invention prepares black silicon matte using metal catalytic chemical corrosion method, and front forms nano aperture matte and reduces Diamond wire cuts the surface reflectivity of polysilicon chip, has both solved diamond wire and has cut polysilicon chip using table caused by conventional making herbs into wool technology Reflectivity high problem in face improves black silion cell transfer efficiency, and solves the problems, such as surface chromatic aberration, and it is good to improve black silion cell Product rate；Black silicon nanometer suede makes polycrystalline diamond line cut efficiency of solar cell promotion 0.2-0.3% (absolute value).
(2) present invention uses one texture-etching side, only forms nanometer suede in front, and the back side is even curface after alkali polishing, Back surface recombination rate is reduced while increasing back reflection, improves the open-circuit voltage and short circuit current of black silion cell.Single side Making herbs into wool is compared with the two-sided making herbs into wool of immersion, and production capacity promotes one times, and chemicals cost, cost for wastewater treatment, energy consumption cost are lower, drop Low black silicon manufacturing cost has huge application, it can be achieved that prepared by the batch of the black silicon of large area in the preparation of black silicon solar cell Potentiality.
(3) battery front side of the invention forms selective emitting electrode structure, the light between battery electrode grid line and grid line The corresponding active region in region forms low-doped shallow diffusion region, and the gate electrode line lower zone of battery forms highly doped deep diffusion Area.Be conducive to improve the collection rate, the series resistance for reducing solar cell, the table for reducing photogenerated minority carriers of photo-generated carrier Face is compound and reduces the influence of diffusion death layer.It is superimposed selective emitting electrode structure, black silion cell efficiency can promote 0.2-0.3% again (absolute value) significantly improves the quantum efficiency of black silion cell short-wave band.
(4) cell backside of the invention uses AlOx/SiNxOverlayer passivation is opened a window using laser on the passivation layer, with aluminium paste Reaction forms local back surface field, which not only forms good internal optics back reflection mechanism, but also significantly reduces back of the body table Face electricity recombination rate, black silion cell efficiency promote 0.7-1.0% again, significantly improve the quantum effect of black silion cell long-wave band Rate.
(5) present invention forms heavy doping using laser doping technology in metal electrode lower zone.Laser action is being adulterated Phosphorus source and silicon chip surface, using its high-temperature heating, the phosphorus atoms in doped source are diffused rapidly to silicon chip table by local melting material Face, after laser is removed, silicon chip is cooling and crystallizes, and forms alloy with doping phosphorus atoms, and form heavily doped area.The present invention is using sharp The impurity of silicon chip surface grid line corresponding position is selected activation by light, be realize selective emitter battery structure most precisely, most Economic means plays selective emitter in the advantage for improving battery shortwave spectrum responder face to greatest extent.
(6) present invention forms front gate line using photoinduction electroplating technology, overcomes silk-screen printing technique and is difficult to form height The fine grid line of quality and it can not ensure the critical defect that grid line and selective emitter precisely align, ingenious formation fine metal Grid minimize masking caused by electrode and leakage current.
Description of the drawings
Fig. 1 is the SEM figures (5000 times of amplification) of conventional slurry silicon wafer suede structure.
Fig. 2 is the SEM figures (5000 times of amplification) of the black silicon suede structure of diamond wire polycrystalline.
Fig. 3 is the reflectivity comparison diagram of black silion cell and conventional batteries.
Fig. 4 is the structural schematic diagram of selective emitter solar battery.
Fig. 5 is the schematic diagram of selective emitter+rear side local contact solar battery structure.
Fig. 6 is the black silicon front elevation of single side.
Fig. 7 is the black silicon back view of single side.
Fig. 8 is photoinduction electroplating principle schematic diagram.
Reference sign：1- silicon chips, 2-AlOx/SiNxOverlayer passivation dielectric layer, 3- Al-BSFs, 4- silicon nitride antireflectives Film, 5- grid lines, 6- back electrodes.
Specific implementation mode
With reference to specific attached drawing, the invention will be further described.
Embodiment 1：A kind of preparation method of the black policrystalline silicon PERC battery structures of selective emitter, includes the following steps：
(1) one texture-etching side：Through the load → alkali throwing → pickling → heavy silver → borehole → desilverization → reaming → alkali cleaning → pickling → Fragment → pickling → washing → drying forms nanometer suede in the front of silicon chip 1, and silicon chip back side is burnishing surface without matte, is prepared into The nanometer suede aperture 600nm arrived, reflectivity 18%；
(2) it spreads：Existed using phosphorus oxychloride in diffusion furnace at a temperature of 880 DEG C using the method for tube furnace phosphorus diffusion The front of silicon chip carries out phosphorus diffusion and forms N-type layer, 120 Ω of diffusion rear surface square resistance/；
(3) it etches：Etching method is protected using moisture film, removes front side of silicon wafer phosphorosilicate glass and back side pn-junction；Due to single side system The back side is smooth after suede, is in polishing condition, achievees the purpose that polished backside without increasing chemical concentration when etching, reduces chemistry Product dosage；
(4) plated film：It is 75nm in the thickness of front side of silicon wafer deposited silicon nitride antireflection film layer 4, silicon nitride anti-reflecting film, puts down Equal refractive index is 2.04；In silicon chip back side depositing Al Ox/SiNxOverlayer passivation dielectric layer 2, aluminum oxide film thickness 20nm, refraction Rate is 1.55-1.70, and silicon nitride film thickness is 200nm, refractive index 1.90-2.20；
(5) backside laser opens a window：It is got ready or routing in silicon chip back side using laser, makes AlOx/SiNxOverlayer passivation is situated between Matter layer is removed from silicon chip surface；Lines open a window：Lines spacing is 0.7-0.9mm, line width 40-60um, and line segment is dislocatedly distributed；Point Shape opens a window：Point spacing is 0.6-0.8mm, spot diameter 200um, is dislocatedly distributed, and equilateral triangle is formed；
(6) silk-screen printing：Overleaf silk-screen printing silver electrode and aluminium paste；
(7) it is sintered：Using chain-type sintering furnace low-temperature sintering, aluminium paste forms local Al-BSF with the pasc reaction at laser windowing 3, non-windowed regions are passive area, and dielectric layer is not reacted with aluminium paste；
For conventional batteries, front side silver paste, back side silver paste, back side aluminium paste need to be completed at the same time sintering to form adhesive force normal Electrode and back surface field, it usually needs high temperature co-firing.Since aluminium silicon temperature of eutectic point is 577 DEG C, the application only needs low-temperature sintering i.e. Part Al-BSF can be achieved and do not need 800 DEG C or more of high temperature sintering generally at 600-650 DEG C, avoid high temperature sintering and bring Silicon warp deformation, reduce the hidden of silicon chip in processing procedure and split rate and fragment rate；
(8) phosphoric acid is sprayed：In the phosphoric acid of front side of silicon wafer even application 5% and the mixed solution of alcohol, heat is used after spraying Nitrogen is dried；
(9) laser doping：Front side of silicon wafer is heated using the laser of wavelength 355nm or 532nm, silicon chip is made to be heated to Molten condition, while laser heats silicon chip surface and slots, the phosphorus atoms in phosphoric acid incorporate in the silicon of molten condition, when sharp After melt region is removed, this region begins to cool and recrystallizes light hot spot, and phosphorus atoms and the silicon of involvement form alloy, form phase The N answered+Layer obtains the main gate line after laser doping and secondary grid line, 12 μm of the width of grid line 5；
(10) nickel copper/silver electrode is electroplated in photoinduction：The carrier generated under illumination condition using battery, and be aided with outer Power supply is set, anode metal is made to dissolve, metal ion is dissociated by electrolyte solution to the front gate line in cathodic region, that is, battery Place deposits, the metal grid lines that silk-screen printing is formed in the i.e. alternative traditional handicraft of these metal grid lines plated；Step includes：Acid Wash → photoinduction nickel plating → washing → photoinduction copper facing → washing → photoinduction is silver-plated → washing → drying, silicon chip surface illumination is strong Spend 15000lux, 1 μm of nickel layer thickness, 10 μm of copper layer thickness, 4 μm of silver thickness；
(11) it anneals：Battery after plating is placed in nitrogen or the chain-type sintering furnace of nitrogen and hydrogen mixture atmosphere and is moved back Fire reduces nisiloy contact resistance, increases the binding force between metal grid lines and silicon, between metal and metal；Annealing temperature 300 DEG C, annealing time 8 minutes.
Embodiment 2：A kind of preparation method of the black policrystalline silicon PERC battery structures of selective emitter, includes the following steps：
(1) one texture-etching side：Include the following steps：Load → alkali throwing → pickling → heavy silver → borehole → the desilverization → reaming → alkali → pickling → fragment → pickling → washing → drying is washed, nanometer suede is prepared in front side of silicon wafer, and the back side is burnishing surface, nanometer suede Face diameter 550nm or so, reflectivity 17%；
(2) it spreads：Existed using phosphorus oxychloride in diffusion furnace at a temperature of 880 DEG C using the method for tube furnace phosphorus diffusion The front of silicon chip carries out phosphorus diffusion and forms N-type layer, 130 Ω of diffusion rear surface square resistance/；
(3) it etches：Etching method is protected using moisture film, removes front side of silicon wafer phosphorosilicate glass and back side pn-junction, etches Reducing thickness 0.08g；
(4) plated film：In front side of silicon wafer deposited silicon nitride antireflection film layer, film thickness 79nm, refractive index 2.03；In silicon chip back side Depositing Al Ox/SiNxOverlayer passivation dielectric layer, aluminium oxide film thickness 15nm, silicon nitride film thickness 150nm；
(5) backside laser opens a window：It is overleaf got ready using laser, puts spacing 0.8mm, 200 μm of spot diameter, dislocation point Cloth forms equilateral triangle；
(6) silk-screen printing：Overleaf silk-screen printing silver electrode and aluminium paste；
(7) it is sintered：Local Al-BSF is formed using 650 DEG C of sintering of chain-type sintering furnace；
(8) phosphoric acid is sprayed：In the phosphoric acid solution of front side of silicon wafer even application 3%, dried using hot nitrogen after spraying；
(9) laser doping：Using wavelength 355nm ultraviolet laser to front side of silicon wafer carry out phosphorus doping, 8 μm of grid line width, Grating spacing 1.0mm；
(10) nickel copper/silver electrode is electroplated in photoinduction：Step includes：Pickling → photoinduction nickel plating → washing → photoinduction plating Copper → washing → photoinduction is silver-plated → washing → drying；Silicon chip surface intensity of illumination 15000lux, 1 μm of nickel layer thickness, layers of copper are thick 13 μm of degree, 2 μm of silver thickness；
(11) it anneals：Battery after plating is placed in nitrogen chain-type sintering furnace and is annealed, 350 DEG C of annealing temperature, annealing 5 minutes time.
The black policrystalline silicon PERC battery electrical properties that table 1 is obtained using embodiment 1
Embodiment 3：A kind of preparation method of the black policrystalline silicon PERC battery structures of selective emitter, includes the following steps：
(1) one texture-etching side：Include the following steps：Load → alkali throwing → pickling → heavy silver → borehole → the desilverization → reaming → alkali → pickling → fragment → pickling → washing → drying is washed, nanometer suede is prepared in front side of silicon wafer, and the back side is burnishing surface, is prepared into The nanometer suede aperture 400nm arrived, reflectivity 15%；
(2) it spreads：Existed using phosphorus oxychloride in diffusion furnace at a temperature of 890 DEG C using the method for tube furnace phosphorus diffusion The front of silicon chip carries out phosphorus diffusion and forms N-type layer, 140 Ω of diffusion rear surface square resistance/；
(3) it etches：Remove front side of silicon wafer phosphorosilicate glass and back side pn-junction, etching Reducing thickness 0.07g；
(4) plated film：In front side of silicon wafer deposited silicon nitride antireflection film layer, film thickness 80nm, mean refractive index 2.01；In silicon chip Backside deposition AlOx/SiNxOverlayer passivation dielectric layer, aluminium oxide film thickness 10nm, silicon nitride film thickness 180nm；
(5) backside laser opens a window：Using laser overleaf routing, make AlOx/SiNx overlayer passivations dielectric layer from silicon chip Sur-face peeling, lines spacing 0.9mm, line width 40um, line segment are dislocatedly distributed；
(6) silk-screen printing：Overleaf silk-screen printing silver electrode and aluminium paste；
(7) it is sintered：Using 630 DEG C of low-temperature sinterings of chain-type sintering furnace, aluminium paste forms part with the pasc reaction at laser windowing Al-BSF；
(8) phosphoric acid is sprayed：In the phosphoric acid solution of front side of silicon wafer even application 8%, dried using hot nitrogen after spraying；
(9) laser doping：Phosphorus doping, 10 μm of grid line width are carried out to front side of silicon wafer using the laser of wavelength 532nm；
(10) nickel copper/silver electrode is electroplated in photoinduction：Step includes：Pickling → photoinduction nickel plating → washing → photoinduction plating Copper → washing → photoinduction is silver-plated → washing → drying；Silicon chip surface intensity of illumination 20000lux, nickel layer is 2 μm thick, copper layer thickness 15 μm, 3 μm of silver thickness；
(11) it anneals：Battery after plating is placed in the chain-type sintering furnace of nitrogen and hydrogen mixture atmosphere and is annealed, annealing temperature 450 DEG C of degree, annealing time 3 minutes.

Claims (7)

1. a kind of preparation method of the black policrystalline silicon PERC battery structures of selective emitter, characterized in that include the following steps：
（1）Nanometer suede is formed in front side of silicon wafer, silicon chip back side is burnishing surface；
（2）Diffusion：Phosphorus diffusion is carried out in the front of silicon chip and forms N-type layer, and diffusion rear surface square resistance is 120-140 Ω/；
（3）Remove front side of silicon wafer phosphorosilicate glass and back side pn-junction；
（4）Plated film：In front side of silicon wafer deposited silicon nitride antireflection film layer, in silicon chip back side depositing Al Ox/SiNxOverlayer passivation medium Layer；
（5）It is got ready or routing in silicon chip back side using laser, makes AlOx/SiNxOverlayer passivation dielectric layer is shelled from silicon chip surface From；
（6）Silk-screen printing：Overleaf silk-screen printing silver electrode and aluminium paste；
（7）Sintering：Carrying out low-temperature sintering makes aluminium paste form local Al-BSF with the pasc reaction at laser windowing, and sintering temperature is 600-650℃；
（8）Spray phosphoric acid：It is dry using hot nitrogen after spraying in the mixed solution of the phosphoric acid and alcohol of front side of silicon wafer even application 3-8% It is dry；
（9）Laser doping：Front side of silicon wafer is heated using laser, forms main gate line and secondary grid line；
（10）Nickel copper/silver electrode is electroplated in photoinduction：Front side of silicon wafer is immersed into electroplating solution, to front side of silicon wafer under illumination condition It is electroplated, deposition plates metal grid lines, silicon chip surface intensity of illumination 15000-20000lux, nickel at the front gate line of silicon chip 1-2 μm of layer thickness, 10-15 μm of copper layer thickness, 2-4 μm of silver thickness；
（11）Annealing.
2. the preparation method of the black policrystalline silicon PERC battery structures of selective emitter as described in claim 1, it is characterized in that：Institute State step（1）The nanometer suede aperture 200-700nm being prepared, reflectivity 14-18%.
3. the preparation method of the black policrystalline silicon PERC battery structures of selective emitter as described in claim 1, it is characterized in that：Institute State step（2）In, in diffusion furnace at a temperature of 880 DEG C, phosphorus diffusion is carried out in the front of silicon chip using phosphorus oxychloride and forms N-type Layer.
4. the preparation method of the black policrystalline silicon PERC battery structures of selective emitter as described in claim 1, it is characterized in that：Institute State step（4）In, the thickness of silicon nitride anti-reflecting film is 75-85nm, mean refractive index 2.04-2.14；Aluminum oxide film thickness For 10-30nm, refractive index 1.55-1.70, silicon nitride film thickness is 120-200nm, refractive index 1.90-2.20.
5. the preparation method of the black policrystalline silicon PERC battery structures of selective emitter as described in claim 1, it is characterized in that：Institute State step（5）When middle progress routing, lines spacing is 0.7-0.9mm, line width 40-60um；When getting ready, point spacing is 0.6- 0.8mm, spot diameter 200um.
6. the preparation method of the black policrystalline silicon PERC battery structures of selective emitter as described in claim 1, it is characterized in that：Institute State step（9）For the middle optical maser wavelength used for 355nm or 532nm, the grid line width of formation is 8-12 μm.
7. the preparation method of the black policrystalline silicon PERC battery structures of selective emitter as described in claim 1, it is characterized in that：Institute State step（11）In, silicon chip is annealed in nitrogen or nitrogen and hydrogen mixture atmosphere, and annealing temperature is 300-450 DEG C, when annealing Between 3-8 minutes.
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