CN218513468U - Smooth-faced tunneling type heterojunction solar cell - Google Patents

Abstract

The utility model belongs to the technical field of solar cells, and relates to a faceting surface tunneling type heterojunction solar cell, which comprises a first electrode, a first conductive film layer, an N-type microcrystalline silicon lamination layer, an N-type polycrystalline silicon layer, a tunneling oxide layer, a semiconductor substrate, an intrinsic film layer, a P-type semiconductor film layer, a second conductive film layer and a second electrode which are sequentially overlapped from the faceting surface to the shady surface; the N-type microcrystalline silicon stack includes one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers a. An object of the utility model is to provide a to plain noodles tunnelling type heterojunction solar cell, the TOPCON technique that the plain noodles adopted N type micrite silicon stromatolite stack tunneling oxide layer and N type polycrystalline silicon layer to constitute has that the passivation is effectual, the good characteristics of electric conductivity, has both guaranteed open circuit voltage, the fill factor of battery, has compensatied the not enough of positive polycrystal extinction again.

Description

Smooth-faced tunneling type heterojunction solar cell

Technical Field

The utility model belongs to the technical field of solar cell, a to plain noodles tunnelling type heterojunction solar cell is related to.

Background

The heterojunction solar cell is more and more favored by the photovoltaic industry because of having the advantages of high conversion efficiency, low process temperature, high stability, low attenuation rate and the like, and is the future development direction of the high conversion efficiency solar cell.

The heterojunction technology has simple process flow, higher conversion efficiency and higher comprehensive power generation capacity, has the attenuation speed far lower than that of a PERC battery, has larger development potential, but the used plate type PECVD coating equipment of amorphous silicon or microcrystalline silicon is relatively expensive, the comprehensive cost of the equipment has no larger advantage than that of the PERC battery, the production technology needs to be improved, the investment of equipment fixed assets is further reduced, and the purpose of large market competitiveness of the comprehensive investment is achieved.

Disclosure of Invention

An object of the utility model is to provide a to plain noodles tunnelling type heterojunction solar cell, the TOPCON technique that the plain noodles adopted N type micrite silicon stromatolite stack tunneling oxide layer and N type polycrystalline silicon layer to constitute has that the passivation is effectual, the good characteristics of electric conductivity, has both guaranteed open circuit voltage, the fill factor of battery, has compensatied the not enough of positive polycrystal extinction again.

The purpose of the utility model is realized through the following technical scheme:

a light facing tunneling heterojunction solar cell comprises a first electrode, a first conductive film layer, an N-type microcrystalline silicon lamination layer, an N-type polycrystalline silicon layer, a tunneling oxide layer, a semiconductor substrate, an intrinsic film layer, a P-type semiconductor film layer, a second conductive film layer and a second electrode which are sequentially stacked from a light facing surface to a backlight surface; the N-type microcrystalline silicon stack includes one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers.

Compare prior art, the utility model has the advantages of:

1. the N-type oxygen-containing microcrystalline silicon layer is introduced to the TOPCON film layer on the light-facing surface, so that the optical energy gap of the front surface is widened, the problem that the TOPCON film layer is easy to absorb light on the front surface is solved, and the short-circuit current is ensured.

2. The TOPCON technology composed of the light-facing surface tunneling oxide layer and the N-type polycrystalline silicon layer has the characteristics of good passivation effect and good conductivity, and not only ensures the open-circuit voltage of the battery, but also promotes the filling factor of the battery.

3. An oxygen-containing microcrystalline silicon film layer is introduced into the light facing surface, so that the defect that the polycrystalline film layer on the suede is too thin and is easy to cause PVD (physical vapor deposition) sputtering damage is overcome, and the open-circuit voltage is ensured.

4. The utility model discloses well oxygen-containing microcrystalline silicon layer need not like deposit oxygen-containing microcrystalline silicon layer on the intrinsic amorphous silicon layer, needs deposit one deck in advance and incubate the layer, just enables the quick micrite of oxygen-containing microcrystalline layer, the utility model discloses well oxygen-containing microcrystalline layer can directly be quick crystallization on the polycrystal layer, has the film forming rate height, the good characteristics of electric conductive property.

5. Because the TOPCON film layer is used for partially replacing the N-type amorphous silicon layer of the traditional heterojunction, the equipment investment of plate type PECVD is reduced, and the total cost of heterojunction solar cell production equipment can be greatly reduced.

Drawings

FIG. 1 is a schematic cross-sectional view of a silicon wafer after double-sided etching and cleaning in an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of a silicon wafer after sequentially forming a tunneling oxide layer and a first intrinsic polysilicon layer on the surface of the silicon wafer according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of the silicon wafer after the first intrinsic polycrystalline layer is converted into an N-type polycrystalline silicon layer by high temperature diffusion and a phosphosilicate glass layer is formed on the surface of the N-type polycrystalline silicon layer in the embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of a silicon wafer with a phosphosilicate glass layer removed from the surface thereof according to an embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view after depositing an N-type microcrystalline silicon stack on the front side of a silicon wafer in an embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view of a silicon wafer after a silicon nitride protective layer is deposited on the front surface of the silicon wafer according to an embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of the embodiment of the present invention, which removes the first intrinsic polysilicon layer, the tunneling oxide layer and the pyramid matte on the back side of the silicon wafer by polishing and cleaning.

Fig. 8 is a schematic cross-sectional view of a silicon wafer with a front silicon nitride protective layer removed according to an embodiment of the present invention.

Fig. 9 is a schematic cross-sectional view of the embodiment of the present invention after a second intrinsic amorphous silicon layer and a P-type semiconductor film layer are sequentially deposited on the back surface of the silicon wafer.

Fig. 10 is another schematic cross-sectional view of the embodiment of the present invention after a second intrinsic amorphous silicon layer and a P-type semiconductor film layer are sequentially deposited on the back surface of the silicon wafer.

Fig. 11 is a schematic cross-sectional view after forming a transparent conductive layer and a metal gate line electrode on the front and back surfaces of a silicon wafer according to an embodiment of the present invention.

Description of reference numerals: 1. a silicon wafer, 2, a tunneling oxide layer, 3a, a first intrinsic polycrystalline silicon layer, 3b, an N-type polycrystalline silicon layer, 3c, a phosphorosilicate glass layer, 4a, an oxygen-containing microcrystalline layer, 4b, a non-oxygen-containing microcrystalline layer, 5, a silicon nitride protection layer, 6, a second intrinsic amorphous silicon layer, 7, a P-type semiconductor film layer, 7a, a non-oxygen-containing incubation layer, 7b, an oxygen-containing P-type microcrystalline layer, 7c, a non-oxygen-containing P-type microcrystalline layer; 8. transparent conducting layer, 9, metal grid line electrode.

Detailed Description

A light facing tunneling type heterojunction solar cell comprises a first electrode, a first conductive film layer, an N-type microcrystalline silicon lamination layer, an N-type polycrystalline silicon layer, a tunneling oxide layer, a semiconductor substrate, an intrinsic film layer, a P-type semiconductor film layer, a second conductive film layer and a second electrode which are sequentially overlapped from a light facing surface to a backlight surface; the N-type microcrystalline silicon stacked layer includes one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers. The N-type microcrystalline silicon lamination layer and the N-type polycrystalline silicon layer jointly form an N-type semiconductor film layer.

The semiconductor substrate is a monocrystalline silicon wafer, a pyramid suede is arranged on the light facing surface of the semiconductor substrate, and the backlight surface of the semiconductor substrate is a chemical polishing surface.

The thickness of the tunneling oxide layer is 1-2nm; the thickness of the N-type polycrystalline silicon layer is 15-50nm, and the sheet resistance is 80-300 omega/\9633.

The intrinsic film layer is a hydrogenated intrinsic amorphous silicon layer and has the thickness of 3-12nm; the P-type semiconductor film layer is a P-type amorphous silicon layer or a P-type microcrystalline laminated layer, and the thickness of the P-type semiconductor film layer is 9-45nm.

The conductive doping concentration of the P-type microcrystalline lamination layer and the N-type semiconductor film layer is 10 ¹⁹ -10 ²¹ cm ^-3 。

The first conductive film layer and/or the second conductive film layer are/is a transparent conductive film layer. The transparent conductive film layer is one film layer or a combination of more than two film layers of Indium Tin Oxide (ITO), tungsten-doped indium oxide (IWO), gallium-doped zinc oxide (IGZO), aluminum-doped zinc oxide (AZO), zinc-doped indium oxide (IZO), gallium-doped zinc oxide (GZO) and titanium-doped indium oxide (ITIO).

The thickness of the first conductive film layer is 60-110nm; the thickness of the second conductive film layer is 15-50nm.

In the N-type microcrystal lamination, the total thickness of the oxygen-containing microcrystal layer is 5-20nm, and the total thickness of the non-oxygen-containing microcrystal layer is 5-20nm.

The N-type microcrystal laminated layer comprises an oxygen-containing microcrystal layer and a non-oxygen-containing microcrystal layer which are sequentially laminated from a light facing surface to a backlight surface, and the film thickness ratios of the oxygen-containing microcrystal layer to the non-oxygen-containing microcrystal layer are (0.5-1.5): 1.

and each film layer of the N-type microcrystal lamination is formed by depositing by increasing the ratio of N-type doping gas to silane stage by stage.

The invention is described in detail below with reference to the drawings and examples:

fig. 1 to 11 are schematic diagrams illustrating an embodiment of a method for manufacturing a light-facing tunneling-type heterojunction solar cell according to the present invention.

Example 1

A manufacturing method of a light facing surface tunneling type heterojunction solar cell comprises the following specific steps:

(1) Carrying out double-sided texturing on the N-type monocrystalline silicon wafer or the N-type ingot silicon wafer 1, wherein the texturing time is 8-40 minutes, and the texturing temperature is 65-85 ℃. The texturing solution is an alkaline mixed solution and is a mixed solution of potassium hydroxide, a texturing additive and water, wherein the mass percentage of the potassium hydroxide is 1-5%, and the mass percentage of the texturing additive is 0.5-1%. And (2) double-sided polishing, namely removing a wire-electrode cutting damage layer on the surface of the silicon wafer by using an alkaline solution, wherein the alkaline solution can be potassium hydroxide, sodium hydroxide or a mixed solution of the potassium hydroxide and the sodium hydroxide, the reaction temperature of the alkaline solution is generally 65-90 ℃, the reaction time is 1-15min, the thickness of the single-sided removal is controlled to be 1-20 mu m, and then standard RCA cleaning is carried out to remove the alkaline solution remained on the surface of the silicon wafer (as shown in figure 1).

(2) Oxidizing the surface of the silicon wafer 1 after double-sided texturing to sequentially form a tunneling oxide layer 2 and a first intrinsic polycrystalline silicon layer 3a (as shown in fig. 2), wherein the surface oxidation can be performed by using a nitric acid solution oxidation, ozone oxidation or thermal oxidation, preferably, the utility model discloses in a tubular LPCVD equipment, the thermal oxidation is performed for 30min at 550-650 ℃ to form the tunneling oxide layer 2 with the thickness of 1.2-2.0nm, and the tunneling oxide layer is an ultrathin silicon oxide layer; the ultrathin silicon oxide layer can also be formed by vacuum plasma-assisted oxidation; the formation of the first intrinsic polysilicon layer 3a and the formation of the tunnel oxide layer 2 are performed in the same tube LPCVD, preferably, after thermal oxidation, gas is evacuated, and gas such as silane is introduced to perform the growth of the first intrinsic polysilicon layer 3a, the growth temperature is controlled to be 550-650 ℃, the gas pressure is controlled to be 5-10000pa, and the thickness of the first intrinsic polysilicon layer 3a can be 15-50nm. The first intrinsic polysilicon layer may also be deposited by Plasma Enhanced CVD (PECVD) in combination with a subsequent high temperature anneal. The first intrinsic polycrystalline silicon layer can also be used for preparing a film by sputtering a silicon target material through physical vapor deposition, and then polycrystalline silicon is formed through a subsequent high-temperature annealing mode.

(3) And (3) performing high-temperature diffusion on the silicon wafer with the oxidized and grown polysilicon film to perform phosphorus doping on the first intrinsic polysilicon layer 3a to form an N-type polysilicon layer 3b (as shown in figure 3), wherein the diffusion temperature is 780-950 ℃, and the sheet resistance of the diffused silicon wafer is 80-300 omega/\9633. The N-type doping of the polysilicon may also be performed by in-situ doping (i.e., introducing a gas containing a phosphorus source into the atmosphere of the gas for preparing the polysilicon). By adopting the in-situ doping, the subsequent furnace tube type PSG glass high-temperature diffusion can be avoided.

(4) The phosphosilicate glass layer 3c (phosphosilicate glass layer, PSG) formed on the surface of the silicon wafer 1 after high temperature diffusion is removed (see fig. 4), and the cleaning solution used for the removal is a chemical solution containing fluoride ions (e.g., a diluted hydrofluoric acid or fluorine-containing acidic solution such as BOE solution). If hydrofluoric acid solution is adopted, the mass percent of HF acid is 0.5-8%, the treatment time of the silicon wafer in the HF acid solution is 1-6 minutes, and the treatment temperature is 20-30 ℃.

(5) Depositing an N-type microcrystalline silicon stack (as shown in fig. 5) on the polycrystalline layer on the front side of the silicon wafer, wherein the N-type microcrystalline silicon stack is formed by an oxygen-containing microcrystalline layer 4a and a non-oxygen-containing microcrystalline layer 4b which are sequentially deposited by a PECVD deposition method, each film layer of the N-type microcrystalline stack is deposited by a process method of increasing the ratio of N-type doping gas to silane stage by stage, and the ratio of N-type doping gas to silane is increased from 1; the oxygen-containing microcrystalline layer 4a and the non-oxygen-containing microcrystalline layer 4b have film thickness ratios of 1: (0.5-1.5). The utility model discloses well oxygen-containing microcrystalline layer is direct to deposit on polycrystalline silicon, need not like the intrinsic amorphous silicon layer on the oxygen-containing microcrystalline silicon layer of deposit, need deposit one deck in advance and incubate the layer, just enable the quick micrite of oxygen-containing microcrystalline layer, the utility model discloses well polycrystalline silicon layer self crystallinity is high for oxygen-containing microcrystalline silicon can quick crystallization, has the film forming rate height, the good characteristics of electric conductive property.

(6) Depositing a silicon nitride protective layer 5 (as shown in fig. 6) on the front surface of the silicon wafer, wherein the silicon nitride protective layer has a strong corrosion resistance to alkaline solution, and can resist alkaline corrosion in the wool making solution, preferably, the silicon nitride has a thickness

The silicon nitride layer may be formed by a thin film formation method such as a sputtering method or a CVD method, and is preferably deposited by a PECVD method in this embodiment.

(7) And (3) removing the N-type polycrystalline silicon layer and the tunneling oxide layer on the back surface of the silicon wafer (as shown in fig. 7), wherein the solution for removing the N-type polycrystalline silicon layer and the tunneling oxide layer is alkaline solution, and the silicon nitride protective layer 5 is arranged on the front surface of the silicon wafer, so that the N-type polycrystalline silicon layer and the pyramid textured structure are still kept on the front surface of the silicon wafer in the solution, and the N-type polycrystalline silicon layer and the tunneling oxide layer on the back surface of the silicon wafer are removed. Preferably, in this embodiment, the pyramid textured surface on the back surface of the silicon wafer is also removed to form a flat surface morphology, the alkali solution is potassium hydroxide, sodium hydroxide or a mixed solution of potassium hydroxide and sodium hydroxide, and preferably, a solution of potassium hydroxide and water is used, wherein the mass percentage content of potassium hydroxide is 10% to 30%, the polishing time is 1 to 10 minutes, and the polishing temperature is 65 ℃ to 85 ℃.

(8) Removing the silicon nitride protective layer 5 (as shown in fig. 8) on the front surface of the silicon wafer, wherein the solution used for removing the protective layer is a chemical solution (such as diluted hydrofluoric acid or BOE solution) containing fluoride ions, and the removal time is determined according to the corrosion resistance of the silicon nitride;

(9) Depositing a second intrinsic amorphous silicon layer 6 and a P-type semiconductor film layer 7 on the polished surface of the back surface of the silicon wafer in sequence, wherein the P-type semiconductor film layer 7 is a P-type amorphous silicon layer (as shown in fig. 9); the second intrinsic amorphous silicon layer is formed by a PECVD (plasma enhanced chemical vapor deposition) method, the deposition temperature is 150-300 ℃, mixed gas of silane, hydrogen or carbon dioxide is introduced into the reaction cavity, wherein the molar content of the silane is 5-100%, and the thickness of the second intrinsic amorphous silicon layer is 3-6nm; and depositing the P-type amorphous silicon layer by adopting a PECVD deposition method, and introducing silane, hydrogen and diborane doping gas for deposition, wherein the deposition thickness is 5-15nm.

(10) Depositing transparent conductive layers 8 (i.e. a first conductive film layer and a second conductive film layer) on the front and back surfaces of the silicon wafer, wherein the transparent conductive layers 8 are typically transparent conductive oxide layers, and the transparent conductive layers 8 may be indium oxide films doped with one or more different metals (e.g. tin, tungsten, titanium, etc.), such as ITO, IWO, ITiO, etc.; or zinc oxide film layer containing one or more different metal doping (such as aluminum, indium, gallium, etc.), such as AZO, GZO, IZO, IGZO, etc. Preferably, ITO (namely an indium oxide film layer doped with tin) is used, the ITO layer is generally deposited by adopting a PVD (physical vapor deposition) mode, the transmittance of the film layer is controlled to be between 88 and 99 percent, the square resistance is 30 to 400 omega/\ 9633, and the film thickness is 15 to 150nm.

(11) Metal gate line electrodes 9 (i.e. a first metal electrode and a second metal electrode) are formed on the front and back surfaces of the silicon wafer (see fig. 10), so as to facilitate the subsequent IV test.

Example 2

The embodiment 2 of the present invention is different from the embodiment 1 only in the step (9): in step (9) of this embodiment, a second intrinsic amorphous silicon layer 6 and a P-type semiconductor film layer 7 are sequentially deposited on the polished surface of the back surface of the silicon wafer, where the P-type semiconductor film layer 7 is a P-type microcrystalline stack including a non-oxygen-containing incubation layer 7a, an oxygen-containing P-type microcrystalline layer 7b, and a non-oxygen-containing P-type microcrystalline layer 7c (as shown in fig. 10), and the film thickness ratios thereof are (0.15-0.6): 1: (0.5-1.5); the second intrinsic amorphous silicon layer is formed by a PECVD (plasma enhanced chemical vapor deposition) method, the deposition temperature is 150-300 ℃, mixed gas of silane, hydrogen or carbon dioxide is introduced into the reaction cavity, wherein the molar content of the silane is 5-100%, and the thickness of the second intrinsic amorphous silicon layer is 3-11nm; and depositing the P-type microcrystal laminated layer by adopting a PECVD (plasma enhanced chemical vapor deposition) method, and introducing silane, hydrogen, carbon dioxide and diborane doping gas for deposition, wherein the deposition thickness is 5-25nm.

The above description is only the preferred embodiment 2 of the present invention, and the scope of the present invention is not limited thereby.

The table above shows the process parameters of each stage of the P-type microcrystalline lamination prepared by PECVD, and the prepared P-type microcrystalline lamination contains three stages of P1, P2 and P3. In a preferred scheme, each film layer of the P-type microcrystalline lamination is deposited by adopting a process mode of increasing the ratio of P-type doping gas to silane stage by stage, wherein the ratio of the P-type doping gas to the silane is increased from 1.

It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (8)

1. A light facing tunneling heterojunction solar cell, comprising: the thin film transistor comprises a first electrode, a first conductive film layer, an N-type microcrystalline silicon lamination layer, an N-type polycrystalline silicon layer, a tunneling oxide layer, a semiconductor substrate, an intrinsic film layer, a P-type semiconductor film layer, a second conductive film layer and a second electrode which are sequentially overlapped from a light facing surface to a backlight surface; the N-type microcrystalline silicon stack includes one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers.

2. The light-facing tunneling-type heterojunction solar cell of claim 1, wherein: the semiconductor substrate is a monocrystalline silicon wafer, a pyramid suede is arranged on the light facing surface of the semiconductor substrate, and the backlight surface of the semiconductor substrate is a chemical polishing surface.

3. The light-facing tunneling-type heterojunction solar cell of claim 1, wherein: the thickness of the tunneling oxide layer is 1-2nm; the thickness of the N-type polycrystalline silicon layer is 15-50nm, and the sheet resistance is 80-300 omega/\9633.

4. The faceting tunneling-type heterojunction solar cell of claim 1, wherein: the intrinsic film layer is a hydrogenated intrinsic amorphous silicon layer and has the thickness of 3-12nm; the P-type semiconductor film layer is a P-type amorphous silicon layer or a P-type microcrystalline lamination, and the thickness of the P-type semiconductor film layer is 9-45nm.

5. The light-facing tunneling-type heterojunction solar cell of claim 1, wherein: the first conductive film layer and/or the second conductive film layer are/is a transparent conductive film layer; the transparent conductive film layer is one film layer or a combination of more than two film layers of indium tin oxide, tungsten-doped indium oxide, gallium-doped zinc-doped indium oxide, aluminum-doped zinc oxide, zinc-doped indium oxide, gallium-doped zinc oxide and titanium-doped indium oxide.

6. The light-facing tunneling-type heterojunction solar cell of claim 5, wherein: the thickness of the first conductive film layer is 60-110nm; the thickness of the second conductive film layer is 15-50nm.

7. The facetted tunneling-type heterojunction solar cell of any of claims 1-6, wherein: in the N-type microcrystal lamination, the total thickness of the oxygen-containing microcrystal layer is 5-20nm, and the total thickness of the non-oxygen-containing microcrystal layer is 5-20nm.

8. The faceting tunneling-type heterojunction solar cell of claim 7, wherein: the N-type microcrystal laminated layer comprises a non-oxygen-containing microcrystal layer and an oxygen-containing microcrystal layer which are sequentially laminated from a light facing surface to a backlight surface, and the corresponding film thickness proportion is (0.5-1.5): 1.

Images