CN115172481B - Heterojunction solar cell - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
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- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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Abstract
The invention belongs to the technical field of solar cells, and relates to a heterojunction solar cell, which comprises a first electrode, a first conductive film layer, a P-type microcrystal lamination layer, an intrinsic film layer, a semiconductor substrate, a tunneling oxide layer, an N-type semiconductor film layer, a second conductive film layer and a second electrode which are sequentially overlapped from a light facing surface to a backlight surface; the P-type microcrystalline stack includes one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers. The invention aims to provide a heterojunction solar cell, the TOPCON technology consisting of a back tunneling oxide layer and an n-doped polycrystalline silicon layer has the characteristics of good passivation effect and good conductivity, meanwhile, a P-type microcrystal lamination layer is adopted on the front surface, an oxygen-containing microcrystal layer is used for enhancing an electrical potential barrier and simultaneously widening an optical energy gap, the open-circuit voltage of the cell is ensured, and the cell filling factor is improved.
Description
Technical Field
The invention belongs to the technical field of solar cells, and relates to a heterojunction solar cell.
Background
With the continuous development of science and technology, solar cells have been widely used in daily life and industry. In recent years, the production technology of solar cells is continuously advanced, the production cost is continuously reduced, the conversion efficiency is continuously improved, and the solar cell power generation is widely applied and becomes an important energy source for power supply.
The silicon-based heterojunction solar cell is an efficient cell technology, integrates the advantages of a monocrystalline silicon solar cell and an amorphous silicon solar cell, and has the characteristics of higher conversion efficiency, good high-temperature characteristic and the like, so that the silicon-based heterojunction solar cell has great market potential.
At present, a passivation layer and a doping layer on the front side and the back side of a silicon-based heterojunction solar cell are deposited by adopting a plate-type Plasma Enhanced Chemical Vapor Deposition (PECVD) device, the deposition temperature is generally less than 220 ℃, in order to reduce the cross contamination of doped elements, a silicon wafer at present generally adopts a back intrinsic amorphous silicon layer, a front intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer and a back P-type doped amorphous silicon layer which are sequentially deposited, 3 sets of plate-type PECVD film coating devices are required to be used, the middle of the silicon wafer needs to enter and exit 3 times in a vacuum chamber, the cost of the high vacuum chamber device is high, and the development of the heterojunction solar cell is seriously hindered.
Disclosure of Invention
The invention aims to provide a heterojunction solar cell, the TOPCON technology consisting of a back tunneling oxide layer and an n-doped polycrystalline silicon layer has the characteristics of good passivation effect and good conductivity, meanwhile, a P-type microcrystal lamination layer is adopted on the front surface, an oxygen-containing microcrystal layer is used for enhancing an electrical potential barrier and simultaneously widening an optical energy gap, the open-circuit voltage of the cell is ensured, and the cell filling factor is improved.
The purpose of the invention is realized by the following technical scheme:
a heterojunction solar cell comprises a first electrode, a first conductive film layer, a P-type microcrystal lamination layer, an intrinsic film layer, a semiconductor substrate, a tunneling oxide layer, an N-type semiconductor film layer, a second conductive film layer and a second electrode which are sequentially laminated from a light facing surface to a backlight surface; the P-type microcrystalline stack includes one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers.
Compared with the prior art, the invention has the advantages that:
1. the TOPCON technology consisting of the back tunneling oxide layer and the N-type semiconductor film layer has the characteristics of good passivation effect and good conductivity, not only ensures the open-circuit voltage of the battery, but also promotes the filling factor of the battery;
2. the front surface adopts a P-type microcrystalline lamination, the oxygen-containing microcrystalline layer is used for enhancing the electrical potential barrier and simultaneously widening the optical energy gap, the high-microcrystalline non-oxygen-containing microcrystalline layer ensures the conductivity, and the defect that the passivation capability and the conductivity cannot be considered by a single P-type amorphous silicon layer is overcome;
3. because the tunneling oxide layer and the N-type semiconductor film layer are used for replacing an amorphous N layer or a microcrystalline N layer of the traditional heterojunction on the back surface, the equipment investment of the flat-plate PECVD is reduced, and the total cost of heterojunction equipment can be greatly reduced.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a high efficiency heterojunction solar cell of the present invention;
FIG. 2 is a schematic cross-sectional view of a silicon wafer after double side polishing and cleaning in an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a silicon wafer with a tunneling oxide layer and a first intrinsic polysilicon layer formed thereon;
FIG. 4 is a schematic cross-sectional view of a silicon wafer after high temperature diffusion to convert the first intrinsic polycrystalline layer into an N-type polycrystalline silicon layer and form a phosphosilicate glass layer on the surface thereof according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a silicon wafer with a phosphorosilicate glass layer removed from a surface thereof according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view after depositing a silicon nitride protective layer on the backside of a silicon wafer in an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of a pyramidal texture formed on the front side of a silicon wafer by texturing and cleaning in an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of a silicon wafer after removal of a silicon nitride protective layer on the backside of the silicon wafer in an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view after sequentially depositing a second intrinsic amorphous silicon layer, a P-type microcrystalline stack on the front side of a silicon wafer in an embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view after forming a highly doped crystallized silicon film layer on the back side of a silicon wafer in an embodiment of the present invention;
FIG. 11 is a schematic cross-sectional view after depositing a transparent conductive layer on the front and back surfaces of a silicon wafer in an embodiment of the present invention;
fig. 12 is a schematic cross-sectional view after forming metal gate line electrodes on the front and back surfaces of a silicon wafer in an embodiment of the present invention;
figure 13 is a flow chart of the fabrication of a high efficiency heterojunction solar cell of the present invention;
fig. 14 is a schematic structural diagram of an embodiment of the high efficiency heterojunction solar cell of the invention.
Description of reference numerals: 1. the structure of the solar cell comprises a silicon wafer, 2, a tunneling oxide layer, 3, a first intrinsic polycrystalline silicon layer, 4, an N-type polycrystalline silicon layer, 4a, a high-doped crystallized silicon film layer, 5, a phosphorosilicate glass layer, 6, a silicon nitride protective layer, 7, a second intrinsic amorphous silicon layer, 8, a P-type microcrystalline laminated layer, 81, a first non-oxygen-containing microcrystalline layer, 82, an oxygen-containing microcrystalline layer, 83, a second non-oxygen-containing microcrystalline layer, 9, a transparent conducting layer, 10 and a metal grid line electrode.
Detailed Description
A heterojunction solar cell comprises a first electrode, a first conductive film layer, a P-type microcrystal lamination layer, an intrinsic film layer, a semiconductor substrate, a tunneling oxide layer, an N-type semiconductor film layer, a second conductive film layer and a second electrode which are sequentially laminated from a light facing surface to a backlight surface; the P-type microcrystalline stack includes one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers. The second conductive film layer covers the N-type semiconductor film layer, and the second electrode is arranged on the surface of the second conductive film layer, so that full-area contact between the conductive film layer and the semiconductor film layer is formed, the transverse flow of current in the semiconductor film layer is avoided, and the conductive capability is improved.
The semiconductor substrate is a monocrystalline silicon wafer, a pyramid suede is arranged on the light facing surface of the semiconductor substrate, and the backlight surface of the semiconductor substrate is a chemical polishing surface.
The intrinsic film layer is a hydrogenated intrinsic amorphous silicon layer and has the thickness of 3-12nm; the thickness of the P-type microcrystal laminated layer is 9-45nm.
The N-type semiconductor film layer is an N-type polycrystalline silicon layer.
The thickness of the tunneling oxide layer is 1-2nm; the thickness of the N-type polycrystalline silicon layer is 20-300nm, and the sheet resistance is 30-200 omega/9633.
And a highly doped crystallized silicon film layer is arranged between the N-type semiconductor film layer and the second conductive film layer. The thickness of the high-doped crystallized silicon film layer is 0.3 to 3nm, and the doping concentration is 1 multiplied by 10 19 -2×10 20 cm -3 . The high-doped crystallized silicon film layer is an N-type doped (such as phosphorus-doped) polycrystal or microcrystal or silicon film in a microcrystal and amorphous mixed state, is formed in a chemical deposition or physical bombardment mode, has an N-type doping rate higher than that of the N-type semiconductor film layer, has a disordered state higher than that of the N-type semiconductor film layer, and is not easy to oxidize. Because the high-doped crystallized silicon film layer is very thin, the high-doped crystallized silicon film layer is generally in a mixed state of three states of polycrystal, microcrystal and mixed state of microcrystal and amorphous. In a preferred scheme, the microcrystallization rate of the high-doped crystallized silicon film layer is controlled to be 10-70%, and N of the high-doped crystallized silicon film layerThe type doping rate is 1-5 times of the N type doping rate of the N type semiconductor film layer.
The conductive doping concentration of the P-type microcrystalline lamination layer and the N-type semiconductor film layer is 10 19 -10 21 cm -3 。
The first conductive film layer and/or the second conductive film layer are/is a transparent conductive film layer. The transparent conductive film layer is one film layer or a combination of more than two film layers of Indium Tin Oxide (ITO), tungsten-doped indium oxide (IWO), gallium-doped zinc oxide (IGZO), aluminum-doped zinc oxide (AZO), zinc-doped indium oxide (IZO), gallium-doped zinc oxide (GZO) and titanium-doped indium oxide (ITIO).
The thickness of the first conductive film layer is 60-110nm; the thickness of the second conductive film layer is 15-50nm.
In the P-type microcrystalline lamination, the thickness of the oxygen-containing microcrystalline layer is 5-20nm, and the thickness of the non-oxygen-containing microcrystalline layer is 5-20nm.
The P-type microcrystal laminated layer comprises a non-oxygen-containing microcrystal layer, an oxygen-containing microcrystal layer and a non-oxygen-containing incubation layer which are sequentially laminated from a light facing surface to a backlight surface, wherein the corresponding film thickness ratio is (0.5-1.5): 1: (0.15-0.6).
And each film layer of the P-type microcrystal lamination is formed by depositing by increasing the ratio of P-type doping gas to silane stage by stage.
The invention is described in detail below with reference to the drawings and examples:
fig. 2 to 13 are schematic diagrams illustrating an embodiment of a heterojunction solar cell according to the present invention.
A manufacturing method of a heterojunction solar cell comprises the following specific steps:
s01, double-sided polishing is carried out on the n-type single crystal or ingot silicon wafer 1, a linear cutting damage layer on the surface of the silicon wafer is removed by using an alkaline solution, the alkaline solution can be potassium hydroxide, sodium hydroxide or a mixed solution of the potassium hydroxide and the sodium hydroxide, the reaction temperature of the alkaline solution is generally 65-90 ℃, the reaction time is 1-15min, the thickness of the single-sided removal is controlled to be 1-20 mu m, and then standard RCA cleaning is carried out to remove the residual metal and organic pollution on the surface of the silicon wafer (as shown in figure 2).
S02, oxidizing the surface of the silicon wafer 1 after double-side polishing, sequentially forming a tunneling oxide layer 2 and growing a first intrinsic polycrystalline silicon layer 3 (as shown in figure 3), wherein the surface oxidation can be performed in a nitric acid solution oxidation, ozone oxidation or thermal oxidation mode, preferably, the invention forms the tunneling oxide layer 2 with the thickness of 1.2-2.0nm by thermal oxidation for 30min at 550-650 ℃ in a tubular LPCVD equipment, and the tunneling oxide layer is an ultrathin silicon oxide layer; the silicon oxide film can also be formed by vacuum plasma-assisted oxidation; the formation of the first intrinsic polysilicon layer 3 and the formation of the tunnel oxide layer 2 are performed in the same tube type LPCVD, preferably, after thermal oxidation, gas is evacuated, and gas such as silane is introduced to perform the growth of the first intrinsic polysilicon layer 3, the growth temperature is controlled to be 550-650 ℃, the gas pressure is controlled to be 5-10000pa, and the thickness of the first intrinsic polysilicon layer 3 can be 20-300nm. The first intrinsic polysilicon layer may also be formed by Plasma Enhanced CVD (PECVD) followed by high temperature annealing. The first intrinsic polycrystalline silicon layer can also be used for preparing a film by sputtering a silicon target material through physical vapor deposition, and then polycrystalline silicon is formed through a subsequent high-temperature annealing mode.
S03, performing high-temperature diffusion on the silicon wafer with the oxidized and grown polycrystalline silicon film to perform phosphorus doping on the first intrinsic polycrystalline silicon layer 3 to form an N-type polycrystalline silicon layer 4 (as shown in figure 4), wherein the diffusion temperature is 780-950 ℃, and the sheet resistance of the silicon wafer after diffusion is 20-200 omega/\9633;. The N-type doping of the polysilicon may also be performed by in-situ doping (i.e., introducing a gas containing a phosphorus source into the atmosphere of the polysilicon preparation gas). The in-situ doping can avoid the subsequent high-temperature diffusion of the furnace tube type PSG glass.
And S04, removing the phosphosilicate glass (PSG) layer 5 (a phosphoric acid-silicon oxide glass layer, PSG) formed on the surface of the silicon wafer 1 after high-temperature diffusion (see fig. 5), wherein the cleaning solution used for removing is a chemical solution containing fluoride ions (such as diluted hydrofluoric acid or a fluorine-containing acidic solution such as a BOE solution). If hydrofluoric acid solution is adopted, the mass percent of HF acid is 0.5-8%, the processing time of the silicon chip in the HF acid solution is 1-6 minutes, and the processing temperature is 20-30 ℃.
S05, depositing a silicon nitride protective layer 6 (i.e., a mask layer) on the back surface of the silicon wafer 1 (see fig. 6), where the silicon nitride protective layer has a property of strong resistance to corrosion by an alkaline solution and can resist alkaline corrosion in a wool making solution, and preferably has a silicon nitride thickness of 700 a-2000 a, and the silicon nitride layer may be formed by a thin film formation method such as a sputtering method or a CVD method, and preferably is formed by deposition by a PECVD method in this embodiment.
S06, performing single-side texturing on the silicon wafer (as shown in figure 7), and texturing the silicon wafer by using an alkaline solution to prepare a texturing additive, wherein a silicon nitride protective layer 6 is arranged on the back side of the silicon wafer, so that a pyramid textured surface is formed on the front side of the silicon wafer after a tunneling oxide layer 2 and a first intrinsic polycrystalline silicon layer on the front side of the silicon wafer are removed in the solution, the texturing solution is a mixed solution of potassium hydroxide, the texturing additive and water, wherein the mass percentage of the potassium hydroxide is 1-5%, and the mass percentage of the texturing additive is 0.5-1%. The texturing time is 8-30 minutes, and the texturing temperature is 65-85 ℃.
And S07, removing the silicon nitride protection layer 6 on the back surface of the silicon wafer (as shown in FIG. 8), wherein the solution for removing the protection layer is a chemical solution (such as diluted hydrofluoric acid or BOE solution) containing fluorine ions, and the removal time is determined according to the corrosion resistance degree of the silicon nitride.
S08, preparing a highly doped crystallized silicon film layer 4a (as shown in figure 9) on the N-type polycrystalline silicon layer 4 on the back surface of the silicon wafer, wherein the thickness of the highly doped crystallized silicon film layer is 0.3-3 nm. Unlike the conventional heterojunction thin film technology, the polysilicon is very easy to form a thin silicon oxide layer at low temperature, the thickness of the thin silicon oxide layer is about 1nm, and the oxide layer exists on the N-type polysilicon layer 4, which is easy to cause the rapid decrease of the conductivity. The intrinsic oxide layer can be deposited and eliminated and a microcrystalline film (namely the high-doping crystallized silicon film layer 4 a) is prepared by adopting the PECVD (plasma enhanced chemical vapor deposition) high-power-density, high-pressure and high-hydrogen-silicon-ratio process, so that the additionally increased contact resistance can be eliminated; the highly doped crystallized silicon film layer 4a may also be prepared by PVD method, in which more than one of argon, hydrogen or ammonia is introduced to remove the silicon oxide thin layer by ion bombardment, and simultaneously, a certain degree of microcrystallization is formed by bombardment, which is helpful to eliminate the contact resistance problem of the second conductive film layer formed later.
S09, sequentially depositing a second intrinsic amorphous silicon layer 7 and a P-type microcrystal laminated layer 8 on the pyramid texture surface of the front surface of the silicon wafer (as shown in a figure 10); the second intrinsic amorphous silicon layer is formed by a PECVD (plasma enhanced chemical vapor deposition) method, the deposition temperature is 150-300 ℃, mixed gas of silane, hydrogen or carbon dioxide is introduced into the reaction cavity, wherein the molar content of the silane is 5-100%, and the thickness of the second intrinsic amorphous silicon layer is 3-11nm; and depositing the P-type microcrystal laminated layer by adopting a PECVD (plasma enhanced chemical vapor deposition) method, and introducing silane, hydrogen, carbon dioxide and diborane doping gas for deposition, wherein the deposition thickness is 5-25nm. In a preferred embodiment, as shown in fig. 14, the P-type microcrystalline stack 8 is composed of a non-oxygen-containing incubation layer 81, an oxygen-containing microcrystalline layer 82, and a non-oxygen-containing microcrystalline layer 83 deposited sequentially by using a PECVD deposition method, each film layer of the P-type microcrystalline stack is deposited by a process of increasing the ratio of P-type doping gas to silane by stages, and the ratio of P-type doping gas to silane is increased from 1; the non-oxygen-containing incubation layer, the oxygen-containing microcrystalline layer and the non-oxygen-containing microcrystalline layer have the corresponding film thickness ratio of (0.15-0.6): 1: (0.5-1.5).
S10, depositing a transparent conductive layer 9 (namely a first conductive film layer positioned on the front side and a second conductive film layer positioned on the back side) on the front side and the back side of the silicon wafer (as shown in FIG. 11), wherein the transparent conductive layer 9 is generally a transparent conductive oxide layer, and the transparent conductive layer 9 can be an indium oxide film layer containing one or more different metal dopings (such as tin, tungsten, titanium and the like), such as ITO, IWO, ITiO and the like; or zinc oxide film layer doped with one or more different metals (such as aluminum, indium, gallium, etc.), such as AZO, GZO, IZO, IGZO, etc. Preferably, ITO (namely an indium oxide film layer containing tin doping) is used, the ITO layer is generally deposited by adopting a PVD (physical vapor deposition) mode, the transmittance of the film layer is controlled to be between 88 and 99 percent, the square resistance is 30 to 400 omega/9633, and the film thickness is 15 to 110nm.
And S11, forming metal grid line electrodes 10 (namely a first metal electrode and a second metal electrode) on the front surface and the back surface of the silicon wafer (as shown in figure 12), so as to facilitate the subsequent IV test.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
The above table shows the process parameters of each stage of the P-type microcrystalline stack 8 prepared by PECVD, where the prepared P-type microcrystalline stack 8 comprises three stages, P1, P2, and P3, and correspondingly forms the non-oxygen-containing incubation layer 81, the oxygen-containing microcrystalline layer 82, and the non-oxygen-containing microcrystalline layer 83.
The table above is a typical electrical comparison a for three photovoltaic cell technologies: topocon technique, B: heterojunction technology, C: the invention relates to a mixed passivation technology.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A heterojunction solar cell, characterized in that: the thin film transistor comprises a first electrode, a first conductive film layer, a P-type microcrystal laminated layer, an intrinsic film layer, a semiconductor substrate, a tunneling oxide layer, an N-type semiconductor film layer, a second conductive film layer and a second electrode which are sequentially stacked from a light facing surface to a backlight surface; the P-type microcrystalline stack comprises more than one oxygen-containing microcrystalline layer and more than one non-oxygen-containing microcrystalline layer; and a highly doped crystallized silicon film layer is arranged between the N-type semiconductor film layer and the second conductive film layer, the microcrystallization rate of the highly doped crystallized silicon film layer is controlled to be 10-70%, and the N-type doping rate of the highly doped crystallized silicon film layer is 1-5 times that of the N-type semiconductor film layer.
2. The heterojunction solar cell of claim 1, wherein: the semiconductor substrate is a monocrystalline silicon wafer, a pyramid suede is arranged on the light facing surface of the semiconductor substrate, and the backlight surface of the semiconductor substrate is a chemical polishing surface.
3. The heterojunction solar cell of claim 1, wherein: the intrinsic film layer is a hydrogenated intrinsic amorphous silicon layer and has the thickness of 3-12nm; the thickness of the P-type microcrystal lamination layer is 9-45nm.
4. The heterojunction solar cell of claim 1, wherein: the N-type semiconductor film layer is an N-type polycrystalline silicon layer.
5. The heterojunction solar cell of claim 4, wherein: the thickness of the tunneling oxide layer is 1-2nm; the thickness of the N-type polycrystalline silicon layer is 20-300nm, and the sheet resistance is 30-200 omega/9633.
6. The heterojunction solar cell of claim 1, wherein: the thickness of the high-doping crystallized silicon film layer is 0.3 to 3nm, and the doping concentration is 1 multiplied by 10 19 -2×10 20 cm -3 。
7. The heterojunction solar cell of claim 1, wherein: the first conductive film layer and/or the second conductive film layer are/is a transparent conductive film layer; the transparent conductive film layer is one film layer or a combination of more than two film layers of indium tin oxide, tungsten-doped indium oxide, gallium-doped zinc-doped indium oxide, aluminum-doped zinc oxide, zinc-doped indium oxide, gallium-doped zinc oxide and titanium-doped indium oxide.
8. The heterojunction solar cell of claim 7, wherein: the thickness of the first conductive film layer is 60-110nm; the thickness of the second conductive film layer is 15-50nm.
9. The heterojunction solar cell of any of claims 1-8, wherein: the P-type microcrystal laminated layer comprises a non-oxygen-containing microcrystal layer, an oxygen-containing microcrystal layer and a non-oxygen-containing incubation layer which are sequentially laminated from a light facing surface to a backlight surface, wherein the corresponding film thickness ratio is (0.5-1.5): 1: (0.15-0.6).
10. The heterojunction solar cell of claim 9, wherein: and each film layer of the P-type microcrystal lamination is formed by depositing by increasing the ratio of P-type doping gas to silane stage by stage.
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