CN114613866A - Solar cell and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
Abstract
The application provides a solar cell and a preparation method thereof, wherein the solar cell comprises a silicon substrate, a front electrode and a back electrode which are respectively arranged on two sides of the silicon substrate, wherein a tunneling layer, a doped polycrystalline silicon layer and an antireflection layer are sequentially stacked on the front surface of the silicon substrate, and the front electrode penetrates through the antireflection layer and is in contact with the doped polycrystalline silicon layer; the back surface of the silicon substrate is sequentially provided with an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer in a stacking mode, and the back surface electrode is arranged on the surface of one side, away from the silicon substrate, of the transparent conducting layer. The solar cell and the preparation method thereof can improve the passivation performance of the surface of the cell, reduce the parasitic absorption of the film layer related to the front side of the cell to incident light, increase the utilization rate of the incident light, reduce the defects possibly evolved in a high-temperature process and the high-temperature process by taking the intrinsic amorphous silicon layer and the doped amorphous layer as a back passivation structure, and prolong the service life of the cell.
Description
Technical Field
The application relates to the technical field of solar power generation, in particular to a solar cell and a preparation method thereof.
Background
With the rapid development of the photovoltaic industry, the efficiency requirements of domestic and foreign markets for solar cells and photovoltaic modules are also continuously increased, which also prompts various manufacturers to actively develop and research high-efficiency cells. For crystalline silicon batteries, the improvement of battery performance and conversion efficiency through the innovation of battery structures and related processes is a key issue of continuous attention in the industry.
It is considered in the industry that TOPCon cells and HJT cells are the main technological development routes of crystalline silicon solar cells in the post PERC era. The TOPCon (tunnel Oxide Passivated contact) cell is characterized in that an ultrathin tunneling Oxide layer and a doped polycrystalline silicon layer are prepared on the back surface of the cell to form a passivation contact structure together, so that the surface recombination and the metal recombination of the back surface can be greatly reduced, and the open-circuit voltage Voc and the conversion efficiency of the cell are greatly improved. The Heterojunction (HJT) cell is mainly characterized in that an intrinsic alpha-Si and H layer is deposited on the front surface and the back surface of an n-type silicon wafer, a p-type alpha-Si and H layer and an n-type alpha-Si and H layer are respectively deposited, and then metallization is carried out, so that the Heterojunction (HJT) cell has the advantages of high conversion efficiency, low light attenuation, low temperature coefficient and the like. However, in the preparation process of the doped polysilicon layer, especially the boron doped polysilicon layer, the process temperature is high, which may cause the generation of related defects on the silicon substrate and affect the service life of the battery; the film structure on the surface of the light-absorbing film absorbs light relatively seriously, and the effective absorption of incident light is influenced.
In view of the above, it is necessary to provide a novel solar cell and a method for manufacturing the same.
Disclosure of Invention
The application aims to provide a solar cell and a preparation method thereof, which can improve the surface passivation performance, reduce the light absorption loss, reduce the defects of the cell and ensure the service life of the cell.
In order to achieve the purpose, the application provides a solar cell, which comprises a silicon substrate, a front electrode and a back electrode, wherein the front electrode and the back electrode are respectively arranged on two sides of the silicon substrate; the back surface of the silicon substrate is sequentially provided with an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer in a stacking mode, and the back surface electrode is arranged on the surface of one side, away from the silicon substrate, of the transparent conducting layer.
As a further improvement of the present application, the doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer, and the front electrode is correspondingly disposed on the first doped polysilicon layer; the thickness of the first doped polysilicon layer is greater than that of the second doped polysilicon layer.
As a further improvement of the application, the thickness of the first doped polycrystalline silicon layer is set to be 60-200 nm; the thickness of the second doped polycrystalline silicon layer is set to be 10-50 nm.
As a further improvement of the present application, the first doped polysilicon layer has a doping concentration greater than the doping concentration of the second doped polysilicon layer.
As a further improvement of the application, the doping concentration of the doped polysilicon layer is set to be 5E 18-5E 20cm-3。
As a further improvement of this application, the tunneling layer sets up to silicon oxide film or silicon oxynitride film, the thickness of tunneling layer sets up to 1 ~ 3 nm.
As a further improvement of the application, the antireflection layer comprises a first antireflection layer and a second antireflection layer which are arranged in a stacked mode, the first antireflection layer is set to be a hydrogen-rich silicon nitride film, the thickness of the first antireflection layer is set to be 3-30 nm, and the refractive index is set to be 2.1-2.4; the second antireflection layer is provided as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a composite film composed of at least two of them.
As a further improvement of the application, the thickness of the intrinsic amorphous silicon layer is set to be 5-10 nm.
As a further improvement of the present application, the intrinsic amorphous silicon layer includes a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer stacked on a surface of the first intrinsic amorphous silicon layer facing away from the silicon substrate, and a hydrogen content of the second intrinsic amorphous silicon layer is greater than a hydrogen content of the first intrinsic amorphous silicon layer.
As a further improvement of the application, the thickness of the first intrinsic amorphous silicon layer is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1.
As a further improvement of the application, the thickness of the doped amorphous layer is set to be 5-10 nm; the doping concentration of the doped amorphous layer is 1E 18-5E 20cm-3。
As a further improvement of the present application, the doped amorphous layer includes a first doped amorphous layer and a stacked layer, the first doped amorphous layer deviates from a second doped amorphous layer on one side surface of the silicon substrate, and the doping concentration of the second doped amorphous layer is greater than that of the first doped amorphous layer.
As a further improvement of the application, the thickness of the transparent conducting layer is set to be 70-120 nm.
As a further improvement of the present application, the silicon substrate is an N-type silicon wafer; the doped polycrystalline silicon layer is a phosphorus doped polycrystalline silicon layer, and the doped amorphous layer is a boron doped amorphous layer.
The application also provides a preparation method of the solar cell, which mainly comprises the following steps:
sequentially preparing a tunneling layer, a doped polycrystalline silicon layer and an antireflection layer on the front side of a silicon substrate;
preparing an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer on the back of a silicon substrate in sequence;
grooving in a set area of the antireflection layer;
preparing a front electrode at the grooving position of the antireflection layer;
and preparing a back electrode on the transparent conductive layer.
As a further improvement of the present application, the "notching" refers to removing the anti-reflective layer in a given area by laser etching, so that the doped polysilicon layer is exposed outwards.
As a further improvement of this application, positive electrode and back electrode all adopt low temperature solidification silver thick liquid printing, dry to obtain, and stoving temperature is between 150 ~ 250 ℃.
As a further improvement of the application, the preparation of the doped polysilicon layer comprises depositing a film layer on the surface of the tunneling layer by an LPCVD method or an HWCVD method,and annealing to form an initial doped polysilicon layer, wherein the annealing temperature is 800-950 ℃, and the reaction gas of the film layer comprises SiH4、PH3、H2In which is SiH4、PH3The flow ratio of the two is set to be 1: 0.1-1: 0.001, SiH4、H2The flow ratio of the two is set to be 1: 10-1: 250; or the like, or, alternatively,
depositing an intrinsic silicon film layer on the surface of the tunneling layer by an LPCVD (low pressure chemical vapor deposition) method or a PECVD (plasma enhanced chemical vapor deposition) method, and forming an initial doped polysilicon layer by diffusion, wherein the diffusion adopts a set gaseous phosphorus source or a set solid phosphorus source, and the diffusion temperature is set to be 800-950 ℃.
As a further improvement of the present application, the preparation of the doped polysilicon layer further comprises preparing a mask layer in a partial region of the surface of the initial doped polysilicon layer;
etching part of the initial doped polycrystalline silicon layer in the region where the mask layer is not arranged to obtain a first doped polycrystalline silicon layer corresponding to the mask layer arrangement region and a second doped polycrystalline silicon layer with the thickness smaller than that of the first doped polycrystalline silicon layer, wherein the thickness of the first doped polycrystalline silicon layer is set to be 60-200 nm, and the thickness of the second doped polycrystalline silicon layer is set to be 10-50 nm;
and cleaning and removing the mask layer.
As a further improvement of the present application, the preparation method further includes cleaning the back surface of the silicon substrate after the preparation of the anti-reflection layer is completed, and reserving the tunneling layer, the doped polysilicon layer, and the anti-reflection layer on the side surface of the silicon substrate.
As a further improvement of the present application, the preparation of the intrinsic amorphous silicon layer comprises sequentially depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the back surface of the silicon substrate, wherein the hydrogen content of the second intrinsic amorphous silicon layer is greater than that of the first intrinsic amorphous silicon layer; the preparation of the doped amorphous layer comprises the steps of sequentially depositing a first doped amorphous layer and a second doped amorphous layer on the surface of the second intrinsic amorphous silicon layer, wherein the doping concentration of the second doped amorphous layer is greater than that of the first doped amorphous layer.
As a further improvement of the application, the thickness of the first intrinsic amorphous silicon layer is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1.
As a further improvement of the application, the thickness of the doped amorphous layer is set to be 5-10 nm; the doping concentration of the doped amorphous layer is 1E 18-5E 20cm-3。
As a further improvement of the application, the transparent conducting layer is deposited by a magnetron sputtering method and is obtained by annealing treatment at the temperature of 180-220 ℃.
As a further improvement of the present application, the preparation method further comprises performing light injection or electrical injection treatment after the preparation of the front electrode and the back electrode is completed.
The beneficial effect of this application is: by adopting the solar cell and the preparation method thereof, the passivation structure of the tunneling layer and the doped polycrystalline silicon layer is adopted on the front side of the silicon substrate, so that the passivation performance of the surface of the cell is improved, the parasitic absorption of the film layer related to the front side of the cell to incident light is reduced, and the utilization rate of the incident light is increased; the back surface of the silicon substrate adopts a passivation structure of an intrinsic amorphous silicon layer and a doped amorphous layer, so that the defects which may evolve in a high-temperature treatment process and a high-temperature process are reduced, and the service life of a battery is prolonged.
Drawings
FIG. 1 is a schematic structural diagram of a preferred embodiment of a solar cell of the present application;
FIG. 2 is a schematic structural diagram of another preferred embodiment of a solar cell of the present application;
FIG. 3 is a schematic structural diagram of another preferred embodiment of the solar cell of the present application;
fig. 4 is a schematic main flow chart of a method for manufacturing a solar cell according to the present application.
100-solar cell; 1-a silicon substrate; 2-a tunneling layer; 3-doping a polysilicon layer; 31-a first doped polysilicon layer; 32-a second doped polysilicon layer; 4-an anti-reflection layer; 41-a first anti-reflection layer; 42-a second anti-reflective layer; 5-intrinsic amorphous silicon layer; 51-a first intrinsic amorphous silicon layer; 52-a second intrinsic amorphous silicon layer; 6-doping an amorphous layer; 61-a first doped amorphous layer; 62-a second doped amorphous layer; 7-a transparent conductive layer; 81-front electrode; 82-back electrode.
Detailed Description
The present application will be described in detail below with reference to embodiments shown in the drawings. The present invention is not limited to the above embodiments, and structural, methodological, or functional changes made by one of ordinary skill in the art according to the present embodiments are included in the scope of the present invention.
Referring to fig. 1, a solar cell 100 provided by the present application includes a silicon substrate 1, a tunneling layer 2, a doped polysilicon layer 3, and an anti-reflection layer 4 stacked in sequence on the front surface of the silicon substrate 1, and an intrinsic amorphous silicon layer 5, a doped amorphous layer 6, and a transparent conductive layer 7 stacked in sequence on the back surface of the silicon substrate 1.
The silicon substrate 1 is an N-type silicon wafer, and the resistivity of the silicon substrate 1 is set to be 0.5-7 omega-cm, preferably 1-2 omega-cm. The front side of the silicon substrate 1 is usually subjected to alkali texturing to form a given pyramid textured structure, and the size of the textured structure is set to be 1-5 microns, preferably 2-3 microns. The solar cell 100 further comprises a front electrode 81 and a back electrode 82 which are respectively arranged on the two side surfaces of the silicon substrate 1, wherein the front electrode 81 penetrates through the antireflection layer 4 and is in contact with the doped polysilicon layer 3; the back electrode 82 is disposed on a surface of the transparent conductive layer 7 facing away from the silicon substrate 1.
The tunneling layer 2 is a silicon oxide film or a silicon oxynitride film or a composite film formed by the silicon oxide film and the silicon oxynitride film, the thickness of the tunneling layer 2 is set to be 1-3 nm, and the tunneling layer can be generally prepared by a chemical oxidation method, a thermal oxidation method or an ozone oxidation method. The doped polysilicon layer 3 is a phosphorus doped polysilicon layer, that is, the doped polysilicon layer 3 is an N + layer disposed on the front surface of the silicon substrate 1, and the solar cell 100 is a back junction cell. Antireflection layer 4 can adopt silicon nitride film usually, and thickness sets up to 70 ~ 100nm, and the regulation of technological parameters such as accessible gas flow, reaction time, temperature improves the rete performance and the antireflection effect of antireflection layer 4.
The doped polysilicon layer 3 is doped with a high concentrationThe degree is set to be 5E 18-5E 20cm-3The sheet resistance is set to be 20-100 omega/sq. Here, the doped polysilicon layer 3 includes a first doped polysilicon layer 31 and a second doped polysilicon layer 32 which are adjacently disposed, the thickness of the first doped polysilicon layer 31 is greater than that of the second doped polysilicon layer 32, and the front electrode 81 is correspondingly disposed on the first doped polysilicon layer 31. In other words, the thicker first doped polysilicon layer 31 is disposed under the front electrode 81, so as to ensure passivation performance and prevent the first doped polysilicon layer 31 from being damaged in the subsequent metallization process; the light receiving area on the front surface of the silicon substrate 1 adopts the second doped polysilicon layer 32 with smaller thickness, so that the light absorption loss of the film layer can be effectively reduced, and the effective absorption and conversion of incident light rays are improved. In this embodiment, the thickness of the first doped polysilicon layer 31 is set to be 60 to 200 nm; the thickness of the second doped polysilicon layer 32 is set to be 10-50 nm. In addition, the absorption coefficient of the doped polysilicon layer 3 is greatly influenced by the doping concentration of the doped polysilicon layer, and on the basis of ensuring the passivation performance, the doping concentration of the first doped polysilicon layer 31 can be set to be larger than that of the second doped polysilicon layer 32.
The thickness of the intrinsic amorphous silicon layer 5 is set to be 5-10 nm; the doped amorphous layer 6 refers to a doped amorphous silicon film layer or a doped amorphous silicon oxide film layer. The doped amorphous layer 6 is a boron doped amorphous layer, the thickness of the doped amorphous layer 6 is 5-10 nm, and the doping concentration of the doped amorphous layer 6 is 1E 18-5E 20cm-3Preferably, the doping concentration of the doped amorphous layer 6 is 1E 19-1E 20cm-3. The thickness of the transparent conductive layer 7 is set to be 70-120 nm, the transparent conductive layer 7 is generally referred to as a transparent conductive oxide film layer, and the transparent conductive layer 7 can be set to be an ITO film layer as an example.
In the preparation process of the tunneling layer 2, the doped polysilicon layer 3 and the antireflection layer 4, corresponding film layers are deposited on the side surfaces of the silicon substrate 1. Referring to fig. 2, this embodiment is distinguished from the previous embodiment by the following features: through when the silicon substrate 1 carries out back washing, adjust reaction liquid concentration, combine the control of reaction time and temperature, make it covers the effect to play a certain extent to subtract reflecting layer 4, when realizing back washing, remains the tunneling layer 2, doping polycrystalline silicon layer 3 and the subtracting reflecting layer 4 of silicon substrate 1 side, and then improves the passivation properties of silicon substrate 1 border position.
Referring to fig. 3, in order to further improve the film performance and the battery efficiency, the antireflection layer 4 includes a first antireflection layer 41 and a second antireflection layer 42 which are stacked, the first antireflection layer 41 is configured as a hydrogen-rich silicon nitride film, the thickness of the first antireflection layer is set to be 3 to 30nm, and the refractive index is set to be 2.1 to 2.4; the second antireflection layer 42 is provided as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a composite film composed of at least two of them. Moreover, the antireflection layer 4 may also be provided with a gradual film structure, which is not described in detail herein.
The intrinsic amorphous silicon layer 5 comprises a first intrinsic amorphous silicon layer 51 and a second intrinsic amorphous silicon layer 52 stacked on the surface of the first intrinsic amorphous silicon layer 51 on the side away from the silicon substrate 1, and the hydrogen content of the second intrinsic amorphous silicon layer 52 is greater than that of the first intrinsic amorphous silicon layer 51. Specifically, the thickness of the first intrinsic amorphous silicon layer 51 is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer 52 is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1. Through the design, better passivation effect can be realized.
The doped amorphous layer 6 comprises a first doped amorphous layer 61 and a second doped amorphous layer 62 stacked on the surface of the first doped amorphous layer 61, which is far away from the silicon substrate 1, wherein the doping concentration of the second doped amorphous layer 62 is greater than that of the first doped amorphous layer 61. The inner low-concentration first doped amorphous layer 61 can effectively reduce recombination at the interface, and the outer high-concentration second doped amorphous layer 62 can form a good contact with the transparent conductive layer.
The solar cell 100 combines a heterojunction cell structure with a polycrystalline silicon passivation technology, and production cost is reduced. In addition, the solar cell 100 is designed by the boron-doped amorphous layer, a high-temperature boron diffusion process (950-1050 ℃) is not required, and the crystal defects which may evolve and are generated under the high-temperature condition are avoided. Furthermore, the front electrode 81 and the back electrode 82 are both prepared by low-temperature solidified silver paste, and high-temperature sintering is not needed; the front electrode 81 may be formed by electroplating a metal material such as copper or nickel.
In particular, the silicon substrate 1 may also be a P-type silicon wafer, the doped polysilicon layer 3 is also configured as a phosphorus doped polysilicon layer, and the doped amorphous layer 6 is also configured as a boron doped amorphous layer. At this time, the doped amorphous layer 6 serves as a back P + layer; a corresponding PN junction is formed between the doped polysilicon layer 3 and the silicon substrate 1, which will not be described in detail herein.
Referring to fig. 4, the method for manufacturing the solar cell 100 includes:
providing a silicon substrate 1, and carrying out surface treatment on the silicon substrate 1;
sequentially preparing a tunneling layer 2, a doped polycrystalline silicon layer 3 and an antireflection layer 4 on the front side of a silicon substrate 1;
cleaning the back surface;
preparing an intrinsic amorphous silicon layer 5, a doped amorphous layer 6 and a transparent conducting layer 7 on the back of a silicon substrate 1 in sequence;
grooving in a given area of the antireflection layer 4;
preparing a front electrode 81 at the grooving position of the antireflection layer 4, so that the front electrode 81 penetrates through the antireflection layer 4 and is in contact with the doped polysilicon layer 3;
a back electrode 82 is prepared on the transparent conductive layer 7.
The surface treatment step comprises the steps of firstly carrying out double-sided alkaline texturing on the silicon substrate 1 by using KOH or NaOH or TMAH aqueous solution, and controlling the pyramid height on the surface of the silicon substrate 1 to be 1-5 microns, preferably 2-3 microns. In actual production, a given texturing additive can be added into the solution to improve the texture quality of the silicon substrate 1.
The preparation of the doped polysilicon layer 3 specifically comprises:
depositing a film layer on the surface of the tunneling layer 2 by adopting an LPCVD method or an HWCVD method, annealing to form an initial doped polysilicon layer,the annealing temperature is 800-950 ℃, and the reaction gas of the film layer comprises SiH4、PH3、H2In which is SiH4、PH3The flow ratio of the two is set to be 1: 0.1-1: 0.001, SiH4、H2The flow ratio of the two is set to be 1: 10-1: 250; or the like, or, alternatively,
depositing an intrinsic silicon film layer on the surface of the tunneling layer by LPCVD or PECVD, and diffusing to form an initial doped polysilicon layer, wherein the diffusion adopts a given gaseous phosphorus source (such as POCl)3) Or a solid phosphorus source (e.g.: phosphorus paste, Al (PO)3)3Etc.), setting the diffusion temperature to be 800-950 ℃, setting the thickness of the initial doped polysilicon layer to be 60-200 nm, preferably 100-150 nm, and setting the sheet resistance to be 30-50 omega/sq;
preparing a mask layer in a partial area of the surface of the initial doped polycrystalline silicon layer;
etching part of the initial doped polysilicon layer in the region where the mask layer is not arranged to obtain a first doped polysilicon layer 31 corresponding to the mask layer arrangement region and a second doped polysilicon layer 32 with the thickness smaller than that of the first doped polysilicon layer 31;
and cleaning and removing the mask layer.
The antireflection layer 4 is usually deposited by a PECVD method, and the antireflection layer 4 with a given thickness and refractive index can be obtained by adjusting the process conditions such as the reaction gas flow rate, the deposition temperature and the like.
The back cleaning step can adopt HF and HNO3The mixed solution is used for polishing and cleaning the back surface of the silicon substrate 1, or alkali solution is used for secondary texturing the back surface of the silicon substrate 1, and then low-concentration HF/high-concentration HNO is used3The mixed liquid carries out rounding treatment and post cleaning on the pyramid structure on the back of the silicon substrate 1. In particular, the "back side cleaning" process preferably maintains the tunneling layer 2, the doped polysilicon layer 3 and the anti-reflection layer 4 on the side surface of the silicon substrate 1, so as to improve the passivation performance of the edge position of the silicon substrate 1.
The intrinsic amorphous silicon layer 5 and the doped amorphous layer 6 are also prepared by adopting a PECVD method. The preparation of the intrinsic amorphous silicon layer 5 comprises the steps of depositing a first intrinsic amorphous silicon layer 51 and a second intrinsic amorphous silicon layer 52 on the back surface of the silicon substrate 1 in sequence, wherein the hydrogen content of the second intrinsic amorphous silicon layer 52 is greater than that of the first intrinsic amorphous silicon layer 51; the preparation of the doped amorphous layer 6 includes depositing a first doped amorphous layer 61 and a second doped amorphous layer 62 on the surface of the second intrinsic amorphous silicon layer 52 in sequence, wherein the doping concentration of the second doped amorphous layer 62 is greater than that of the first doped amorphous layer 61.
Specifically, silane is used as a gas source in the deposition process of the first intrinsic amorphous silicon layer 51, no hydrogen is introduced, the thickness of the first intrinsic amorphous silicon layer 51 is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the second intrinsic amorphous silicon layer 52 uses silane with high hydrogen dilution ratio as a gas source, and the gas flow ratio is set to SiH4:H2The thickness of the second intrinsic amorphous silicon layer 52 is set to be 3 to 8nm, and the refractive index is set to be 3.8 to 4.1. The doping concentration of the first doped amorphous layer 61 is 1E 18-5E 19cm-3(ii) a The doping concentration of the second doped amorphous layer 62 is 1E 19-5E 20cm-3。
The transparent conducting layer 7 is deposited by adopting a magnetron sputtering method and is obtained by annealing at the temperature of 180-220 ℃, and the annealing temperature is preferably 190-210 ℃.
The "grooving" refers to removing the antireflection layer 4 in a given area by laser etching, so that the doped polysilicon layer 3 is exposed outwards. The antireflection layer 4 can be designed according to the optical effect optimization without considering the burn-through contact problem of the front electrode 81, and the requirement on front metallization is lower. The notching process may preferably employ a laser beam having a shorter wavelength, such as 355nm, to better control the laser beam from etching through the doped polysilicon layer 3.
The front electrode 81 and the back electrode 82 are obtained by printing and drying low-temperature cured silver paste, and the printing position of the front electrode 81 corresponds to the slotting position, so that the low-temperature cured paste is directly contacted with the doped polycrystalline silicon layer 3; the temperature of the drying is usually set to be 150-250 ℃.
In addition, the preparation method further includes performing light injection or electrical injection treatment on the silicon substrate 1 after the preparation of the front electrode 81 and the back electrode 82 is completed, so that internal defects are reduced, and subsequent attenuation is reduced. To further illustrate the electrical performance of the solar cell 100 of the present application, refer to the following table:
| Group | Voc(mV) | Isc(A) | FF(％) | Rs(mΩ) | Rsh(Ω) | EFF(％) |
| example 1 | 721.9 | 9.864 | 83.56 | 0.61 | 1427.1 | 24.17％ |
| Example 2 | 724.9 | 9.841 | 83.17 | 0.82 | 1427.1 | 24.10％ |
| Comparative example | 710.2 | 9.923 | 82.89 | 1.22 | 1404.3 | 23.73％ |
The difference between the embodiment 1 and the embodiment 2 lies in that the preparation processes of the doped polysilicon layer 3 are different, the doped polysilicon layer 3 in the embodiment 1 adopts an LPCVD method to deposit an intrinsic silicon film layer, and then adopts POCl at 850-950 DEG C3Diffusing a gaseous source, and locally thinning to obtain the product; the doped polysilicon layer 3 in the embodiment 2 is obtained by depositing a lightly-doped amorphous silicon/polysilicon film layer by LPCVD or HWCVD, and then annealing at a high temperature and locally thinning. Here, the comparative example is a TOPCon cell fabricated using an N-type silicon wafer of the same specification. Obviously, the solar cell 100 of the present application effectively increases the open-circuit voltage and the fill factor through the structural optimization design, and the conversion efficiency is significantly improved compared to the existing TOPCon cell.
In summary, according to the solar cell 100 and the preparation method thereof, through structural design optimization, the absorption and conversion of incident light rays on the front side of the cell are ensured while the surface passivation of the cell is improved; and through reducing the high temperature treatment step, especially boron expands the high temperature process, reduce the defect that probably evolves and appear in the silicon substrate 1, improve battery performance and life time.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above list of details is only for the concrete description of the feasible embodiments of the present application, they are not intended to limit the scope of the present application, and all equivalent embodiments or modifications that do not depart from the technical spirit of the present application are intended to be included within the scope of the present application.
Claims (25)
1. The utility model provides a solar cell, includes the silicon substrate, establishes respectively the front electrode and the back electrode of silicon substrate both sides, its characterized in that: the front surface of the silicon substrate is sequentially provided with a tunneling layer, a doped polycrystalline silicon layer and an antireflection layer in a stacking mode, and the front surface electrode penetrates through the antireflection layer and is in contact with the doped polycrystalline silicon layer; the back surface of the silicon substrate is sequentially provided with an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer in a stacking mode, and the back surface electrode is arranged on the surface of one side, away from the silicon substrate, of the transparent conducting layer.
2. The solar cell of claim 1, wherein: the doped polysilicon layer comprises a first doped polysilicon layer and a second doped polysilicon layer, and the front electrode is correspondingly arranged on the first doped polysilicon layer; the thickness of the first doped polysilicon layer is greater than that of the second doped polysilicon layer.
3. The solar cell of claim 2, wherein: the thickness of the first doped polycrystalline silicon layer is set to be 60-200 nm; the thickness of the second doped polycrystalline silicon layer is set to be 10-50 nm.
4. The solar cell of claim 2, wherein: the doping concentration of the first doped polysilicon layer is greater than that of the second doped polysilicon layer.
5. The solar cell of claim 1, wherein: the doping concentration of the doped polysilicon layerThe setting is 5E18 ~ 5E20cm-3。
6. The solar cell of claim 1, wherein: the tunneling layer is set to be a silicon oxide film or a silicon oxynitride film, and the thickness of the tunneling layer is set to be 1-3 nm.
7. The solar cell of claim 1, wherein: the antireflection layer comprises a first antireflection layer and a second antireflection layer which are stacked, the first antireflection layer is a hydrogen-rich silicon nitride film, the thickness of the first antireflection layer is 3-30 nm, and the refractive index is 2.1-2.4; the second antireflection layer is provided as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a composite film composed of at least two of them.
8. The solar cell of claim 1, wherein: the thickness of the intrinsic amorphous silicon layer is set to be 5-10 nm.
9. The solar cell of claim 1, wherein: the intrinsic amorphous silicon layer comprises a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer which is stacked on the surface of one side, away from the silicon substrate, of the first intrinsic amorphous silicon layer, and the hydrogen content of the second intrinsic amorphous silicon layer is larger than that of the first intrinsic amorphous silicon layer.
10. The solar cell of claim 9, wherein: the thickness of the first intrinsic amorphous silicon layer is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1.
11. The solar cell of claim 1, wherein: the thickness of the doped amorphous layer is set to be 5-10 nm; and the doping concentration of the doped amorphous layer is 1E 18-5E 20cm-3。
12. The solar cell of claim 1, wherein: the doped amorphous layer comprises a first doped amorphous layer and a second doped amorphous layer which is arranged on the surface of one side, away from the silicon substrate, of the first doped amorphous layer in a stacking mode, and the doping concentration of the second doped amorphous layer is larger than that of the first doped amorphous layer.
13. The solar cell of claim 1, wherein: the thickness of the transparent conducting layer is set to be 70-120 nm.
14. The solar cell of claim 1, wherein: the silicon substrate is an N-type silicon wafer; the doped polycrystalline silicon layer is a phosphorus doped polycrystalline silicon layer, and the doped amorphous layer is a boron doped amorphous layer.
15. A method for manufacturing a solar cell is characterized in that:
sequentially preparing a tunneling layer, a doped polycrystalline silicon layer and an antireflection layer on the front side of a silicon substrate;
preparing an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer on the back of a silicon substrate in sequence;
grooving in a set area of the antireflection layer;
preparing a front electrode at the grooving position of the antireflection layer;
and preparing a back electrode on the transparent conductive layer.
16. The method of claim 15, wherein: the grooving refers to removing the antireflection layer in a set area by laser etching so that the doped polysilicon layer is exposed outwards.
17. The method of claim 15, wherein: the front electrode and the back electrode are obtained by adopting low-temperature curing silver paste printing and drying, and the drying temperature is 150-250 ℃.
18. The method of claim 15, wherein: the preparation of the doped polycrystalline silicon layer comprises the steps of depositing a film layer on the surface of the tunneling layer by adopting an LPCVD method or HWCVD method, and then annealing to form an initial doped polycrystalline silicon layer, wherein the annealing temperature is 800-950 ℃, and the reaction gas of the film layer comprises SiH4、PH3、H2In which is SiH4、PH3The flow ratio of the two is set to be 1: 0.1-1: 0.001, SiH4、H2The flow ratio of the two is set to be 1: 10-1: 250; or the like, or, alternatively,
depositing an intrinsic silicon film layer on the surface of the tunneling layer by an LPCVD (low pressure chemical vapor deposition) method or a PECVD (plasma enhanced chemical vapor deposition) method, and forming an initial doped polysilicon layer by diffusion, wherein the diffusion adopts a set gaseous phosphorus source or a set solid phosphorus source, and the diffusion temperature is set to be 800-950 ℃.
19. The method of claim 18, wherein: the preparation of the doped polycrystalline silicon layer further comprises the step of preparing a mask layer in a partial area of the surface of the initial doped polycrystalline silicon layer;
etching part of the initial doped polycrystalline silicon layer in the region where the mask layer is not arranged to obtain a first doped polycrystalline silicon layer corresponding to the mask layer arrangement region and a second doped polycrystalline silicon layer with the thickness smaller than that of the first doped polycrystalline silicon layer, wherein the thickness of the first doped polycrystalline silicon layer is set to be 60-200 nm, and the thickness of the second doped polycrystalline silicon layer is set to be 10-50 nm;
and cleaning and removing the mask layer.
20. The method of claim 15, wherein: the preparation method further comprises the steps of cleaning the back surface of the silicon substrate after the preparation of the antireflection layer is completed, and reserving the tunneling layer, the doped polycrystalline silicon layer and the antireflection layer on the side surface of the silicon substrate.
21. The method of claim 15, wherein: the preparation of the intrinsic amorphous silicon layer comprises the steps of depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer in sequence on the back surface of the silicon substrate, wherein the hydrogen content of the second intrinsic amorphous silicon layer is larger than that of the first intrinsic amorphous silicon layer; the preparation of the doped amorphous layer comprises the steps of sequentially depositing a first doped amorphous layer and a second doped amorphous layer on the surface of the second intrinsic amorphous silicon layer, wherein the doping concentration of the second doped amorphous layer is greater than that of the first doped amorphous layer.
22. The method of manufacturing according to claim 21, wherein: the thickness of the first intrinsic amorphous silicon layer is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1.
23. The method of claim 15, wherein: the thickness of the doped amorphous layer is set to be 5-10 nm; the doping concentration of the doped amorphous layer is 1E 18-5E 20cm-3。
24. The method of claim 15, wherein: the transparent conducting layer is deposited by a magnetron sputtering method and is obtained by annealing treatment at the temperature of 180-220 ℃.
25. The method of claim 15, wherein: the preparation method also comprises the step of carrying out light injection or electric injection treatment after the preparation of the front electrode and the back electrode is finished.
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