CN111564505A - Heterojunction solar cell with passivated double intrinsic layers and preparation method thereof - Google Patents

Heterojunction solar cell with passivated double intrinsic layers and preparation method thereof Download PDF

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CN111564505A
CN111564505A CN202010418281.8A CN202010418281A CN111564505A CN 111564505 A CN111564505 A CN 111564505A CN 202010418281 A CN202010418281 A CN 202010418281A CN 111564505 A CN111564505 A CN 111564505A
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layer
intrinsic layer
intrinsic
solar cell
silicon wafer
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李正平
刘超
杨杰
任栋樑
陈昌明
徐小娜
周国平
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Entropy Shanghai Energy Technology Co ltd
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Abstract

The invention discloses a heterojunction solar cell with double-intrinsic-layer passivation and a preparation method thereof. The solar cell comprises a crystalline silicon wafer, wherein a first intrinsic layer, a second intrinsic layer, a first doped amorphous silicon layer, a first transparent conducting layer and a first electrode are sequentially arranged on one side of the crystalline silicon wafer, and a second electrode is sequentially arranged on the other side of the crystalline silicon wafer. The preparation method comprises the following steps: forming a first intrinsic layer on one side of a crystal silicon wafer; performing hydrogen passivation on the first intrinsic layer; then, a second intrinsic layer, a first doped amorphous silicon layer, a first transparent conductive layer, a first electrode, a second electrode, etc. are formed. According to the invention, the first intrinsic layer and the second intrinsic layer are adopted, so that the structural property of the intrinsic layer is effectively improved, the open-circuit voltage of the heterojunction solar cell is improved, and the amplification can reach 0.02V.

Description

Heterojunction solar cell with passivated double intrinsic layers and preparation method thereof
Technical Field
The invention relates to the technical field of silicon solar cells, in particular to a heterojunction solar cell with double-intrinsic-layer passivation and a preparation method thereof.
Background
The heterojunction solar cell has the high efficiency and high stability of the crystalline silicon solar cell, and simultaneously has the advantages of relatively simple process, better temperature characteristic and higher output at high temperature due to low energy consumption. Therefore, the solar cell has attracted much attention in recent years and has become one of the main development directions of the solar cell.
The heterojunction solar cell with an intrinsic thin layer is constructed by interposing an intrinsic structure between a doped amorphous silicon layer and a crystalline silicon substrate. The nature of the intrinsic structure is a key factor affecting the performance of the heterojunction solar cell; most importantly, the nature of the intrinsic structure affects the open circuit voltage of the heterojunction solar cell. However, the open circuit voltage of the current heterojunction solar cell is still low, and needs to be further improved. The open-circuit voltage of the heterojunction solar cell can be improved by regulating and controlling the structure and the performance of the intrinsic layer.
Therefore, those skilled in the art have devoted themselves to develop a double intrinsic layer passivated heterojunction solar cell, which improves the open circuit voltage and the conversion efficiency of the heterojunction cell by the good passivation capability of the double intrinsic layer.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the open-circuit voltage of the existing heterojunction solar cell is still low.
In order to solve the technical problem, the invention provides a heterojunction solar cell with double-intrinsic-layer passivation, which is characterized by comprising a crystalline silicon wafer, wherein a first intrinsic layer, a second intrinsic layer, a first doped amorphous silicon layer, a first transparent conducting layer and a first electrode are sequentially arranged on one side of the crystalline silicon wafer, and a second electrode is sequentially arranged on the other side of the crystalline silicon wafer.
Preferably, a third intrinsic layer, a fourth intrinsic layer, a second doped amorphous silicon layer and a second transparent conducting layer are sequentially arranged between the crystalline silicon wafer and the second electrode.
Preferably, the crystalline silicon wafer is monocrystalline silicon or polycrystalline silicon, and the doping type is P-type silicon or N-type silicon.
Preferably, the optical bandgap Eg of the first intrinsic layer1Optical band gap Eg between the second intrinsic layer2Optical band gap Eg with crystalline silicon waferCrystal grainIn between, i.e. EgCrystal grain＜Eg1＜Eg2。
More preferably, the optical bandgap Eg of the first intrinsic layer1The optical band gap Eg of the second intrinsic layer2The following conditions are satisfied: 1.12eV < Eg1＜1.8eV，1.6eV＜Eg2＜1.8eV。
More preferably, the optical bandgap Eg of the third intrinsic layer3Optical bandgap Eg between the fourth intrinsic layer4Optical band gap Eg with crystalline silicon waferCrystal grainIn between, i.e. EgCrystal grain＜Eg3＜Eg4。
More preferably, the optical bandgap Eg of the third intrinsic layer3Optical band gap Eg with the first intrinsic layer1The same; an optical bandgap Eg of the fourth intrinsic layer4Optical band gap Eg with the second intrinsic layer2The same is true.
Preferably, the first intrinsic layer is intrinsic silicon hydride; the second intrinsic layer is intrinsic hydrogenated silicon.
Preferably, the thickness of the first intrinsic layer is 2-5 nm, and the thickness of the first intrinsic layer is smaller than that of the second intrinsic layer.
The invention also provides a preparation method of the double intrinsic layer passivated heterojunction solar cell, which is characterized by comprising the following steps:
step 1): forming a first intrinsic layer on one side of a crystal silicon wafer;
step 2): performing hydrogen passivation on the first intrinsic layer;
step 3): forming a second intrinsic layer on the first intrinsic layer;
step 4): forming a first doped amorphous silicon layer on the second intrinsic layer;
step 5): forming a third intrinsic layer on the other side of the crystal silicon wafer;
step 6): forming a fourth intrinsic layer on the third intrinsic layer;
step 7): forming a second doped amorphous silicon layer on the fourth intrinsic layer;
step 8): forming a first transparent conductive layer on the first doped amorphous silicon layer;
step 9): forming a second transparent conductive layer on the second doped amorphous silicon layer;
step 10): forming a first electrode on the first transparent conductive layer;
step 11): and forming a second electrode on the second transparent conductive layer.
Compared with the prior art, the invention has the following technical effects:
the heterojunction solar cell of the invention introduces double intrinsic passivation layers at one side or two sides, because a first intrinsic layer and a second intrinsic layer are adopted, or a first intrinsic layer and a second intrinsic layer are adopted at one side, a third intrinsic layer and a fourth intrinsic layer are adopted at the other side, the optical band gap Eg1 of the first intrinsic layer is between the optical band gap Eg2 of the second intrinsic layer and the optical band gap Eg crystal of a crystal silicon wafer, and the optical band gap Eg3 of the third intrinsic layer is between the optical band gap Eg4 of the fourth intrinsic layer and the optical band gap Eg crystal of the crystal silicon wafer; therefore, the structural property of the intrinsic layer is effectively improved, the open-circuit voltage of the heterojunction solar cell is improved, and the amplification can reach 0.02V. The preparation method can effectively improve the open-circuit voltage of the heterojunction solar cell, has easy process control and high productivity, and is beneficial to industrial large-scale production of the heterojunction solar cell.
Drawings
Fig. 1 is a schematic structural diagram of a heterojunction solar cell provided by the present invention.
Detailed Description
In order to make the invention more comprehensible, preferred embodiments are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the heterojunction solar cell with double-intrinsic-layer passivation provided by the invention comprises a crystalline silicon wafer 1, wherein a first intrinsic layer 2, a second intrinsic layer 3, a first doped amorphous silicon layer 4, a first transparent conductive layer 5 and a first electrode 6 are sequentially arranged on one side of the crystalline silicon wafer 1, and a third intrinsic layer 7, a fourth intrinsic layer 8, a second doped amorphous silicon layer 9, a second transparent conductive layer 10 and a second electrode 11 are sequentially arranged on the other side of the crystalline silicon wafer 1.
In the embodiment, the heterojunction solar cell is basically of a symmetrical structure, so that the thermal stress and the mechanical stress in the production process can be reduced, and the thinning development of the crystalline silicon wafer 1 is facilitated. In addition, both sides can absorb light to increase the power generation amount.
The crystalline silicon wafer 1 and the first doped amorphous silicon layer 4 form a PN junction. The crystalline silicon wafer 1 and the second doped amorphous silicon layer 9 form an enhanced electric field (also called back electric field). The open circuit voltage of the heterojunction solar cell can be further increased by strengthening the electric field. It will of course be appreciated that the electric field enhancement, i.e. the second doped amorphous silicon layer 9, may also be absent.
The crystal silicon wafer 1 is monocrystalline silicon or polycrystalline silicon, and the doping type is P-type silicon or N-type silicon. In the embodiment, the crystalline silicon wafer 1 is an N-type crystalline silicon wafer, and correspondingly, the first doped amorphous silicon layer 4 is a P-type amorphous silicon layer, and the second doped amorphous silicon layer 9 is an N-type amorphous silicon layer. In the heterojunction solar cell of the present invention, the crystalline silicon wafer 1 may also be a P-type, and correspondingly, the first doped amorphous silicon layer 4 is an N-type and the second doped amorphous silicon layer 9 is a P-type. The crystal silicon wafer 1 adopts an N-type crystal silicon wafer, so that the performance of the heterojunction solar cell is more excellent, the photoinduced degradation phenomenon of a P-type cell can be overcome, and in addition, the density of the efficient recombination center is far lower than that of the P-type cell, so that electrons have longer service life and diffusion length. In particular, the crystalline silicon may be single crystalline silicon or polycrystalline silicon. More specifically, the crystalline silicon wafer 1 of the present embodiment is an N-type single crystalline silicon wafer.
The thickness of the crystalline silicon wafer 1 is generally less than 200 μm. In this embodiment, the thickness of the crystalline silicon wafer 1 is 100 to 200 μm. Therefore, the use of silicon materials can be saved, and the cost is further reduced; but also can improve the process stability. The thickness of the first intrinsic layer 2 is 2-5 nm, and the thickness is smaller than that of the second intrinsic layer 3.
The surface of the crystal silicon wafer 1 is a suede surface, and the crystal silicon is suede, so that the reflection of the surface of the battery can be reduced, and more photons can be absorbed by the crystal silicon wafer 1; meanwhile, the method has the function of removing the surface damage of the crystalline silicon. The texture is a pyramid texture, which is more favorable for light to obliquely irradiate the inside of the crystal silicon wafer 1, reduces the reflectivity of light on the surface of the battery, enlarges the optical path and increases the number of absorbed photons.
In the solar cell, the first intrinsic layer 2 and the second intrinsic layer 3 form an upper intrinsic structure, and the upper intrinsic structure is used for passivating the crystalline silicon wafer 1, so that the interface between the crystalline silicon wafer 1 and the first doped amorphous silicon layer 4 is passivated, and the open-circuit voltage of the heterojunction solar cell is increased. The optical bandgap Eg of the first intrinsic layer 21Optical bandgap Eg between the second intrinsic layer 32Optical band gap Eg with crystalline silicon wafer 1Crystal grainIn between, i.e. EgCrystal grain＜Eg1＜Eg2. From the first doped amorphous silicon layer to the crystalline silicon wafer, the optical band gaps of the layers are in a decreasing state. On one hand, the method can help minority carrier collection and increase minority carrier lifetime; on the other hand, the graded band gap increases the absorption efficiency of the actual spectrum. Optical bandgap Eg of the first intrinsic layer 21The optical band gap Eg of the second intrinsic layer 32The following conditions are satisfied: 1.12eV < Eg1＜1.8eV，1.6eV＜Eg2< 1.8 eV. This may further improve the performance of the heterojunction solar cell.
Typically, the intrinsic structure has a thickness of no more than 10nm, preferably 5 to 10 nm. Therefore, the heterojunction solar cell has higher open-circuit voltage, the absorption of the upper intrinsic structure to light is reduced, the cell resistance is reduced, and the filling factor is improved. Preferably, the thickness of the first intrinsic layer 2 is smaller than the thickness of the second intrinsic layer 3. Therefore, the influence on the filling factor due to the increase of the series resistance can be reduced while the open circuit voltage of the heterojunction solar cell is increased. More preferably, the thickness of the first intrinsic layer 2 is 2 to 5 nm; the thickness of the second intrinsic layer 3 is 3 to 8 nm. In the present embodiment, the thickness of the first intrinsic layer 2 is 3nm, and the thickness of the second intrinsic layer 3 is 5 nm.
In the present embodiment, the first intrinsic layer 2 is intrinsic silicon hydride, and the second intrinsic layer 3 is intrinsic silicon hydride.
The third and fourth intrinsic layers 7 and 8 are similar to the first and second intrinsic layers 2 and 3. The third intrinsic layer 7 and the fourth intrinsic layer 8 form a lower intrinsic structure; the lower intrinsic structure is used for passivating the crystalline silicon wafer 1, so that the interface between the crystalline silicon wafer 1 and the second doped amorphous silicon layer 9 is passivated, and the open-circuit voltage of the heterojunction solar cell is increased. The optical band gap of the lower intrinsic structure is between the crystalline silicon wafer 1 and the second doped amorphous silicon layer 9. Optical bandgap Eg of the third intrinsic layer 73Optical bandgap Eg between the fourth intrinsic layer 84Optical band gap Eg with crystalline silicon wafer 1Crystal grainIn between, i.e. EgCrystal grain＜Eg3＜Eg4. I.e. the optical bandgap Eg of the third intrinsic layer 73The optical band gap Eg of the fourth intrinsic layer 84Also satisfies the requirement of 1.12eV < Eg3＜1.8eV，1.6eV＜Eg4＜1.8eV。
In the present embodiment, the optical bandgap Eg1 of the first intrinsic layer 2 is the same as the optical bandgap Eg3 of the third intrinsic layer 7; the optical bandgap Eg2 of the second intrinsic layer 3 is the same as the optical bandgap Eg4 of the fourth intrinsic layer 8.
In general, the thickness of the intrinsic structure is not greater than 10nm, preferably 5-10 nm. Therefore, the heterojunction solar cell has higher open-circuit voltage, the absorption of the lower intrinsic structure to light is reduced, the cell resistance is reduced, and the filling factor is improved. Preferably, the thickness of the third intrinsic layer 7 is smaller than the thickness of the fourth intrinsic layer 8. Therefore, the influence on the filling factor due to the increase of the series resistance can be reduced while the open circuit voltage of the heterojunction solar cell is increased. More preferably, the thickness of the third intrinsic layer 7 is 2 to 5 nm; the thickness of the fourth intrinsic layer 8 is 3-8 nm. In the present embodiment, the thickness of the third intrinsic layer 7 is the same as that of the first intrinsic layer 2; the thickness of the fourth intrinsic layer 8 is the same as the thickness of the second intrinsic layer 3.
In the present embodiment, the third intrinsic layer 7 is intrinsic hydrogenated silicon, and the fourth intrinsic layer 8 is intrinsic hydrogenated silicon.
Of course, it is understood that the present invention may be provided with only the fourth intrinsic layer 8 without the third intrinsic layer 7; neither the third intrinsic layer 7 nor the fourth intrinsic layer 8 may be provided.
In the present embodiment, the first electrode 6 is formed in a grid shape, and is generally formed by screen printing. The second electrode 11 is a layer, specifically an all-silver electrode.
In the present embodiment, the first transparent conductive layer 5 is used to improve the conductivity of the first doped amorphous silicon layer 4 and the first electrode 6, which effectively increases the collection of carriers. In the present embodiment, the first transparent conductive layer 5 is a tungsten-doped indium oxide (IWO) layer. The IWO layer has potential high carrier mobility characteristics, and compared with an Indium Tin Oxide (ITO) layer, the IWO layer has lower carrier concentration under the condition of ensuring the same conductivity, so that the IWO layer has smaller carrier absorption and larger plasma wavelength, and further the IWO layer has high light transmittance and low absorption rate in a near infrared region. Of course, the first transparent conductive layer 5 can also be an ITO layer or a Fluorine Tin Oxide (FTO) layer.
The thicknesses of the first transparent conductive layer 5 and the second transparent conductive layer 10 are both 60-100 nm. So that the electrical and optical properties thereof are more excellent.
Similarly, the second transparent conductive layer 10 is used to improve the conductivity of the second doped amorphous silicon layer 9 and the second electrode 11, and effectively increase the collection of carriers. In this embodiment, the second transparent conductive layer 10 is also an IWO layer. Of course, the second transparent conductive layer 10 can also be an ITO layer or an FTO layer.
Of course, it is understood that the present invention may also be provided with a second transparent conductive layer 10, or with an opaque conductive layer.
According to the heterojunction solar cell, the first intrinsic layer and the second intrinsic layer are adopted, and the optical band gap of the first intrinsic layer is between the optical band gap of the second intrinsic layer and the optical band gap of the crystal silicon wafer, so that the structural property of the intrinsic layer is effectively improved, the open-circuit voltage of the heterojunction solar cell is improved, and the amplification can reach 0.02V.
The preparation method of the heterojunction solar cell comprises the following steps:
step 1: forming a first intrinsic layer 2 on one side of a crystalline silicon wafer 1;
step 2: hydrogen passivation of the first intrinsic layer 2;
and step 3: forming a second intrinsic layer 3 on the first intrinsic layer 2;
and 4, step 4: forming a first doped amorphous silicon layer 4 on the second intrinsic layer 3;
and 5: forming a third intrinsic layer 7 on the other side of the crystalline silicon wafer 1;
step 6: forming a fourth intrinsic layer 8 on the third intrinsic layer 7;
and 7: forming a second doped amorphous silicon layer 9 on the fourth intrinsic layer 8;
and 8: forming a first transparent conductive layer 5 on the first doped amorphous silicon layer 4;
and step 9: forming a second transparent conductive layer 10 on the second doped amorphous silicon layer 9;
step 10: forming a first electrode 6 on the first transparent conductive layer 5;
step 11: a second electrode 11 is formed on the second transparent conductive layer 10.
In order to improve the performance of the heterojunction solar cell, the crystalline silicon wafer is preferably subjected to a texturing and cleaning step. The texture surface making method can adopt wet texture surface making, and generally adopts alkaline solution (such as KOH, NaOH, tetramethyl ammonium hydroxide and the like) with a certain proportion to carry out anisotropic etching for a certain time. And cleaning the crystal silicon wafer after texturing, wherein the cleaning mainly has the function of removing metal ions remained on the surface of the crystal silicon wafer after texturing and a natural oxidation film formed on the surface of the crystal silicon wafer. In addition, during cleaning, the chemical liquid for removing the oxide film on the surface of the crystal silicon wafer can also play a role in partially passivating the crystal silicon wafer. For crystalThe cleaning of the bulk silicon wafer can adopt chemical cleaning, such as: RCA washing solution (alkaline and acidic hydrogen peroxide solution) and alkaline hydrogen peroxide solution are used, and the mass ratio of the alkaline hydrogen peroxide solution to the alkaline hydrogen peroxide solution is H2O:H2O2:NH4OH＝
5:1:1-5:2: 1; acid hydrogen peroxide solution with the mass ratio of H2O:H2O2HC1 is 6:1:1-8:2: 1; the RCA washing solution is used under the following conditions: cleaning at 75-85 deg.C for 10-20 min, wherein alkaline hydrogen peroxide solution is used first and then acidic hydrogen peroxide solution is used.
In order to improve the performance of the heterojunction solar cell, the heterojunction solar cell of the embodiment further includes a third intrinsic layer, a fourth intrinsic layer, a second doped amorphous silicon layer, a second transparent conductive layer, and the like.
The first intrinsic layer, the second intrinsic layer, the third intrinsic layer, the fourth intrinsic layer, the first doped amorphous silicon layer and the second doped amorphous silicon layer are formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). Of course, it is understood that the method is not limited to the above-mentioned method, but may be a Hot Wire Chemical Vapor Deposition (HWCVD) method or a high frequency plasma enhanced Chemical Vapor Deposition (VHF-PECVD) method, or other preparation methods.
The deposition conditions of the first intrinsic layer were: the reaction gas is SiH4And H2The deposition temperature is 160-230 ℃; the deposition pressure range is 100-300 Pa; the flow range of SiH4 is 30-200 sccm; h2The flow range is 200-900 sccm; the deposition power range is 150-400W.
The deposition conditions of the second intrinsic layer were: the reaction gas is SiH4And H2The deposition temperature is 160-230 ℃; the deposition pressure range is 300-600 Pa; SiH4The flow range is 30-200 sccm; the flow range of H2 is 200-900 sccm; the deposition power range is 400-700W.
Before the second intrinsic layer is formed, that is, after the first intrinsic layer is formed, a step of hydrogen passivating the first intrinsic layer is further included. The hydrogen passivation is specifically passivated by adopting a glow discharge method. Of course, it is understood that the second intrinsic layer may also be hydrogen passivated for further optimization.
The third and fourth intrinsic layers can refer to the first and second intrinsic layers, and are not described herein again.
The first transparent conductive layer and the second transparent conductive layer are deposited by Reactive Plasma Deposition (RPD). When the first transparent conductive layer and the second transparent conductive layer are formed, argon and oxygen can be simultaneously introduced, and the volume ratio of the oxygen to the argon is 2.5.
The first electrode and the second electrode are formed by screen printing of low-temperature silver paste, wherein the drying temperature is 100 ℃, and the sintering temperature is 200 ℃.
The preparation method provided by the invention can effectively improve the open-circuit voltage of the heterojunction solar cell, is easy to control the process and high in productivity, and is beneficial to industrial large-scale production of the heterojunction solar cell.
Example 1
After etching and cleaning a 150-micron thick N-type monocrystalline silicon wafer, depositing a first intrinsic layer on one side surface of the monocrystalline silicon wafer in a PECVD (plasma enhanced chemical vapor deposition) mode, wherein the deposition conditions are as follows: SiH4The flow rate was 95sccm, the flow rate of hydrogen was 430sccm, the power was 230W, the temperature was 170 ℃, the pressure was 260Pa, and the deposition thickness was 3 nm.
Then, hydrogen passivation is carried out on the first intrinsic layer by hydrogen glow discharge under the passivation conditions that: the hydrogen flow rate was 430sccm, the power was 600W, the pressure was 450Pa, and the time was 4 s.
And depositing a second intrinsic layer on the passivated first intrinsic layer by adopting a PECVD (plasma enhanced chemical vapor deposition) mode, wherein the deposition conditions are as follows: SiH4 was flowed at 95sccm, hydrogen was flowed at 430sccm, power was 600W, temperature was 170 deg.C, pressure was 510Pa, and deposition thickness was 4 nm.
And depositing P-type amorphous silicon on the second intrinsic layer by adopting PECVD (plasma enhanced chemical vapor deposition), and depositing an IWO (ultraviolet radiation) layer on the P-type amorphous silicon by adopting RPD (plasma enhanced chemical vapor deposition).
And sequentially depositing a third intrinsic layer (with the same deposition condition as the first intrinsic layer), a fourth intrinsic layer (with the same deposition condition as the second intrinsic layer), N-type heavily-doped amorphous silicon and an IWO layer on the other surface of the N-type monocrystalline silicon wafer.
And finally, screen printing is adopted to form a grid line electrode on the front side and an all-silver electrode on the back side. Wherein the drying temperature is 100 ℃, and the sintering temperature is 200 ℃.
A heterojunction solar cell was obtained as described above and designated a 1.
Comparative example 1
Unlike embodiment 1, the first intrinsic layer and the third intrinsic layer were not provided, the thickness of the second intrinsic layer was 5nm, and the thickness of the fourth intrinsic layer was 5 nm; the other portions are the same as in example 1.
A heterojunction solar cell was obtained as described above and designated D1.
The open circuit voltage of test A1 and D1, A1 was 0.755V, and D1 was 0.735V.
From the above, the open-circuit voltage of a1 is greater than that of D1, and the difference reaches 0.02V, which indicates that the invention can effectively increase the open-circuit voltage of the heterojunction solar cell.

Claims (10)

1. The heterojunction solar cell with the double-intrinsic-layer passivation is characterized by comprising a crystalline silicon wafer (1), wherein a first intrinsic layer (2), a second intrinsic layer (3), a first doped amorphous silicon layer (4), a first transparent conducting layer (5) and a first electrode (6) are sequentially arranged on one side of the crystalline silicon wafer (1), and a second electrode (11) is sequentially arranged on the other side of the crystalline silicon wafer (1).
2. The double intrinsic layer passivated heterojunction solar cell as claimed in claim 1, wherein a third intrinsic layer (7), a fourth intrinsic layer (8), a second doped amorphous silicon layer (9), a second transparent conductive layer (10) are sequentially disposed between the crystalline silicon wafer (1) and the second electrode (11).
3. The double intrinsic layer passivated heterojunction solar cell according to claim 1 or 2 wherein said crystalline silicon wafer (1) is single crystalline silicon or polycrystalline silicon and the doping type is P-type silicon or N-type silicon.
4. The double intrinsic layer passivated heterojunction solar cell of claim 1 or 2 whereinAn optical bandgap Eg of said first intrinsic layer (2)1An optical band gap Eg between the second intrinsic layer (3)2Optical band gap Eg with crystalline silicon wafer (1)Crystal grainIn between, i.e. EgCrystal grain＜Eg1＜Eg2。
5. The double intrinsic layer passivated heterojunction solar cell according to claim 4 wherein the optical bandgap Eg of the first intrinsic layer (2)1An optical band gap Eg of the second intrinsic layer (3)2The following conditions are satisfied: 1.12eV < Eg1＜1.8eV，1.6eV＜Eg2＜1.8eV。
6. The double intrinsic layer passivated heterojunction solar cell according to claim 2 wherein the optical bandgap Eg of the third intrinsic layer (7)3An optical bandgap Eg between the fourth intrinsic layer (8)4Optical band gap Eg with crystalline silicon wafer (1)Crystal grainIn between, i.e. EgCrystal grain＜Eg3＜Eg4。
7. The double intrinsic layer passivated heterojunction solar cell according to claim 2 wherein the optical bandgap Eg of the third intrinsic layer (7)3An optical band gap Eg with the first intrinsic layer (2)1The same; an optical bandgap Eg of the fourth intrinsic layer (8)4Optical band gap Eg with the second intrinsic layer (3)2The same is true.
8. The double intrinsic layer passivated heterojunction solar cell according to claim 1 or 2 wherein said first intrinsic layer (2) is intrinsic silicon hydride; the second intrinsic layer (3) is intrinsic hydrogenated silicon.
9. The double intrinsic layer passivated heterojunction solar cell according to claim 1 or 2, characterized in that the first intrinsic layer (2) has a thickness of 2-5 nm and a thickness less than the thickness of the second intrinsic layer (3).
10. Method for the preparation of a double intrinsic layer passivated heterojunction solar cell according to any of the claims 2-8, characterized in that it comprises the following steps:
step 1): forming a first intrinsic layer (2) on one side of a crystalline silicon wafer (1);
step 2): hydrogen passivation of the first intrinsic layer (2);
step 3): forming a second intrinsic layer (3) on the first intrinsic layer (2);
step 4): forming a first doped amorphous silicon layer (4) on the second intrinsic layer (3);
step 5): forming a third intrinsic layer (7) on the other side of the crystal silicon wafer (1);
step 6): forming a fourth intrinsic layer (8) on the third intrinsic layer (7);
step 7): forming a second doped amorphous silicon layer (9) on the fourth intrinsic layer (8);
step 8): forming a first transparent conductive layer (5) on the first doped amorphous silicon layer (4);
step 9): forming a second transparent conductive layer (10) on the second doped amorphous silicon layer (9);
step 10): forming a first electrode (6) on the first transparent conductive layer (5);
step 11): a second electrode (11) is formed on the second transparent conductive layer (10).
CN202010418281.8A 2020-05-18 2020-05-18 Heterojunction solar cell with passivated double intrinsic layers and preparation method thereof Withdrawn CN111564505A (en)

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Application publication date: 20200821