CN105720115A - Heterojunction solar cell and preparation method therefor - Google Patents

Heterojunction solar cell and preparation method therefor Download PDF

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Publication number
CN105720115A
CN105720115A CN201610279832.0A CN201610279832A CN105720115A CN 105720115 A CN105720115 A CN 105720115A CN 201610279832 A CN201610279832 A CN 201610279832A CN 105720115 A CN105720115 A CN 105720115A
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layer
heterojunction solar
solar battery
crystal silicon
transparency conducting
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杨乐
张闻斌
王琪
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Suzhou Gcl System Integration Technology Industrial Application Research Institute Co Ltd
GCL System Integration Technology Co Ltd
GCL System Integration Technology Suzhou Co Ltd
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Suzhou Gcl System Integration Technology Industrial Application Research Institute Co Ltd
GCL System Integration Technology Co Ltd
GCL System Integration Technology Suzhou Co Ltd
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Publication of CN105720115A publication Critical patent/CN105720115A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022466Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1884Manufacture of transparent electrodes, e.g. TCO, ITO
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
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Abstract

The invention relates to the field of the solar cell and specifically discloses a heterojunction solar cell. The heterojunction solar cell comprises a crystal silicon wafer, and a first intrinsic layer, a first doped noncrystalline silicon layer, a first transparent conductive layer and a first electrode that are positioned on one side of the crystal silicon wafer in sequence, and a second electrode positioned on the other side of the crystal silicon wafer, wherein the first transparent conductive layer is a GraphExeter layer. According to the heterojunction solar cell, the first transparent conductive layer is the GraphExeter layer, so that thin film resistance is greatly lowered and the conductivity is greatly improved under the condition of keeping the high transmissivity, and the conversion efficiency of the heterojunction solar cell is further improved. The invention also discloses a preparation method for the heterojunction solar cell.

Description

Heterojunction solar battery and preparation method thereof
Technical field
The present invention relates to area of solar cell, particularly relate to a kind of heterojunction solar battery and preparation method thereof.
Background technology
Heterojunction solar battery (HIT battery) by adding constructed by intrinsic layer between doped amorphous silicon layer and crystalline silicon substrate.Heterojunction solar battery had both had high efficiency and the high stability of crystal silicon solar energy battery, simultaneously because energy consumption is little, technique is relatively easy, temperature characterisitic is better, at high temperature also can have higher output.Receive much concern in recent years, one of main development direction having become as solaode.
Owing to the electric conductivity of doped amorphous silicon is poor, so in the manufacturing process of heterojunction solar battery, adding layer of transparent conductive layer between electrode and doped amorphous silicon layer, transparency conducting layer can increase the collection of carrier effectively.Transparency conducting layer has optical clear and conduction dual-use function, the collection of efficient carrier is played pivotal role, it is also possible to reduce the reflection of light, play good light trapping effect, be good window layer material.
But, the material of current transparency conducting layer is generally metal-oxide, for instance tin indium oxide (ITO), fluorine oxide stannum (FTO) etc..Under the requirement of certain light transmission, the electric conductivity of these materials need to improve, to promote electricity conversion further.
Summary of the invention
Based on this, it is necessary for transparency conducting layer in existing heterojunction solar battery under the requirement of certain light transmission, electric conductivity is low, is unfavorable for the problem that electricity conversion promotes, it is provided that the heterojunction solar battery that a kind of transparency conducting layer conductivity is high, electricity conversion is high.
A kind of heterojunction solar battery, including: crystal silicon chip, it is sequentially located at the first intrinsic layer on the side of described crystal silicon chip, the first doped amorphous silicon layer, the first transparency conducting layer and the first electrode, and is positioned at the second electrode of the opposite side of described crystal silicon chip;
Wherein, described first transparency conducting layer is that Graphene inserts tri-chlorination iron layer.
Above-mentioned heterojunction solar battery, owing to adopting Graphene to insert tri-chlorination iron layer as the first transparency conducting layer, when keeping high-transmission rate (being typically in about 87%), its sheet resistance can be reduced to 15 Ω/, its conductivity is greatly improved, and then makes the conversion efficiency of heterojunction solar battery improve.
Wherein in an embodiment, the thickness of described first transparency conducting layer is 1~15nm.
Wherein in an embodiment, described first intrinsic layer is non-crystalline silicon.
Wherein in an embodiment, described crystal silicon chip is N-type crystalline silicon sheet, and described first doped amorphous silicon layer is P-type non-crystalline silicon layer.
Wherein in an embodiment, described heterojunction solar battery also includes the reinforcement electric field unit between described second electrode and described crystal silicon chip;Described reinforcement electric field unit includes the second intrinsic layer and the second doped amorphous silicon layer that are sequentially located on the opposite side of described crystal silicon chip.
Wherein in an embodiment, described second intrinsic layer is non-crystalline silicon.
Wherein in an embodiment, described heterojunction solar battery also includes the second transparency conducting layer between described second electrode and described second doped amorphous silicon layer.
The preparation method that present invention also offers a kind of above-mentioned heterojunction solar battery.
The preparation method of a kind of heterojunction solar battery, comprises the steps:
The first intrinsic layer is formed in the side of crystal silicon chip;
Described first intrinsic layer forms the first doped amorphous silicon layer;
Described first doped amorphous silicon layer forms the first transparency conducting layer;Described first transparency conducting layer is that Graphene inserts tri-chlorination iron layer;
Described first transparency conducting layer forms the first electrode;
Opposite side at described crystal silicon chip forms the second electrode.
Above-mentioned preparation method, technique is easily controlled, and production capacity is big, is conducive to the industrialization large-scale production of heterojunction solar battery.
Wherein in an embodiment, described first intrinsic layer and/or described first doped amorphous silicon layer using plasma strengthen chemical vapour deposition technique and are formed.
Wherein in an embodiment, described first transparency conducting layer is formed by wet method transfer.
Accompanying drawing explanation
Fig. 1 is the structural representation of the heterojunction solar battery of one embodiment of the invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with detailed description of the invention, the present invention is further elaborated.Should be appreciated that detailed description of the invention described herein is only in order to explain the present invention, is not intended to limit the present invention.
It should be noted that be referred to as " being arranged at " another element when element, it can directly on another element or can also there is element placed in the middle.When an element is considered as " connection " another element, it can be directly to another element or may be simultaneously present centering elements.For illustrative purposes only, being not offered as is unique embodiment for term as used herein " vertical ", " level ", "left", "right" and similar statement.
Unless otherwise defined, all of technology used herein is identical with the implication that the those skilled in the art belonging to the present invention are generally understood that with scientific terminology.The term used in the description of the invention herein is intended merely to the purpose describing specific embodiment, it is not intended that in the restriction present invention.Term as used herein " and/or " include the arbitrary and all of combination of one or more relevant Listed Items.
Referring to Fig. 1, the heterojunction solar battery 100 of one embodiment of the invention, including: crystal silicon chip 110, it is sequentially located at the first intrinsic layer the 121, first doped amorphous silicon layer the 131, first transparency conducting layer 151 and the first electrode 161 on the side (upside in Fig. 1) of crystal silicon chip 110;And it is sequentially located at the second intrinsic layer the 122, second doped amorphous silicon layer the 132, second transparency conducting layer 152 and the second electrode 162 of the opposite side (downside in Fig. 1) of crystal silicon chip 110.First transparency conducting layer 151 inserts ferric chloride (GraphExeter) layer for Graphene.
In the present embodiment, heterojunction solar battery 100 is structure substantially symmetrically, so can reduce thermal stress and mechanical stress in production process, is conducive to the thinning development of crystal silicon chip 110 simultaneously.Generated energy is made to increase it addition, two sides all can absorb light.
In the present invention, crystal silicon chip 110 and the first doped amorphous silicon layer 131 constitute PN junction.Crystal silicon chip 110 and the second doped amorphous silicon layer 132 composition add highfield (being also back of the body electric field).The open-circuit voltage of heterojunction solar battery 100 can be improved further by adding highfield.Highfield is added, say, that do not set the second doped amorphous silicon layer 132 it is, of course, understood that can not also set.
In the present embodiment, crystal silicon chip 110 is N-type crystalline silicon sheet (n-c-Si), and accordingly, the first doped amorphous silicon layer 131 is P-type non-crystalline silicon layer (p-a-Si), and the second doped amorphous silicon layer 132 is N-type non-crystalline silicon layer (n-a-Si).It is, of course, understood that be not limited to above-mentioned form, in the heterojunction solar battery of the present invention, it is also possible to be crystal silicon chip 110 be P type, accordingly, the first doped amorphous silicon layer 131 is N-type, and the second doped amorphous silicon layer 132 is P type.
In the present embodiment, crystal silicon chip 110 adopts N-type crystalline silicon sheet (n-c-Si), the performance that can make heterojunction solar battery 100 is more superior, the photic decay of battery adopting P type can be overcome, additionally, the density at its high efficiency composition center is far below P type so that electronics has higher life-span and diffusion length.Specifically, crystalline silicon can be monocrystal silicon or polysilicon.More specifically, the crystal silicon chip 110 of the present embodiment is n type single crystal silicon sheet.
Specifically, the thickness of crystal silicon chip 110 is generally less than 200 μm.Preferably, the thickness of crystal silicon chip 110 is 100~200 μm.So both can save the use of silicon materials, and then reduce cost;Technology stability can be improved again.
Preferably, the surface of crystal silicon chip 110 is matte;It is to say, crystalline silicon is carried out making herbs into wool.So can reduce the reflection of battery surface so that more photon can be absorbed by crystal silicon chip 110;Also there is the effect that can remove surface of crystalline silicon damage simultaneously.In the present embodiment, matte is Pyramid matte, is so more beneficial for light and slants the inside of crystal silicon chip 110, reduces the reflectance of the light of battery surface so that light path becomes big, and the number of photons quantitative change of absorption is many.
Wherein, the effect of the first intrinsic layer 121 is, is used for being passivated crystal silicon chip 110, makes the interface being positioned at the crystal silicon chip 110 of the first intrinsic layer 121 both sides and the first doped amorphous silicon layer 131 obtain purification, and then makes the open-circuit voltage of heterojunction solar battery 100 increase.The optical band gap of the first intrinsic layer 121 is between crystal silicon chip 110 and the first doped amorphous silicon layer 131.In the present embodiment, the first intrinsic layer 121 is amorphous silicon layer, say, that be made up of intrinsic amorphous silicon.Usually, the thickness of the first intrinsic layer 121 is not more than 10nm, it is preferred to 5~10nm.So so that heterojunction solar battery has higher open-circuit voltage, the absorption to light of first intrinsic layer 121 can be reduced simultaneously, reduce cell resistance simultaneously, improve fill factor, curve factor.In the present embodiment, the thickness of the first intrinsic layer 121 is 6nm.
In like manner, the effect of the second intrinsic layer 122 is, is used for being passivated crystal silicon chip 110, makes the interface being positioned at the crystal silicon chip 110 of the second intrinsic layer 122 both sides and the second doped amorphous silicon layer 132 obtain purification, and then makes the open-circuit voltage of heterojunction solar battery 100 increase.The optical band gap of the second intrinsic layer 122 is between crystal silicon chip 110 and the second doped amorphous silicon layer 132.In the present embodiment, the second intrinsic layer 122 is amorphous silicon layer, say, that be made up of intrinsic amorphous silicon.Similarly, the thickness of the second intrinsic layer 122 is also not more than 10nm, it is preferred to 5~10nm.So so that heterojunction solar battery has higher open-circuit voltage, the absorption to light of second intrinsic layer 122 can be reduced simultaneously, reduce cell resistance simultaneously, improve fill factor, curve factor.In the present embodiment, the thickness of the second intrinsic layer 122 is 6nm.
It is, of course, understood that the present invention can also be not provided with the second intrinsic layer 122.
In the present embodiment, the first electrode 161 is anelectrode, and the second electrode 162 is back electrode.Specifically, the first 161 one-tenth of electrode is grid-like, is formed typically via silk screen printing.Second electrode 162, in stratiform, is more specifically full silver electrode.
Wherein, the effect of the first transparency conducting layer 151 is, improves the first doped amorphous silicon layer 131 and the first electrode 161 electric conductivity, effectively increases the collection of carrier.In the present invention, the first transparency conducting layer 151 inserts ferric chloride (GraphExeter) layer for Graphene.Graphene inserts the Graphene intercalation compound that ferric chloride (GraphExeter) is more than two-layer one order, and wherein intercalator is ferric chloride.Graphene inserts ferric chloride (GraphExeter) and can pass through commercially available, can also oneself prepare.Graphene is inserted ferric chloride (GraphExeter) layer and is adjusted Graphene surface resistance and work function by chemical doping.
Preferably, the thickness of the first transparency conducting layer 151 is 1~15nm.So its electric property and optical property are more excellent.
Wherein, the effect of the second transparency conducting layer 152 is, improves the second doped amorphous silicon layer 132 and the second electrode 162 electric conductivity, effectively increases the collection of carrier.In the present embodiment, the thickness of the second transparency conducting layer 152 is 45nm.In the present embodiment, the second transparency conducting layer 152 is tin indium oxide (ITO) layer.Certainly, the second transparency conducting layer 152 can also is that tungsten-doped indium oxide (IWO) layer, also or fluorine oxide stannum (FTO) layer.It is, of course, understood that the present invention can also arrange the second transparency conducting layer 152, also or arrange opaque conductive layer.
The heterojunction solar battery of the present invention, owing to adopting Graphene to insert tri-chlorination iron layer as the first transparency conducting layer, when keeping high-transmission rate (being typically in about 87%), its sheet resistance film resistor can be reduced to 15 Ω/, its conductivity is greatly improved, and then makes the conversion efficiency of heterojunction solar battery improve.
The preparation method that present invention also offers a kind of above-mentioned heterojunction solar battery.
The preparation method of a kind of heterojunction solar battery, comprises the steps:
The first intrinsic layer is formed in the side of crystal silicon chip;
First intrinsic layer is formed the first doped amorphous silicon layer;
First doped amorphous silicon layer is formed the first transparency conducting layer;First transparency conducting layer is that Graphene inserts tri-chlorination iron layer;
First transparency conducting layer is formed the first electrode;
Opposite side at crystal silicon chip forms the second electrode.
Wherein, in order to improve the performance of heterojunction solar battery, it is preferable that first crystal silicon chip to be carried out making herbs into wool and cleaning step.Wherein, making herbs into wool mode can adopt wet-method etching or dry method making herbs into wool;Wet-method etching generally uses the alkaline solution (such as: KOH, NaOH, tetramethyl oxyammonia etc.) of certain proportioning and carries out the anisotropic etch of certain time;Dry method making herbs into wool obtains figure generally by mask blank and re-uses reactive ion etching (RIE:ReactiveIonEtching) and perform etching (mainly through C2H4And SF6);Dry method making herbs into wool also can react ion etching (RIE) by machine when not having mask, and use gas is SF6And O2.To needing to be carried out step after crystal silicon chip making herbs into wool, the Main Function of cleaning remains in the metal ion on crystal silicon chip surface and the natural oxide film of crystal silicon chip surface formation after being in that removal making herbs into wool.It addition, when cleaning, the chemical liquid for removing crystal silicon chip surface film oxide can also play the effect to crystal silicon chip partial deactivation.Cleaning for crystal silicon chip, it is possible to adopt Chemical cleaning, for instance: using RCA washing liquid (alkalescence and acid hydrogen peroxide solution), alkaline hydrogen peroxide solution, proportioning is it may be that H2O:H2O2:NH4OH=5:1:1-5:2:1;Acid hydrogen peroxide solution, proportioning is it may be that H2O:H2O2: HC1=6:1:1-8:2:1;RCA washing liquid use condition is: 75 DEG C-85 DEG C, scavenging period 10-20 minute, and cleaning sequence is using acid hydrogen peroxide solution after first using alkaline hydrogen peroxide solution.
In order to improve the performance of heterojunction solar battery, the heterojunction solar battery of this enforcement also includes the second intrinsic layer, the second doped amorphous silicon layer and the second transparency conducting layer etc..
Wherein, the plasma enhanced chemical vapor deposition method that is formed by (PECVD, PlasmaEnhancedChemicalVaporDeposition) of the first intrinsic layer, the second intrinsic layer, the first doped amorphous silicon layer, the second doped amorphous silicon layer.Certainly, it is understandable that, it is not limited to aforesaid way, can also is that hot filament CVD (HWCVD, HotwireChemicalVaporDeposition) or high-frequency plasma strengthen the heavy method (VHF-PECVD) of chemical gaseous phase, also or other preparation methoies.
Preferably, the second transparency conducting layer is by reaction and plasma deposition (RPD).When forming the second transparency conducting layer, it is preferable that pass into argon and oxygen simultaneously, and oxygen/argon ratio is 2.5.
Wherein it is preferred to, Graphene inserts ferric chloride (GraphExeter) layer by wet method transfer (matrix etching) to be transferred the surface of the first doped amorphous silicon layer (to be transferred be).
Specifically, the first side surface of copper substrate forms Graphene by chemical vapour deposition (CVD) (CVD) method and insert ferric chloride (GraphExeter) layer.By the monomer of PDMS (polydimethylsiloxane) and initiator in 10:1 ratio mixing and stirring, then at exsiccator evacuation, eliminate bubble, be cast in template (silicon chip and glass), 98 DEG C of curing oven 1h, strip down after cooling and are namely fabricated to PDMS seal.Then being attached on microscope slide by PDMS seal one side, one side is attached on the second side surface of copper substrate;Microscope slide is driven in filling FeCl3On the culture dish of corrosive liquid so that copper substrate is immersed in corrosive liquid, soak the time about half a day, it is seen that be corroded to copper substrate, so that Graphene inserts ferric chloride (GraphExeter) layer and is attached on PDMS;PDMS is taken out from corrosive liquid, in deionized water rinsing 3-4 time;Graphene on PDMS is inserted on ferric chloride (GraphExeter) layer coining to be transferred, naturally dries 1h, place into 60 DEG C of baking 1h in baking oven so that Graphene contacts tightr with to be transferred;Tearing PDMS, final Graphene is successfully moved on to be transferred.
Preferably, the first electrode, the second electrode are formed by silk screen printing low-temperature silver slurry, and wherein drying temperature is 100 DEG C, and sintering temperature is 200 DEG C.
Each technical characteristic of above-described embodiment can combine arbitrarily, for making description succinct, all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics is absent from contradiction, all it is considered to be the scope that this specification is recorded.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to making some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.

Claims (10)

1. a heterojunction solar battery, it is characterized in that, including: crystal silicon chip, it is sequentially located at the first intrinsic layer on the side of described crystal silicon chip, the first doped amorphous silicon layer, the first transparency conducting layer and the first electrode, and is positioned at the second electrode of the opposite side of described crystal silicon chip;
Wherein, described first transparency conducting layer is that Graphene inserts tri-chlorination iron layer.
2. heterojunction solar battery according to claim 1, it is characterised in that the thickness of described first transparency conducting layer is 1~15nm.
3. heterojunction solar battery according to claim 1, it is characterised in that described first intrinsic layer is non-crystalline silicon.
4. heterojunction solar battery according to claim 1, it is characterised in that described crystal silicon chip is N-type crystalline silicon sheet, described first doped amorphous silicon layer is P-type non-crystalline silicon layer.
5. heterojunction solar battery according to claim 1, it is characterised in that described heterojunction solar battery also includes the reinforcement electric field unit between described second electrode and described crystal silicon chip;Described reinforcement electric field unit includes the second intrinsic layer and the second doped amorphous silicon layer that are sequentially located on the opposite side of described crystal silicon chip.
6. heterojunction solar battery according to claim 5, it is characterised in that described second intrinsic layer is non-crystalline silicon.
7. heterojunction solar battery according to claim 5, it is characterised in that described heterojunction solar battery also includes the second transparency conducting layer between described second electrode and described second doped amorphous silicon layer.
8. the preparation method of the heterojunction solar battery described in a claim 1, it is characterised in that comprise the steps:
The first intrinsic layer is formed in the side of crystal silicon chip;
Described first intrinsic layer forms the first doped amorphous silicon layer;
Described first doped amorphous silicon layer forms the first transparency conducting layer;Described first transparency conducting layer is that Graphene inserts tri-chlorination iron layer;
Described first transparency conducting layer forms the first electrode;
Opposite side at described crystal silicon chip forms the second electrode.
9. preparation method according to claim 8, it is characterised in that described first intrinsic layer and/or described first doped amorphous silicon layer using plasma strengthen chemical vapour deposition technique and formed.
10. preparation method according to claim 8, it is characterised in that described first transparency conducting layer is formed by wet method transfer.
CN201610279832.0A 2016-04-28 2016-04-28 Heterojunction solar cell and preparation method therefor Pending CN105720115A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111564505A (en) * 2020-05-18 2020-08-21 熵熠(上海)能源科技有限公司 Heterojunction solar cell with passivated double intrinsic layers and preparation method thereof
CN113013294A (en) * 2021-02-26 2021-06-22 江苏润阳悦达光伏科技有限公司 HJT heterojunction battery based on repeated printing and preparation method thereof

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