CN205609535U - Solar cell with heterojunction - Google Patents
Solar cell with heterojunction Download PDFInfo
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- CN205609535U CN205609535U CN201620380937.0U CN201620380937U CN205609535U CN 205609535 U CN205609535 U CN 205609535U CN 201620380937 U CN201620380937 U CN 201620380937U CN 205609535 U CN205609535 U CN 205609535U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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Abstract
The utility model relates to a solar cell field specifically discloses a solar cell with heterojunction, and it includes the crystal silicon chip, lies in the first intrinsic layer on one side of crystal silicon chip, first doping amorphous silicon layer, transparent conducting film, and positive electrode in proper order to and lie in graphite alkene layer on the opposite side of crystal silicon chip, and copper layer in proper order. Above -mentioned solar cell with heterojunction, owing to the back of the body field of adopting graphite alkene layer and copper layer as solar cell with heterojunction, wherein the conductivity can be improved as back conducting layer in graphite alkene layer, finally improves solar cell with heterojunction's short -circuit current density, carries high conversion efficiency, the copper layer is as the back electrode, and it is more low -priced to compare the silver electrode, has effectively reduced solar cell with heterojunction's material cost.
Description
Technical field
This utility model relates to area of solar cell, particularly relates to a kind of heterojunction solar battery.
Background technology
Heterojunction solar battery (HIT battery) is by adding between doped amorphous silicon layer and crystalline silicon substrate
Enter constructed by intrinsic layer.Heterojunction solar battery had both had high efficiency and the height of crystal silicon solar energy battery
Stability, simultaneously because energy consumption is little, technique is relatively easy, temperature characterisitic is more preferable, the most also can have relatively
High output.Receive much concern in recent years, one of main development direction having become as solaode.
Owing to the electric conductivity of non-crystalline silicon is poor, the back surface field of heterojunction solar battery is generally conductive layer and full silver
Electrode, conductive layer can increase the collection of carrier effectively.But, conductive layer is generally tin indium oxide
(ITO), the metal-oxide such as fluorine oxide stannum (FTO).The electric conductivity of these materials is low, is unfavorable for photoelectric conversion
The lifting of efficiency.It addition, the material cost of full silver electrode is higher.
Utility model content
Based on this, it is necessary to, material low for the electricity conversion of existing heterojunction solar battery becomes
This high problem, it is provided that the heterojunction solar battery that a kind of electricity conversion is high, the cost of material is low.
A kind of heterojunction solar battery, including: crystal silicon chip, it is sequentially located at the side of described crystal silicon chip
On the first intrinsic layer, the first doped amorphous silicon layer, transparency conducting layer and anelectrode, and be sequentially located at
Graphene layer on the opposite side of described crystal silicon chip and layers of copper.
Above-mentioned heterojunction solar battery, owing to using graphene layer and layers of copper as heterojunction solar battery
Back surface field, wherein graphene layer is as backside conductive layer, can improve conductivity, final improves the hetero-junctions sun
The short-circuit current density of energy battery, improves conversion efficiency；Layers of copper, as back electrode, compares silver electrode more honest and cleaner
Valency, effectively reduces the material cost of heterojunction solar battery.
Wherein in an embodiment, described heterojunction solar battery also include being positioned at described graphene layer with
Reinforcement electric field unit between described crystal silicon chip；Described reinforcement electric field unit includes being sequentially located at described crystal
The second intrinsic layer on the opposite side of silicon chip and the second doped amorphous silicon layer.
Wherein in an embodiment, the thickness of described graphene layer is 0.34～15nm.
Wherein in an embodiment, described graphene layer is deposited in described layers of copper by chemical gaseous phase.
Wherein in an embodiment, the thickness of described layers of copper is 20～50 μm.
Wherein in an embodiment, described transparency conducting layer is tungsten-doped indium oxide layer.
Wherein in an embodiment, the thickness of described transparency conducting layer is 60～100nm.
Wherein in an embodiment, described crystal silicon chip is N-type crystalline silicon sheet, described first doping amorphous
Silicon layer is P-type non-crystalline silicon layer.
Wherein in an embodiment, described first intrinsic layer is non-crystalline silicon.
Wherein in an embodiment, described second intrinsic layer is non-crystalline silicon.
Accompanying drawing explanation
Fig. 1 is the structural representation of the heterojunction solar battery of this utility model one embodiment.
Detailed description of the invention
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with specifically
Embodiment, is further elaborated to this utility model.Should be appreciated that described herein specifically
Embodiment, only in order to explain this utility model, is not used to limit this utility model.
It should be noted that when element is referred to as " being arranged at " another element, and it can be directly at another
On individual element or element placed in the middle can also be there is.When an element is considered as " connection " another yuan
Part, it can be directly to another element or may be simultaneously present centering elements.Used herein
Term " vertical ", " level ", "left", "right" and similar statement simply to illustrate that mesh
, being not offered as is unique embodiment.
Unless otherwise defined, all of technology used herein and scientific terminology with belong to of the present utility model
The implication that those skilled in the art are generally understood that is identical.Institute in description of the present utility model herein
The term used is intended merely to describe the purpose of specific embodiment, it is not intended that in limiting this utility model.
Term as used herein " and/or " include the arbitrary and all of one or more relevant Listed Items
Combination.
See Fig. 1, the heterojunction solar battery 100 of this utility model one embodiment, including: crystal silicon chip
110, be sequentially located at the first intrinsic layer 121 on the side (upside in Fig. 1) of crystal silicon chip 110,
One doped amorphous silicon layer 131, transparency conducting layer 151 and anelectrode 161；And it is sequentially located at crystal silicon chip
Second intrinsic layer the 122, second doped amorphous silicon layer 132 of the opposite side (downside in Fig. 1) of 110, stone
Ink alkene layer 152 and layers of copper 162.
In the present embodiment, heterojunction solar battery 100, in almost symmetry structure, so can reduce life
The thinning development of thermal stress and mechanical stress during product, the most beneficially crystal silicon chip 110.It addition, two
Face all can absorb light makes generated energy increase.
In this utility model, crystal silicon chip 110 and the first doped amorphous silicon layer 131 constitute PN junction.Crystal
Silicon chip 110 and the second doped amorphous silicon layer 132 composition add highfield (being also back of the body electric field).By adding highfield
The open-circuit voltage of heterojunction solar battery 100 can be improved further.It is, of course, understood that not
If adding highfield, say, that do not set the second doped amorphous silicon layer 132.
In the present embodiment, crystal silicon chip 110 is N-type crystalline silicon sheet (n-c-Si), and accordingly, first mixes
Miscellaneous amorphous silicon layer 131 is P-type non-crystalline silicon layer (p-a-Si), and the second doped amorphous silicon layer 132 is N-type amorphous
Silicon layer (n-a-Si).It is, of course, understood that be not limited to above-mentioned form, of the present utility model different
In matter joint solar cell, it is also possible to be crystal silicon chip 110 be p-type, accordingly, the first doped amorphous silicon
Layer 131 is N-type, and the second doped amorphous silicon layer 132 is p-type.
In the present embodiment, crystal silicon chip 110 uses N-type crystalline silicon sheet (n-c-Si), can make hetero-junctions too
The performance of sun energy battery 100 is more superior, it is possible to overcome the photic decay of battery using p-type, it addition,
The density at its high efficiency composition center is far below p-type so that electronics has higher life-span and diffusion length.Its
In, crystalline silicon can be monocrystal silicon or polysilicon.More specifically, the crystal silicon chip 110 of the present embodiment is N
Type monocrystalline silicon layer.
Specifically, the thickness of crystal silicon chip 110 is generally less than 200 μm.Preferably, crystal silicon chip 110
Thickness is 100～200 μm.The most both can save the use of silicon materials, and then reduce cost；Can carry again
High technology stability.
Preferably, the surface of crystal silicon chip 110 is matte；It is to say, crystalline silicon is carried out making herbs into wool.This
Sample can reduce the reflection of battery surface so that more photon can be absorbed by crystal silicon chip 110；Simultaneously
Also there is the effect that can remove surface of crystalline silicon damage.Preferably, matte is Pyramid matte, this
Sample is more beneficial for light and slants the inside of crystal silicon chip 110, reduces the reflectance of the light of battery surface, makes
Obtaining light path and become big, the number of photons quantitative change of absorption is many.Making herbs into wool mode can use wet-method etching or dry method making herbs into wool；
Wet-method etching generally uses the alkaline solution of certain proportioning (such as: KOH, NaOH, tetramethyl oxyammonia
Deng) carry out the anisotropic etch of certain time；Dry method making herbs into wool obtains figure again generally by mask blank
Reactive ion etching (RIE:Reactive Ion Etching) is used to perform etching and (mainly pass through C2H4And SF6)；
Dry method making herbs into wool also can carry out reactive ion etching (RIE) by machine in the case of not having mask, uses
Gas is SF6And O2.To needing to be carried out step, acting predominantly on of cleaning after crystal silicon chip making herbs into wool
Metal ion and the autoxidation of crystal silicon chip surface formation on crystal silicon chip surface is remained in after removing making herbs into wool
Film.It addition, when cleaning, it is right that the chemical liquid for removing crystal silicon chip surface film oxide can also play
The effect of crystal silicon chip partial deactivation.For the cleaning of crystal silicon chip, Chemical cleaning can be used, such as:
Use RCA washing liquid (alkalescence and acid hydrogen peroxide solution), alkaline hydrogen peroxide solution, proportioning it may be that
H2O:H2O2:NH4OH=5:1:1-5:2:1；Acid hydrogen peroxide solution, proportioning is it may be that H2O:H2O2:HC1
=6:1:1-8:2:1；RCA washing liquid use condition is: 75 DEG C-85 DEG C, and scavenging period 10-20 minute cleans
Order is using acid hydrogen peroxide solution after first using alkaline hydrogen peroxide solution.
Wherein, the effect of the first intrinsic layer 121 is, is used for being passivated crystal silicon chip 110, makes to be positioned at the first intrinsic
The layer crystal silicon chip 110 of 121 both sides and the interface of the first doped amorphous silicon layer 131 obtain purification, and then make
The open-circuit voltage of heterojunction solar battery 100 increases.The optical band gap of the first intrinsic layer 121 is between crystal
Between silicon chip 110 and the first doped amorphous silicon layer 131.In the present embodiment, the first intrinsic layer 121 is non-
Crystal silicon layer, say, that be made up of intrinsic amorphous silicon.Usually, the thickness of the first intrinsic layer 121 is little
In 10nm, preferably 5～10nm.So can be so that heterojunction solar battery has higher open circuit electricity
Pressure, reduces the absorption to light of first intrinsic layer 121 simultaneously, reduces cell resistance simultaneously, improves fill factor, curve factor.
In the present embodiment, the thickness of the first intrinsic layer 121 is 6nm.
In like manner, the effect of the second intrinsic layer 122 is, is used for being passivated crystal silicon chip 110, makes to be positioned at the second intrinsic
The layer crystal silicon chip 110 of 122 both sides and the interface of the second doped amorphous silicon layer 132 obtain purification, and then make
The open-circuit voltage of heterojunction solar battery 100 increases.The optical band gap of the second intrinsic layer 122 is between crystal
Between silicon chip 110 and the second doped amorphous silicon layer 132.In the present embodiment, the second intrinsic layer 122 is non-
Crystal silicon layer, say, that be made up of intrinsic amorphous silicon.Similarly, the thickness of the second intrinsic layer 122 is the most not
More than 10nm, preferably 5～10nm.So can be so that heterojunction solar battery has higher open circuit
Voltage, reduces the absorption to light of second intrinsic layer 122 simultaneously, reduces cell resistance simultaneously, improve fill because of
Son.In the present embodiment, the thickness of the second intrinsic layer 122 is 6nm.
It is, of course, understood that this utility model can also be not provided with the second intrinsic layer 122.
Usually, first intrinsic layer the 121, second intrinsic layer the 122, first doped amorphous silicon layer 131, second
Doped amorphous silicon layer 132 using plasma strengthens chemical vapour deposition technique (PECVD, Plasma Enhanced
Chemical Vapor Deposition).It is, of course, understood that be not limited to aforesaid way, also may be used
To be hot filament CVD (HWCVD, Hot wire Chemical Vapor Deposition) or height
Frequently PECVD sinks method (VHF-PECVD) also or other preparation methoies.
Wherein, the effect of transparency conducting layer 151 is, improves the first doped amorphous silicon layer 131 and anelectrode 161
Electric conductivity, increases the collection of carrier effectively.In the present embodiment, transparency conducting layer 151 is for mixing tungsten
Indium sesquioxide. (IWO) layer.Tungsten-doped indium oxide (IWO) layer has potential high carrier mobility characteristic,
In the case of ensureing identical electrical conductivity, compared with ITO layer, IWO layer has relatively low carrier concentration,
Therefore there is less Carriers Absorption and bigger plasma wavelength, and then IWO layer has in near-infrared region
There are high transmission rate and low absorptivity.Certainly, transparency conducting layer 151 can also is that tin indium oxide (ITO) layer,
Also or fluorine oxide stannum (FTO) layer.Preferably, transparency conducting layer 151 deposits (RPD) by reaction and plasma.
When forming transparency conducting layer 151, it is passed through argon and oxygen the most simultaneously, and oxygen/argon ratio is 2.5.
Preferably, the thickness of transparency conducting layer 151 is 60～100nm.So its electric property and optical property
More excellent.
In the present embodiment, anelectrode 161 becomes grid-like, is typically formed by silk screen printing.More specifically,
Forming anelectrode 161 by silk screen printing low-temperature silver slurry, wherein drying temperature is 100 DEG C, and sintering temperature is
200℃。
Wherein, layers of copper 162 is as back electrode.Preferably, the thickness of layers of copper 162 is 20～50 μm.So
The performance of heterojunction solar battery can be optimized.In the present embodiment, the thickness of layers of copper 162 is 25 μm.
Wherein, the effect of graphene layer 152 is, improves the second doped amorphous silicon layer 132 and leads with layers of copper 162
Electrical property, increases the collection of carrier effectively.Graphene layer 152 refers to that the material of this layer is Graphene,
Graphene layer 152 can only include a layer graphene, can also be that multi-layer graphene is constituted.At the present embodiment
In, the thickness of graphene layer is 0.34～15nm.So can optimize the property of heterojunction solar battery further
Energy.
Preferably, graphene layer 152 and layers of copper 162 are formed in the following way: layers of copper 162 (as
Substrate) a side surface on by chemical gaseous phase deposition (CVD) method formed graphene layer 152.Then by band copper
The graphene layer 152 of layer 162 is adhered on to be transferred.It is understood that transfer face is according to actual feelings
The difference of condition, can be opposite side surface or the table of the second doped amorphous silicon layer 132 of crystal silicon chip 110
Face.
Heterojunction solar battery 100 of the present utility model, owing to using graphene layer 152 and layers of copper 162 to make
For the back surface field of heterojunction solar battery, wherein graphene layer 152 is as backside conductive layer, can improve conduction
Rate, the final short-circuit current density improving heterojunction solar battery, improves conversion efficiency；Layers of copper 162 is made
For back electrode, compare silver electrode more cheap, effectively reduce the material cost of heterojunction solar battery.
Each technical characteristic of embodiment described above can combine arbitrarily, for making description succinct, the most right
The all possible combination of each technical characteristic in above-described embodiment is all described, but, if these skills
There is not contradiction in the combination of art feature, is all considered to be the scope that this specification is recorded.
Embodiment described above only have expressed several embodiments of the present utility model, its describe more concrete and
In detail, but therefore can not be interpreted as the restriction to utility model patent scope.It should be pointed out that, it is right
For those of ordinary skill in the art, without departing from the concept of the premise utility, it is also possible to do
Going out some deformation and improvement, these broadly fall into protection domain of the present utility model.Therefore, this utility model is special
The protection domain of profit should be as the criterion with claims.
Claims (10)
1. a heterojunction solar battery, it is characterised in that including: crystal silicon chip, is sequentially located at described
The first intrinsic layer, the first doped amorphous silicon layer, transparency conducting layer and anelectrode on the side of crystal silicon chip,
And it is sequentially located at the graphene layer on the opposite side of described crystal silicon chip and layers of copper.
Heterojunction solar battery the most according to claim 1, it is characterised in that described hetero-junctions is too
Sun can also include the reinforcement electric field unit between described graphene layer and described crystal silicon chip by battery；Described
Strengthen electric field unit and include that the second intrinsic layer being sequentially located on the opposite side of described crystal silicon chip and second is mixed
Miscellaneous amorphous silicon layer.
Heterojunction solar battery the most according to claim 1 and 2, it is characterised in that described graphite
The thickness of alkene layer is 0.34～15nm.
Heterojunction solar battery the most according to claim 1 and 2, it is characterised in that described graphite
Alkene layer is deposited in described layers of copper by chemical gaseous phase.
Heterojunction solar battery the most according to claim 1 and 2, it is characterised in that described layers of copper
Thickness be 20～50 μm.
Heterojunction solar battery the most according to claim 1 and 2, it is characterised in that described transparent
Conductive layer is tungsten-doped indium oxide layer.
Heterojunction solar battery the most according to claim 1 and 2, it is characterised in that described transparent
The thickness of conductive layer is 60～100nm.
Heterojunction solar battery the most according to claim 1 and 2, it is characterised in that described crystal
Silicon chip is N-type crystalline silicon sheet, and described first doped amorphous silicon layer is P-type non-crystalline silicon layer.
Heterojunction solar battery the most according to claim 1 and 2, it is characterised in that described first
Intrinsic layer is non-crystalline silicon.
Heterojunction solar battery the most according to claim 2, it is characterised in that described second
Levying layer is non-crystalline silicon.
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|---|---|---|---|
| CN201620380937.0U CN205609535U (en) | 2016-04-28 | 2016-04-28 | Solar cell with heterojunction |
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| CN201620380937.0U CN205609535U (en) | 2016-04-28 | 2016-04-28 | Solar cell with heterojunction |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107465391A (en) * | 2017-07-24 | 2017-12-12 | 协鑫集成科技股份有限公司 | Device, interface resistance test mode and application for test interface resistance |
| CN108074992A (en) * | 2016-11-18 | 2018-05-25 | 清华大学 | It is a kind of using carbon nanomaterial film as the crystal silicon solar energy battery of hetero-junctions back surface field |
-
2016
- 2016-04-28 CN CN201620380937.0U patent/CN205609535U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108074992A (en) * | 2016-11-18 | 2018-05-25 | 清华大学 | It is a kind of using carbon nanomaterial film as the crystal silicon solar energy battery of hetero-junctions back surface field |
| CN107465391A (en) * | 2017-07-24 | 2017-12-12 | 协鑫集成科技股份有限公司 | Device, interface resistance test mode and application for test interface resistance |
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Effective date of registration: 20230919 Address after: 201400 Nanqiao Zhenjianghai Economic Park, Fengxian District, Shanghai Patentee after: GCL SYSTEM INTEGRATION TECHNOLOGY Co.,Ltd. Patentee after: GCL INTEGRATION TECHNOLOGY (SUZHOU) Co.,Ltd. Patentee after: Wuhu GCL Integrated New Energy Technology Co.,Ltd. Address before: Room 125, building 2, No.58, Zhonghui Road, Suzhou Industrial Park, Suzhou, Jiangsu 215000 Patentee before: SUZHOU GCL SYSTEM INTEGRATION TECHNOLOGY INDUSTRIAL APPLICATION RESEARCH INSTITUTE Co.,Ltd. Patentee before: GCL INTEGRATION TECHNOLOGY (SUZHOU) Co.,Ltd. Patentee before: GCL SYSTEM INTEGRATION TECHNOLOGY Co.,Ltd. |
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| TR01 | Transfer of patent right |