CN115172602B - Doped metal oxide composite layer structure - Google Patents
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Abstract
The invention belongs to the technical field of solar cells, and particularly relates to an Atomic Layer Deposition (ALD) doped metal oxide composite layer structure. The invention provides a wide band gap doped metal oxide tunneling junction based on ALD continuous deposition, which comprises an ALD deposited metal oxide electron transport layer (including TiO 2 ZnO or SnO 2 ) And an ALD deposited doped nickel oxide hole transport layer. The composite layer structure is used for the perovskite laminated solar cell, has the advantages of small parasitic absorption, low deposition damage, conformal deposition and small leakage current, and can effectively reduce parasitic absorption loss and leakage current, reduce deposition damage and further improve the photoelectric conversion efficiency of the crystalline silicon/perovskite laminated cell.
Description
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to a doped metal oxide composite layer structure which is used for perovskite-crystalline silicon laminated solar cells.
Background
The main focus of solar photovoltaic technology development is to increase conversion efficiency and reduce manufacturing costs, thereby reducing the cost of electricity (LCOE). Currently, the energy conversion efficiency of crystalline silicon solar cells accounting for 95% of the market is already close to 29.4% of the theoretical limit. In order to improve the market competitiveness of photovoltaic cells, the stacked cells can break through the single junction cell efficiency limit by widening the spectral response range. Theoretical research shows that for a double-junction two-end laminated solar cell, the combination of a top cell with the material band gap of 1.65-1.75eV and a bottom cell with the material band gap of 1.10-1.20eV meets the best spectrum matching, and the energy of solar photons can be utilized to the maximum extent, and the theoretical conversion efficiency is as high as 44%. The perovskite/crystalline silicon laminated cell has the advantages of high sub-cell energy band matching degree, good process compatibility and similar application scene to the current main crystalline silicon cell, is a hot spot of the current laminated device research, and has the laboratory conversion efficiency rapidly improved from 13.7% in 2015 to 29.8% in 2021 and exceeds the limit efficiency of 29.4% of the single crystalline silicon cell.
In 2015, 13.7% perovskite/crystalline silicon double end stack was reported in the first report in cooperation of Buonassisi, university of Stanford, mcGehee et al, the university of Massa MedLayer cells (MailoaJP, etal.Appl.Phys.Lett.2015, 106, 121105) with single-sided polished HJT silicon cells as bottom cells, N-I-P normal perovskite as top cells, and doped thin film silicon as intermediate composite layer. The efficiency of such stacked devices is generally lower due to the more severe parasitic absorption of the N-I-P structured perovskite top cell. Therefore, in 2017 McGehee team, a perovskite top cell with a trans-P-I-N structure and a band gap of 1.63eV is designed, a single-side polished crystalline silicon cell is used as a bottom cell, a transparent conductive film ITO is used as a composite layer, and the thickness of the composite layer is 1cm 2 23.6% efficiency (m.d. mcgehee, et al, nat. Energy 2017,2, 17009) was achieved on the stacked device, which is an important innovation in the structure of the two-terminal stacked cell device and an important improvement in the device efficiency. Huang Jinsong et al quickly improved the efficiency of perovskite/HJT stacked devices based on single sided polishing to 25.4% by grain boundary passivation strategies for perovskite materials (j.s.huang, et al. Joule 2019,3, 177.). Xu Jixian, mcGehee, et al, in 2020, showed very excellent stability by the composition and energy band control of the ternary halogen, and the corresponding wide-bandgap perovskite top cell, which in turn was coupled with a single-sided polished HJT constructed two-terminal stack device, resulted in 27.1% photoelectric conversion efficiency (McGehee, et al science 2020, 367, 1097). However, the crystalline silicon cell generally has a textured structure to increase light absorption and utilization, so that the perovskite top cell is directly coupled on the textured crystalline silicon cell, and a larger development space is provided in the field of two-end stacked devices. In 2018, the doctor blain group (EPFL) of the lozenges federal institute of technology (EPFL) doped microcrystalline silicon tunnel junction (PECVD) was used to prepare the conformal perovskite top cell by combining physical deposition with solution spin-coating, which achieves a dual-textured stacked cell preparation with a device conversion efficiency of 25.2% (c.ballif, et al, nat, mater.2018, 17, 820). While the textured structure is advantageous for improving the short circuit current of the stacked cell, it presents challenges for the conformal fabrication of perovskite top cells. To overcome the problem, the solution spin-coating method is innovatively adopted by Sargent team of university of Toronto in 2020 to cover the perovskite film layer with the micron thickness on the suede structure with smaller pyramid size, and the indium oxide composite layer is combined to obtainA two-terminal laminated battery having an authentication conversion efficiency of 25.7% (e.h. sargent, et al science 2020, 367, 1135.) was obtained. Similarly, a Huang Jinsong team in north card Luo Nada reported a completely new laminate cell fabrication technique using knife coating to fill up a textured pyramid HJT bottom cell with perovskite material, resulting in a conversion efficiency of 26.2% (j.s. huang, et al joule 2020,4, 850.). In the same year, the korean institute of science and technology (KAIST) and the national laboratory for renewable energy (NREL) cooperate to regulate defects and photoelectric properties of perovskite by using the synergistic effect of two-dimensional and anion engineering, to improve the stability of perovskite battery, and to obtain 26.7% photoelectric conversion efficiency after lamination with HJT (b.shin, et al science 2020, 368, 6487.); at the end of 2020, helmholtz center (HZB) Albrecht et al reported an organic hole material selective contact strategy, which achieved perovskite/crystalline silicon tandem solar cells with efficiency stability of up to 29.15% using ITO composite layers (s.albrecht, et al science 2020, 370, 1300), which further improved the conversion efficiency of the tandem device to a level of 29.8% in 2021, which is a current world record. Recently, de Wolf team at the university of technology of King, shatex Dula (KAUST) has utilized multifunctional molecules to passivate defects of wide band gap perovskite, greatly improving stability, and achieving laminated cell efficiencies of 27.4% (Isikgor, et al, joule. 2021.05.013)% and 28.2% (J.Liu, et al, joule. 2021.11.003), respectively. Furthermore, the laminated initial business oxford photovoltaic company reported 28% and 29.5% perovskite/crystalline silicon laminated cell certification efficiencies in succession from 2018 to 2020, but they did not disclose any technical details.
In order to realize the effective connection of the perovskite top cell and the crystalline silicon bottom cell with wide forbidden bands, the middle composite layer should ensure the effective recombination of majority carriers of the two sub-cells and limit the recombination of minority carriers, so as to realize better current matching, which is important to the performance of perovskite/crystalline silicon laminated cell devices.
Currently, doped thin film silicon tunnel junctions and Indium Tin Oxide (ITO) are the most commonly used perovskite/crystalline silicon stacked cell intermediate composite layer materials. Doped thin film silicon is prepared by Plasma Enhanced Chemical Vapor Deposition (PECVD) technology, and the performance of the doped thin film silicon is mainly that ofThe doping concentration, thickness and other parameters of the silicon film determine that the higher the doping concentration is, the better the tunneling junction performance is; the ITO is most mature and widely used, and is usually deposited by magnetron sputtering, and the performance of the ITO as a composite layer is mainly determined by parameters such as the doping proportion of a target material, the chamber air pressure, the oxygen partial pressure, the sputtering power and the like. However, the main problem of the ITO and doped thin film silicon tunneling junction as a composite layer is that the thin film parasitic absorption is large, limiting the short-circuit current (J sc ) The method comprises the steps of carrying out a first treatment on the surface of the Secondly, ITO is relatively expensive, sputter deposition is more damaging, and deposition equipment for doped silicon films is more costly, requiring the use of toxic, flammable gases (e.g., silanes, phosphanes, and boranes). Therefore, developing an intermediate composite layer structure that is small in parasitic absorption, inexpensive, and small in deposition damage is critical to further improve the conversion efficiency of the stacked cell.
The Atomic Layer Deposition (ALD) technology has the advantages of small deposition damage, uniform film formation, shape retention and the like, and is widely applied to the deposition of functional films. ALD deposited metal oxide has the advantages of small parasitic absorption, adjustable work function and small leakage current (small transverse conductivity), and has potential to replace magnetron sputtering ITO and doping a thin film silicon tunneling junction as an intermediate composite layer of a laminated cell. Si/poly-Si (p) reported by Kcatchpole et al, national university of Australia + )/TiO 2 PVK laminated cell structure, ALD deposited TiO 2 Not only serves as an electron transmission layer, but also replaces the traditional ITO (indium tin oxide) serving as an intermediate composite layer, thereby effectively reducing parasitic absorption of the composite layer and laminating the battery J sc The conversion efficiency is obviously increased to 24.1 percent (K.R. catchpole, et al Sci. Adv.2018,4, 9711). Ho-Baillie et al report Si (p ++ )/SnO 2 The structure replaces the traditional interlayer, snO 2 Not only as electron transport layer of perovskite top cell, but also as silicon bottom cell p ++ The composite structure is formed with reduced voltage and current losses of the laminated cell (Ho-Baillie, et al energy environment. Sci.2018, 11, 2432.). The above results of the study initially demonstrate the great potential of metal oxides as intermediate composite layers.
Currently, perovskite/crystalline silicon stacked cells based on sputtered ITO and doped thin film silicon tunneling junctions as intermediate composite layers suffer from the following drawbacksThe point: the parasitic absorption of ITO and doped film silicon is larger, so that the short-circuit current of the laminated battery is limited; the deposition damage of sputtering ITO and PECVD deposited doped silicon films is large, and the open circuit voltage of a laminated device is reduced. Therefore, developing an intermediate composite layer structure with small parasitic absorption and small deposition damage is a key for further improving the conversion efficiency of the perovskite/crystalline silicon laminated cell. The tunneling junction based on the wide forbidden band doped metal oxide can not only meet the requirement of being used as a composite layer, but also be used as a carrier selection layer of a perovskite top battery and a crystal silicon bottom battery, and has great potential in reducing parasitic absorption, simplifying a preparation process and improving the conversion efficiency of a stacked device. However, only intermediate composite structures based on single-layer metal oxides (e.g. poly-Si (p) + )/TiO 2 And Si (p) ++ )/SnO 2 ) By applying the research of perovskite/crystalline silicon laminated batteries, the conductivity and the composite property of the perovskite/crystalline silicon laminated batteries are poor, and the device performance needs to be further improved.
Disclosure of Invention
In view of the shortcomings of the prior art, the invention provides an ALD continuous deposition doped metal oxide composite layer structure, which is characterized by comprising the following steps:
a crystalline silicon substrate;
a passivation layer deposited on the crystalline silicon substrate;
a tunneling junction layer deposited on the passivation layer, the tunneling junction layer comprising a doped nickel oxide hole transport layer and a doped metal oxide electron transport layer;
and the wide forbidden band perovskite absorption layer is arranged on the tunneling junction layer.
Preferably, the passivation layer material comprises one or more of hydrogenated amorphous silicon, silicon oxide and aluminum oxide, and is deposited to a thickness of 1-10nm.
Preferably, the doping element of the doped nickel oxide hole transport layer comprises one or more of aluminum, magnesium and zinc, the deposition method is atomic layer deposition, and the thickness of the deposition is 1-50nm.
Preferably, the metal oxide of the doped metal oxide electron transport layer comprises TiO 2 ZnO and SnO 2 One or more of the following deposition methodsAnd depositing a sub-layer, wherein the thickness of the deposited layer is 1-50nm.
Preferably, the doping element of the doped metal oxide electron transport layer includes one or more of aluminum, tantalum, gallium, niobium, hydrogen, boron, indium, fluorine, and antimony.
Further, tiO-doped 2 The doping elements include, but are not limited to, one or more of aluminum, tantalum, gallium and niobium, and the doping is realized by adopting an ALD (atomic layer deposition) super-cycle process;
doping elements of doped ZnO include, but are not limited to, one or more of hydrogen, aluminum, boron, gallium and indium, and doping is realized by adopting an ALD (atomic layer deposition) super-circulation process;
doped SnO 2 Including but not limited to one or more of fluorine, tantalum, antimony, indium, aluminum, boron, using ALD supercycle processes.
Preferably, the doped metal oxide composite layer structure further comprises an ultrathin carrier transport layer; the thickness of the ultrathin carrier transmission layer is 1-10nm.
When the doped metal oxide electron transport layer in the tunneling junction layer is deposited on the doped nickel oxide hole transport layer, the ultrathin carrier transport layer is an ultrathin electron transport layer, and is deposited between the doped metal oxide electron transport layer and the wide bandgap perovskite absorption layer;
when the doped nickel oxide hole transport layer in the tunneling junction layer is deposited on the doped metal oxide electron transport layer, the ultrathin carrier transport layer is an ultrathin hole transport layer, and is deposited between the doped nickel oxide hole transport layer and the wide bandgap perovskite absorption layer.
Further, the preparation material of the ultrathin electron transport layer comprises one or more of tin oxide, titanium oxide, zinc oxide, magnesium oxide or niobium oxide.
Further, the preparation material of the ultrathin hole-transporting layer comprises one or more of copper oxide, cuprous oxide, spiro-OMeTAD (2, 2', 7' -tetrakis [ N, N-di (4-methoxyphenyl) amino ] -9,9' -spirobifluorene), PTAA (poly [ bis (4-phenyl) (2, 4, 6-trimethylphenyl) amine ]), and CuSCN (cuprous thiocyanate).
Further, the ultrathin carrier transport layer comprises an intrinsic carrier transport layer and/or a doped carrier transport layer, and the deposition method comprises atomic layer deposition, high-temperature evaporation, a solution method or electron beam evaporation;
the doping elements of the ultrathin doped carrier transport layer include one or more of lithium, cesium, strontium, magnesium, cobalt, boron, aluminum, ruthenium, and rubidium.
The invention also provides a perovskite/crystalline silicon laminated solar cell which comprises the doped metal oxide composite layer structure.
Preferably, the preparation method of the perovskite/crystalline silicon laminated solar cell comprises the following steps:
s1: a crystal silicon bottom battery is selected, and the front surface of the crystal silicon bottom battery is an electron collecting end;
s2: depositing a doped metal oxide electron transport layer on the front surface of the crystalline silicon bottom cell by ALD;
s3: depositing a doped nickel oxide hole transport layer on the surface of the doped metal oxide electron transport layer by ALD to form a doped metal oxide tunneling junction;
s4: preparing a wide band gap perovskite absorption layer on the doped metal oxide tunneling junction; or a hole transport layer is deposited on the doped nickel oxide hole transport layer, so that the perovskite/crystalline silicon laminated solar cell is obtained; the forbidden bandwidth of the wide forbidden bandwidth perovskite absorption layer is 1.6-1.75eV.
Based on the method for realizing the intermediate composite layer structure of the doped metal oxide tunneling junction, the invention simultaneously provides a perovskite/crystalline silicon laminated cell structure with high efficiency and low cost, which is characterized in that a doped electron transport layer is deposited firstly, then a doped nickel oxide hole transport layer is deposited to form a tunneling junction to extract electrons of a crystalline silicon bottom cell and holes of a perovskite top cell, and the method for preparing the intermediate composite layer structure of the tunneling junction is combined with the laminated cell preparation method.
More specific battery structural characterization and battery preparation methods will be presented in the detailed description.
Compared with the prior art, the technical scheme of the invention has the following advantages:
(1) The ALD deposition doped metal oxide tunneling junction intermediate composite layer structure provided by the invention has the advantages of small parasitic absorption, low deposition damage, small leakage current, small composite potential barrier, compatibility with a complex light trapping structure crystal silicon bottom cell and the like, and can effectively improve the conversion efficiency of a perovskite/crystal silicon laminated cell and reduce the preparation cost.
(2) The perovskite/crystalline silicon laminated cell structure provided by the invention has the advantages of small parasitic absorption loss, small minority carrier recombination at a tunneling junction, obvious improvement of open-circuit voltage, short-circuit current and photoelectric conversion efficiency of the cell, simple process and low cost, is suitable for preparing large-size laminated cells, and has good industrialization potential.
Drawings
FIG. 1 is a process flow diagram (A) for preparing a (p-n) tunneling junction intermediate composite layer structure as described in example 1; the (p-n) tunneling junction intermediate composite layer (B) was prepared by the process described in example 1.
FIG. 2 is a process flow diagram (A) for preparing an intermediate composite layer of an (n-p) tunneling junction as described in example 2; the (n-p) tunneling junction intermediate composite layer (B) was prepared by the process described in example 2.
FIG. 3 is a process flow diagram (A) for preparing a (p-n) tunneling junction intermediate composite layer as described in example 3; the (n-p) tunneling junction intermediate composite layer (B) was prepared by the process described in example 3.
Fig. 4 is a schematic structural diagram of the perovskite/crystalline silicon solar cell described in example 4.
Fig. 5 is a schematic structural diagram of a perovskite/crystalline silicon solar cell as described in example 5.
Fig. 6 is a schematic structural diagram of a perovskite/crystalline silicon solar cell as described in example 6.
Fig. 7 is a schematic structural diagram of a perovskite/crystalline silicon stacked solar cell according to example 7.
Fig. 8 is a schematic structural diagram of a perovskite/crystalline silicon stacked solar cell according to example 8.
Fig. 9 is a schematic structural diagram of a perovskite/crystalline silicon stacked solar cell according to example 9.
Reference numerals illustrate: 101-silicon substrate, 102-a-Si: H passivation layer, 103-magnesium doped nickel oxide film, 104-tantalum doped tin oxide electron transport layer, 105-wide bandgap perovskite absorption layer, 201-silicon substrate, 202-a-Si: H passivation layer, 203-phosphorus doped a-Si: H, 204-aluminum doped titanium oxide electron transport layer, 205-zinc doped nickel oxide hole transport layer, 206-wide bandgap perovskite absorption layer, 301-silicon substrate, 302-SiO 2 Passivation layer, 303-aluminum doped nickel oxide film, 304-aluminum doped zinc oxide electron transport layer, 305-intrinsic SnO 2 Film, 306-perovskite film, 401-silicon substrate, 402-a-Si: H passivation layer, 403-boron doped a-Si: H layer, 404-ITO transparent electrode, 405-silver electrode, 406-aluminum doped titanium oxide electron transport layer, 407-magnesium doped nickel oxide hole transport layer, 408-wide bandgap perovskite light absorption layer, 409-C 60 Hole transport layer, 410-SnO 2 Buffer layer, 411-zinc doped indium oxide transparent electrode, 412-silver electrode, 501-silicon substrate, 502-a-Si: H passivation layer, 503-phosphorus doped a-Si: H layer, 504-ITO transparent electrode, 505-silver electrode, 506-aluminum doped nickel oxide film, 507-zinc doped tin oxide electron transport layer, 508-wide bandgap perovskite light absorption layer, 509-Spiro-OMeTAD hole transport layer, 510-MoO x Buffer layer, 511-zinc doped indium oxide transparent electrode, 512-silver electrode, 513-magnesium fluoride antireflection layer, 601-p type crystalline silicon substrate, 602-n type emitter, 603-Al 2 O 3 Passivation layer, 604-SiN x Antireflection film, 605 silver electrode, 606-tunneling SiO 2 Passivation layer, 607-aluminum doped nickel oxide film, 608-aluminum doped zinc oxide electron transport layer, 609-ultrathin SnO 2 Electron transport layer, 610-wide bandgap perovskite light absorption layer, 611-Spiro-OMeTAD hole transport layer, 612-molybdenum oxide buffer layer, 613-zinc doped indium oxide transparent electrode, 614-silver electrode, 615-magnesium fluoride anti-reflection layer, 701-silicon substrate, 702-tunneling SiO 2 Passivation layer, 703-phosphorus doped polysilicon, 704-SiN x Film, 705-silver electrode, 706-zinc doped nickel oxide film, 707-boron doped zinc oxide electron transport layer, 708-ultrathin SnO 2 An electron transport layer, 709-a wide band gap perovskite light absorption layer, 710-Spiro-OMeTAD hole transport layer, 711-molybdenum oxide buffer layer, 712-zinc doped indium oxide transparent electrode, 713-gold electrode, 714-magnesium fluoride anti-reflection layer, 801-silicon substrate,802-Al 2 O 3 passivation layer, 803-SiN x Antireflection film, 804-aluminum electrode, 805-p + Local back field, 806-tunneling SiO 2 Passivation layer, 807-hydrogen doped zinc oxide film, 808-zinc doped nickel oxide film, 809-wide band gap perovskite light absorption layer, 810-C 60 Electron transport layer 811-SnO 2 Buffer layer, 812-zinc doped indium oxide transparent electrode, 813-silver electrode, 814-lithium fluoride antireflection layer, 901-silicon substrate, 902-p-type emitter, 903-tunneling SiO 2 Passivation layer, 904-phosphorus doped polysilicon layer, 905-Al 2 O 3 /SiN x Laminated passivation film, 906-silver electrode, 907-tantalum doped tin oxide film, 908-aluminum doped nickel oxide film, 909-wide band gap perovskite light absorption layer, 910-C 60 Hole transport layer, 911-SnO 2 Buffer layer, 912-zinc doped indium oxide transparent electrode, 913-silver electrode, 914-magnesium fluoride anti-reflection layer.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the invention and practice it.
Example 1
A method for realizing a doped metal oxide (p-n) tunneling junction intermediate composite layer structure is provided, wherein a preparation process flow chart and a structure are respectively shown in fig. 1, and mainly comprise the following steps:
1) Selecting an n-type monocrystalline silicon wafer, polishing and etching with potassium hydroxide KOH alkaline solution to remove a damaged layer, and then cleaning with RCA to obtain a silicon substrate 101;
2) Depositing an a-Si:H passivation layer 102 on the surface of the silicon wafer by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) technology, wherein the thickness of the a-Si:H passivation layer is 5nm, and the deposition temperature is 200 ℃;
3) A magnesium-doped nickel oxide film 103 (NiO: mg) was deposited on the a-Si: H passivation layer, prepared by ALD superconduction, to a thickness of 6.0nm.
4) Preparation of tantalum doped tin oxide electron transport layer 104 (SnO) on nickel oxide film by ALD (atomic layer deposition) supercoyclization without breaking vacuum 2 Ta), thickness is 3nm.
5) A wide band gap perovskite absorption layer 105 was deposited on the tantalum doped tin oxide electron transport layer 104 by spin coating to a thickness of 1000nm.
The doped metal oxide (p-n) tunneling junction intermediate composite layer structure provided by the invention is formed, and as shown in figure 1, the structure has the advantages of low parasitic absorption, small deposition damage, small leakage current and good suede shape retention.
Example 2
The method for realizing the intermediate composite layer of the doped metal oxide (n-p) tunneling junction is mainly characterized by firstly depositing a doped metal oxide electron transport layer and then depositing a doped nickel oxide hole transport layer, thereby meeting the preparation requirements of laminated batteries with different structures, wherein the preparation process flow chart and the structure are respectively shown in figure 2, and mainly comprise the following process steps:
1) Selecting an n-type monocrystalline silicon wafer, polishing and etching with potassium hydroxide KOH alkaline solution to remove a damaged layer, and then cleaning with RCA to obtain a silicon substrate 201;
2) Depositing an a-Si:H passivation layer 202 on the surface of a silicon wafer by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) technology, wherein the thickness of the passivation layer is 5nm, and the deposition temperature is 200 ℃;
3) Depositing phosphorus doped a-Si on the surface of the silicon wafer by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) technology, wherein the thickness is 6nm, and the deposition temperature is 200 ℃;
4) Depositing an aluminum doped titania electron transport layer 204 (TiO) on the phosphorus doped a-Si H203 2 Al) is prepared by adopting an Atomic Layer Deposition (ALD) method, and the thickness is 10nm;
5) Under the condition of no breaking vacuum, depositing a zinc-doped nickel oxide hole transport layer 205 (NiO: zn) on the aluminum-doped titanium oxide electron transport layer 204 by ALD, wherein the thickness is 7nm;
6) A wide band gap perovskite absorber layer 206 was deposited on the electron transport layer using spin coating to a thickness of 900nm.
Thus, the doped metal oxide tunneling junction structure provided by the invention is formed, as shown in fig. 2. The structure has the excellent characteristics of low parasitic absorption, small deposition damage, small leakage current and good suede shape retention.
Example 3
A method for realizing a (p-n) tunneling junction intermediate composite layer structure based on embodiment 1 is provided, which is mainly characterized by adopting tunneling silicon oxide (SiO 2 ) The passivation layer replaces an a-Si-H passivation layer, a layer of ultrathin tin oxide is deposited on the electron transport layer to realize energy level matching with the perovskite layer, the energy level matching structure has higher transparency, the preparation process flow chart and the structure are respectively shown in figure 3, and the preparation process flow chart mainly comprises the following process steps:
1) A p-type monocrystalline silicon wafer is selected, a damaged layer is removed by polishing and etching with potassium hydroxide KOH alkali solution, and then RCA cleaning is performed, so that a silicon substrate 301 is obtained.
2) SiO is deposited on the surface of a silicon wafer by a high-temperature thermal oxidation method 2 Tunneling layer 302, having a thickness of about 1.4nm, is deposited at a temperature of 600 ℃.
3) In SiO 2 An aluminum doped nickel oxide film 303 (NiO: al) was deposited on the tunneling layer 302, and was prepared by Atomic Layer Deposition (ALD) to a thickness of 10.0nm.
4) Under the condition of no vacuum breaking, an ALD (atomic layer deposition) super-cycle is adopted to prepare an aluminum-doped zinc oxide electron transport layer 304 (AZO) on the aluminum-doped nickel oxide film, and the thickness is 10nm.
5) Deposition of intrinsic SnO by ALD on aluminum doped zinc oxide electron transport layer 304 without breaking vacuum 2 Film 305 has a thickness of 5nm.
6) In intrinsic SnO 2 A perovskite thin film 306 was deposited on the thin film 305 by spin coating to a thickness of 500nm.
Thus, the (p-n) tunneling junction intermediate composite layer structure provided by the invention is formed, as shown in fig. 3. The structure has the excellent characteristics of low parasitic absorption, small deposition damage, small leakage current and good suede shape retention.
Based on the above-mentioned preparation method for realizing the doped metal oxide tunneling junction intermediate composite layer structure, the following examples show the application of the tunneling junction intermediate composite layer structure to specific perovskite/crystalline silicon laminated cells, and show the structural characteristics of laminated cells with the tunneling junction intermediate composite layer structure and the preparation method thereof. In summary, the tunneling junction intermediate composite layer structure is mainly characterized in that the tunneling junction intermediate composite layer structure is applied between a crystalline silicon bottom cell and a perovskite top cell, is used for collecting multiple electrons to promote recombination and plays a passivation role to inhibit the multiple electrons from recombination, and the back structure of the crystalline silicon bottom cell can be compatible with most of the crystalline silicon solar cells at present.
Example 4
A laminated cell structure with the tunnel junction intermediate composite layer structure and a method for preparing the same are disclosed. The structure of the stacked cell provided in this embodiment is shown in fig. 4, and the bottom cell is a high-efficiency amorphous silicon heterojunction cell, wherein the front surface is an electron collecting end, and the back surface is a hole collecting end. The perovskite/crystalline silicon laminated cell preparation method specifically comprises the following steps:
1) N-type monocrystalline silicon is selected, a damaged layer on the surface of a silicon wafer is removed by adopting NaOH solution for corrosion, and then dilute KOH solution is utilized for texturing to obtain a silicon substrate 401 with a positive pyramid light trapping structure on two surfaces;
2) Depositing an a-Si: H passivation layer 402 on the front and back sides of the silicon substrate 401 by PECVD process, wherein the thickness is about 5nm, and the deposition temperature is 200 ℃;
3) Depositing a boron doped a-Si H layer 403 (12 nm) on the back surface by adopting a PECVD process, wherein the deposition temperature is 170 ℃ to form a full-area hole transport layer on the back surface;
4) An ITO transparent electrode 404 (indium tin oxide, about 110 nm) was deposited on the back using magnetron sputtering with a sheet resistance of about 120 Ω/sq; then depositing a grid-shaped silver electrode 405;
5) Continuously depositing an aluminum-doped titanium oxide electron transport layer 406 with a thickness of about 5nm and a magnesium-doped nickel oxide hole transport layer 407 (NiO: mg) with a thickness of about 6nm at a deposition temperature of 150 ℃ on the front side by adopting an ALD (atomic layer deposition) super-cyclic process;
6) Preparation of the wide bandgap perovskite light absorbing layer 408 (Cs) using spin coating 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 ) A band gap of about 1.68eV;
7) Preparation of C by thermal evaporation 60 A hole transport layer 409 having a thickness of 20nm;
8) Preparation of SnO by ALD 2 A buffer layer 410 having a thickness of 20nm;
9) Magnetron sputtering is adopted to produce SnO 2 A zinc-doped indium oxide transparent electrode 411 (IZO) is deposited on the buffer layer to a thickness of 100nm;
10 Finally, silver electrode 412 was prepared through a mask using high temperature evaporation to a thickness of 350nm.
The perovskite/crystalline silicon solar cell structure is formed, the external quantum efficiency of the laminated cell is shown in figure 4, the external quantum efficiency and short-circuit current of the laminated cell are obviously improved compared with the ITO composite layer, the J-V curve is shown in figure 4, and the J-V curve is shown in 1 multiplied by 1cm 2 The upper efficiency of the laminated cell on the area is 27.2%, which is improved by 1.3% compared with that of the laminated cell of the ITO composite layer, and the current density and open-circuit voltage are obviously improved compared with those of the laminated cell of the ITO composite layer, thus fully showing the advantages of doped metal oxide tunneling junction.
In fig. 4, the front side of the cell employs an (n-p) tunneling junction and the back side of the cell employs a full area hole passivation contact based on HJT.
Example 5
A laminated cell structure with the doped metal oxide tunneling junction intermediate composite layer structure and a method for preparing the same are disclosed. The structure of the laminated cell provided in this embodiment is shown in fig. 5, the front side of the bottom cell adopts the (p-n) tunneling junction middle composite layer described in embodiment 2, the back side of the bottom cell adopts full-area electronic passivation contact based on the heterojunction cell (HJT) structure, and the front side and the back side of the laminated cell respectively adopt grid lines and full-area silver electrodes. The perovskite/crystalline silicon laminated cell preparation method specifically comprises the following steps:
1) Selecting n-type monocrystalline silicon, removing a damaged layer on the surface of the silicon wafer by adopting NaOH corrosion, then utilizing diluted KOH solution for texturing, and then utilizing the diluted KOH solution for texturing to obtain a silicon substrate 501 with a positive pyramid light trapping structure on two sides;
2) Depositing an a-Si: H passivation layer 502 on the front and back surfaces of the silicon substrate 501 by PECVD process, wherein the thickness is about 5nm, and the deposition temperature is 200 ℃;
3) Adopting PECVD technology to deposit phosphor doped a-Si H layer 503 (5 nm) at 170 ℃ to form a full-area electron hole transport layer on the back;
4) An ITO transparent electrode 504 (about 110 nm) is deposited on the back surface by magnetron sputtering, and the square resistance is about 120 Ω/sq; silver electrode 505 is then deposited;
5) Continuously depositing an aluminum-doped nickel oxide hole transport layer 506 (NiOx: al) with a thickness of about 3nm and a zinc-doped tin oxide electron transport layer 507 (ZTO) with a thickness of about 6nm on the front side by adopting an ALD (atomic layer deposition) super-cycling process, wherein the deposition temperature is 200 ℃;
6) Preparation of the Wide bandgap perovskite light absorbing layer 508 (Cs) Using spin coating 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 ) A band gap of about 1.68eV;
7) Preparing a Spiro-OMeTAD hole transport layer 509 by adopting a spin coating method, wherein the thickness is 200nm;
8) A MoOx buffer layer 510 is prepared by adopting a thermal evaporation method, and the deposition temperature is 100 ℃ and the thickness is 12nm;
9) Preparation of Zinc doped indium oxide transparent electrode 511 (IZO) by magnetron sputtering with thickness of 100nm
10 Silver electrode 512 was prepared by high temperature thermal evaporation through a mask to a thickness of 100nm;
11 Finally, a magnesium fluoride anti-reflection layer 513 is plated by high temperature evaporation, and the thickness is 120nm.
The bottom cell front side in fig. 5 employs a (p-n) tunneling junction and the cell back side employs a full area electron passivating contact based on HJT.
Example 6
A laminated cell structure with the tunnel junction intermediate composite layer structure and a method for preparing the same are disclosed. The structure of the crystalline silicon battery provided by the embodiment is shown in fig. 6, the front side of the bottom battery adopts the (p-n) tunneling junction middle composite layer structure described in embodiment 3, the back side adopts an n-type doped emitter based on a PERC battery and a corresponding passivation film, a layer of ultrathin tin oxide is deposited on an electron transport layer of the top battery for energy level matching regulation, and the front side and the back side of the laminated battery adopt grid-line silver electrodes. The perovskite/crystalline silicon laminated cell preparation method specifically comprises the following steps:
1) Selecting a p-type crystalline silicon substrate 601, removing a surface damage layer by adopting NaOH corrosion, and preparing a pyramid suede by using a diluted KOH solution;
2) After RCA cleaning, phosphorus is diffused in a tube furnace to prepare an n-type emitter 602, wherein the diffusion temperature is 800 ℃, and the square resistance is about 100 ohm/sq;
3) After the surface phosphosilicate glass is removed by the diluted hydrofluoric acid solution, the front n-type emitter and the pyramid suede are removed by single-sided alkali polishing;
4) After cleaning, al is deposited on the back surface by ALD process 2 O 3 Passivation layer 603, thickness 10nm, deposition temperature 200 ℃;
5) Depositing a SiNx antireflection film 604 on the back by PECVD (plasma enhanced chemical vapor deposition) with the thickness of 65nm and the deposition temperature of 400 ℃;
6) The back surface adopts screen printing to prepare a silver electrode 605, and adopts a grid line-shaped distributed electrode pattern design;
7) And sintering at high temperature by using a belt furnace, and burning through SiNx by using silver paste on the back surface, so as to form ohmic contact with n+ for electron collection.
8) Preparation of tunneling SiO on front side by high temperature thermal oxidation 2 Passivation layer 606, 1.7nm thick, oxidized at 600 ℃ for 15 minutes;
9) On the front side SiO 2 ALD (atomic layer deposition) is adopted to deposit an aluminum-doped nickel oxide film 607 (NiO: al) on the passivation layer in a super-circulation manner, wherein the thickness is 6.0nm, and the deposition temperature is 200 ℃;
10 An aluminum-doped zinc oxide electron transport layer 608 (AZO) is deposited on the NiOx film in an ultra-cyclic manner by ALD, the thickness is 10nm, and the deposition temperature is 200 ℃;
11 Deposition of an ultra-thin layer of SnO on AZO by ALD 2 An electron transport layer 609, 1nm thick, at a deposition temperature of 100 ℃;
12 Preparation of a Wide bandgap perovskite light absorbing layer 610 (Cs) Using spin coating 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 ) A band gap of about 1.68eV;
13 A spiral-OMeTAD hole transport layer 611 is prepared by a spin coating method, and the thickness is 120nm;
14 Preparing a molybdenum oxide buffer layer 612 on the hole transport layer by a high-temperature thermal evaporation method, wherein the thickness of the molybdenum oxide buffer layer is 12nm;
15 Depositing zinc doped indium oxide transparent electrode 613 (IZO) on the molybdenum oxide buffer layer by magnetron sputtering to a thickness of 100nm;
16 Preparing a silver electrode 614 through a mask by high temperature evaporation with a thickness of 350nm;
17 Finally, a magnesium fluoride antireflection layer 615 is plated by high-temperature evaporation, and the thickness is 120nm.
The front side of the bottom cell in fig. 6 adopts the (p-n) tunneling junction intermediate composite layer structure described in example 3, and the back side adopts an n-type doped emitter and a corresponding passivation film based on a PERC cell.
Example 7
A laminated cell structure with the tunnel junction intermediate composite layer structure and a method for preparing the same are disclosed. The structure of the stacked cell according to this embodiment is shown in fig. 7, in which the bottom cell is a tunneling oxide passivation contact (TOPcon) based cell, the intermediate composite layer structure is a (p-n) tunneling junction as described in embodiment 3, and the front and back sides of the stacked cell are gate-line silver electrodes. The perovskite/crystalline silicon laminated cell preparation method specifically comprises the following steps:
1) N-type monocrystalline silicon is selected, a damaged layer on the surface of a silicon wafer is removed by adopting NaOH solution for corrosion, and then a diluted KOH solution double-sided alkali polishing process is utilized to obtain a silicon substrate 701;
2) Preparation of tunneling SiO on front and back surfaces by high temperature thermal oxidation after RCA cleaning 2 A passivation layer 702 having a thickness of 1.4nm;
3) The phosphorus doped polysilicon 703 is deposited on the back surface by Plasma Enhanced Chemical Vapor Deposition (PECVD) to a thickness of about 160nm;
4) Annealing at 900 ℃ for 15 minutes in nitrogen atmosphere;
5) Depositing a SiNx film 704 on the back surface by PECVD (plasma enhanced chemical vapor deposition) with the thickness of 110nm and the deposition temperature of 400 ℃;
6) The back surface adopts screen printing to prepare a silver electrode 705, and adopts a grid line-shaped distributed electrode pattern design;
7) Sintering at high temperature by using a belt furnace, burning through SiNx by using silver paste on the back, and forming ohmic contact with poly-Si (n+) for collecting electrons;
8) Depositing a zinc-doped nickel oxide film 706 (NiOx: zn) on the front surface by ALD (atomic layer deposition) with the thickness of 10.0nm and the deposition temperature of 200 ℃;
9) Boron doped zinc oxide electron transport layer 707 (BZO) was deposited over the NiOx film using ALD supercoyclization at a thickness of 8nm at a deposition temperature of 200 c,
10 Ultra-thin SnO layer is deposited on AZO by ALD ultra-circulation 2 Electron transport layer 708, 2nm thick, deposition temperature 100 ℃;
11 Preparation of a Wide bandgap perovskite light absorbing layer 709 (Cs) Using spin coating 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 ) A band gap of about 1.68eV;
12 Spin-coating method is used to prepare the Spiro-OMeTAD hole transport layer 710 with a thickness of 120nm;
13 Preparing a molybdenum oxide buffer layer 711 on the hole transport layer by adopting a high-temperature thermal evaporation method, wherein the thickness of the molybdenum oxide buffer layer is 12nm;
14 Depositing a zinc-doped indium oxide transparent electrode 712 (IZO) on the molybdenum oxide buffer layer by magnetron sputtering to a thickness of 100nm;
15 Preparing a gold electrode 713 with a thickness of 80nm by high-temperature thermal evaporation through a mask;
16 Finally, a magnesium fluoride anti-reflection layer 714 is plated by high-temperature evaporation, and the thickness is 120nm.
Fig. 7 shows a bottom cell with a front side employing a (p-n) tunneling junction intermediate composite layer structure as described in example 3, and a back side employing a TOPcon-based n-doped emitter and corresponding passivation film.
Example 8
A laminated cell structure with the tunnel junction intermediate composite layer structure and a method for preparing the same are disclosed. The structure of the laminated cell provided in this embodiment is shown in fig. 8, in which the bottom cell is a passivated emitter and back (PERC) cell, the middle composite layer structure is an (n-p) tunneling junction as described in embodiment 2, the front surface of the laminated cell is a gate-line silver electrode, and the back surface of the laminated cell is a full-area aluminum electrode. The perovskite/crystalline silicon laminated cell preparation method specifically comprises the following steps:
1) Selecting p-type monocrystalline silicon, removing a surface damage layer by adopting NaOH corrosion, and preparing a silicon substrate 801 with a single-sided pyramid light trapping structure by using a diluted KOH solution;
2) Deposition of Al on the backside after RCA cleaning using ALD process 2 O 3 A passivation layer 802, 10nm thick, at 200 ℃;
3) Depositing a SiNx antireflection film 803 on the back by PECVD, wherein the thickness is 75nm, and the deposition temperature is 400 ℃;
4) Slotting the back by a laser technology, preparing a back aluminum electrode 804 by screen printing, and forming a p+ local back field 805 by high-temperature sintering;
5) Preparation of tunneling SiO on front side by high temperature thermal oxidation 2 Passivation layer 806, 1.7nm thick, oxidizes at 600 ℃ for 15 minutes;
6) The hydrogen-doped zinc oxide film 807 (ZnO: H), the thickness of 10.0nm, and the zinc-doped nickel oxide film 808 (NiOx: zn), the thickness of 8.0nm, were deposited on the front surface by ALD with ALD supercoyclization at 200 ℃;
7) Preparation of a Wide bandgap perovskite light absorbing layer 809 (Cs) Using spin coating 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 ) A band gap of about 1.68eV;
8) Preparation of C by thermal evaporation 60 An electron transport layer 810 having a thickness of 18nm;
9) Preparation of SnO by ALD method 2 A buffer layer 811 having a thickness of 20nm;
10 Preparing a zinc-doped indium oxide transparent electrode 812 (IZO) with a thickness of 100nm by magnetron sputtering;
11 Silver electrode 813 is prepared through a mask by adopting a high-temperature thermal evaporation method, and the thickness is 100nm;
12 A lithium fluoride anti-reflection layer 814 was prepared by high temperature thermal evaporation to a thickness of 100nm.
In fig. 8, the front side of the bottom cell adopts the (p-n) tunneling junction intermediate composite layer structure described in example 3, and the back side adopts the structure of the local back surface field of the main flow PERC cell.
Example 9
A laminated cell structure with the tunnel junction intermediate composite layer structure and a method for preparing the same are disclosed. The structure of the stacked cell according to this embodiment is shown in fig. 9, in which the bottom cell is a tunneling oxide passivation contact (TOPcon) based cell structure, the middle composite layer structure is a (n-p) tunneling junction as described in embodiment 2, and the front and back sides of the stacked cell are gate-line silver electrodes. The perovskite/crystalline silicon laminated cell preparation method specifically comprises the following steps:
1) N-type monocrystalline silicon is selected, a damaged layer on the surface of a silicon wafer is removed by adopting NaOH solution for corrosion, and then a diluted KOH solution double-sided alkali polishing process is utilized to obtain a silicon substrate 901;
2) Boron diffusion in a tube furnace after RCA cleaning to prepare a p-type emitter 902, wherein the diffusion temperature is 950 ℃, and the sheet resistance is about 100 ohm/sq;
3) After removing borosilicate glass on the surface by using dilute hydrofluoric acid solution, removing the p-type emitter on the front surface by using single-sided alkali polishing, and preparing tunneling SiO on the front surface by high-temperature thermal oxidation after cleaning 2 A passivation layer 903 having a thickness of 1.4nm;
4) Depositing a phosphorus doped polysilicon layer 904 on the passivation layer by PECVD (plasma enhanced chemical vapor deposition) with the thickness of about 30nm, and annealing at 900 ℃ for 15 minutes under nitrogen atmosphere;
5) Deposition of Al on the backside by PECVD 2 O 3 A SiNx laminated passivation film 905 having a thickness of 10/100nm;
6) Preparing a silver electrode 906 on the back surface by screen printing, and designing a grid line-shaped distributed electrode pattern;
7) Sintering the aluminum alloy by using a belt furnace at high temperature, and burning through Al by using silver paste on the back surface 2 O 3 SiNx, forming an ohmic contact with p+ for hole collection;
8) Ultra-cyclic deposition of tantalum doped tin oxide film 907 (SnO) on polysilicon using ALD 2 Ta), thickness is 8nm, deposition temperature is 180 ℃;
9) An ALD (atomic layer deposition) ultra-cyclic deposition aluminum-doped nickel oxide film 908 (NiOx: al) with a thickness of 6nm and a deposition temperature of 200 ℃;
10 Preparation of a Wide bandgap perovskite light absorbing layer 909 (Cs) Using spin coating 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 ) A band gap of about 1.68eV;
11 Preparation of C by thermal evaporation 60 Hole transport layer 910, thickness 20nm;
12 Preparation of SnO by ALD 2 A buffer layer 911 having a thickness of 20nm;
13 Magnetron sputtering on SnO 2 Depositing a zinc doped indium oxide transparent electrode 912 (IZO) on the buffer layer, wherein the thickness is 100nm;
14 Silver electrode 913 is prepared by a mask by a high-temperature thermal evaporation method, and the thickness is 100nm;
15 A magnesium fluoride anti-reflection layer 914 is deposited by high temperature thermal evaporation and has a thickness of 140nm.
In fig. 9, the front side of the bottom cell adopts the (n-p) tunneling junction intermediate composite layer structure described in example 2, and the back side adopts the TOPcon cell structure.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (3)
1. A doped metal oxide composite layer structure, comprising:
a crystalline silicon substrate;
a passivation layer deposited on the crystalline silicon substrate; the passivation layer is made of silicon oxide;
a tunneling junction layer, an atomic layer is deposited on the passivation layer, and the tunneling junction layer is composed of an aluminum doped nickel oxide hole transport layer and a doped metal oxide electron transport layer;
the wide forbidden band perovskite absorption layer is arranged on the tunneling junction layer;
the doped metal oxide electron transport layer is prepared by adopting atomic layer deposition, is an aluminum doped zinc oxide electron transport layer, and is prepared by adopting atomic layer deposition, wherein the thickness of the deposition is 10nm;
the doped metal oxide composite layer structure further comprises an ultrathin carrier transmission layer;
the ultrathin carrier transport layer is an ultrathin electron transport layer and is deposited between the doped metal oxide electron transport layer and the wide band gap perovskite absorption layer; the ultrathin electron transport layer is prepared from intrinsic tin oxide with the thickness of 5nm.
2. The doped metal oxide composite layer structure of claim 1, wherein said doped nickel oxide hole transport layer is prepared by atomic layer deposition and has a thickness of 1-50 a nm a.
3. A perovskite/crystalline silicon stacked solar cell comprising the doped metal oxide composite layer structure of claim 1 or 2.
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