CN107465391A - Device, interface resistance test mode and application for test interface resistance - Google Patents
Device, interface resistance test mode and application for test interface resistance Download PDFInfo
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- CN107465391A CN107465391A CN201710608281.2A CN201710608281A CN107465391A CN 107465391 A CN107465391 A CN 107465391A CN 201710608281 A CN201710608281 A CN 201710608281A CN 107465391 A CN107465391 A CN 107465391A
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- 238000012360 testing method Methods 0.000 title claims abstract description 51
- 239000010703 silicon Substances 0.000 claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 45
- 239000013078 crystal Substances 0.000 claims abstract description 42
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 10
- 230000005611 electricity Effects 0.000 claims description 6
- 238000012544 monitoring process Methods 0.000 claims description 5
- 238000005286 illumination Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000009659 non-destructive testing Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 210000004276 hyalin Anatomy 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012113 quantitative test Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013082 photovoltaic technology Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 241000894007 species Species 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
- H02S50/00—Monitoring or testing of PV systems, e.g. load balancing or fault identification
- H02S50/10—Testing of PV devices, e.g. of PV modules or single PV cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
The present invention relates to a kind of device for test interface resistance, and it includes device main body, first electrode, positioned at the side of device main body；And second electrode, positioned at the opposite side of device main body；Device main body includes：Crystal silicon chip, the first intrinsic layer, positioned at crystal silicon chip close to the side of first electrode；First doped amorphous silicon layer, positioned at the first intrinsic layer close to the side of first electrode；First doped amorphous silicon layer and crystal silicon chip homotype.Above-mentioned device, the interface resistance situation of heterojunction solar battery to be detected can be simulated, and then by measuring the all-in resistance of the device, remove other resistance, and then obtain the interface resistance of device, then obtain the interface resistance of heterojunction solar battery to be detected；Namely the interface resistance of heterojunction solar battery can be tested by above-mentioned device, and carry out non-destructive testing.Present invention also offers a kind of interface resistance test mode and application.
Description
Technical field
The present invention relates to field of photovoltaic technology, more particularly to a kind of device, interface resistance for test interface resistance
Test mode and application.
Background technology
Heterojunction solar battery is a kind of typical high performance solar batteries, and it has, and temperature coefficient is low, is declined without photic
The features such as decreasing effect answers (LID), and potential-free induces attenuation effect (PID) and can be with generating electricity on two sides.The actual hair of solar cell
Electricity can be higher by 15%~30% than the polycrystal silicon cell of same nominal power, be especially suitable for the application in distributed power generation market.
The interface resistance of heterojunction solar battery is also to directly affect one of fill factor, curve factor (FF) factor.But for
Interface resistance there is no effective method of testing at present.
The content of the invention
Based on this, it is necessary to there is no asking for Validity Test method for existing heterojunction solar battery median surface resistance
A kind of topic, there is provided device that can be used for testing the interface resistance of heterojunction solar battery.
A kind of device for test interface resistance, including：
Device main body,
First electrode, positioned at the side of the device main body；
And second electrode, positioned at the opposite side of the device main body；
The device main body includes：
Crystal silicon chip,
First intrinsic layer, positioned at the crystal silicon chip close to the side of the first electrode；
First doped amorphous silicon layer, positioned at first intrinsic layer close to the side of the first electrode；Described first mixes
Miscellaneous amorphous silicon layer and the crystal silicon chip homotype.
Above-mentioned device, the interface resistance situation of heterojunction solar battery to be detected can be simulated, and then should by measurement
The all-in resistance of device, other resistance are removed, and then obtain the interface resistance of device, then obtain heterojunction solar to be detected
The interface resistance of battery；Namely the interface resistance of heterojunction solar battery can be tested by above-mentioned device, and carry out nothing
Damage test.
In one of the embodiments, the device main body is symmetrical structure.
In one of the embodiments, the device main body also includes the second intrinsic layer and the second doped amorphous silicon layer；
Second intrinsic layer and second doped amorphous silicon layer are respectively positioned between the crystal silicon chip and the second electrode；It is described
Second intrinsic layer is close to the crystal silicon chip, and second doped amorphous silicon layer is close to the second electrode；
Second doped amorphous silicon layer and the crystal silicon chip homotype.
In one of the embodiments, the device main body also includes non-positioned at the first electrode and the described first doping
The first transparency conducting layer between crystal silicon layer and between the second electrode and second doped amorphous silicon layer
Two transparency conducting layers.
In one of the embodiments, the device main body also include positioned at the crystal silicon chip and the second electrode it
Between heavily doped layer；The heavily doped layer and the crystal silicon chip homotype.
In one of the embodiments, the heavily doped layer to crystalline silicon substrates heavy doping by forming.
In one of the embodiments, the crystal silicon chip is N-type.
In one of the embodiments, the crystal silicon chip is p-type.
Present invention also offers a kind of interface resistance test mode of heterojunction solar battery.
The interface resistance test mode of a kind of heterojunction solar battery, it is characterised in that comprise the following steps：
Prepare device provided by the present invention；The technological parameter of device technological parameter corresponding with battery to be tested
It is identical；
The J-V curves of the device under light illumination are tested, and obtain the all-in resistance of the device；
According to the all-in resistance, interface resistance is calculated.
The interface resistance test mode of above-mentioned heterojunction solar battery, by simulating heterojunction solar electricity to be detected
The device of the interface resistance situation in pond, by measuring the all-in resistance of the device, other resistance are removed, and then obtain the interface of device
Resistance, then obtain the interface resistance of heterojunction solar battery to be detected；Namely can be with quantitative test by above-mentioned device
The interface resistance of heterojunction solar battery, and infringement will not be produced to heterojunction solar battery, i.e. the test is lossless
Test.
Present invention also offers a kind of application of device provided by the present invention.
A kind of application of device provided by the present invention in interface resistance monitoring.
Above-mentioned application, can with monitoring process parameter on influence caused by actual interface resistance, and then can with optimize technique, from
And it can further improve the performance of heterojunction solar battery.
Brief description of the drawings
Fig. 1 is the cross section structure schematic diagram of the device of an embodiment of the present invention.
Fig. 2 is the cross section structure schematic diagram of the device of another embodiment of the present invention.
Fig. 3 is the cross section structure schematic diagram of the device of a further embodiment of this invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with embodiment
The present invention is further elaborated.It should be appreciated that embodiment described herein is only to explain the present invention,
It is not intended to limit the present invention.
Unless otherwise defined, all of technologies and scientific terms used here by the article is with belonging to technical field of the invention
The implication that technical staff is generally understood that is identical.Term used in the description of the invention herein is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein " and/or " include one or more
The arbitrary and all combination of related Listed Items.
For silicon heterogenous solar cell, usually, its series resistance (Rs) is by electrode resistance (Relectrode)、
Electrode and transparent conductive film (Rc,TCO) contact resistance, the square resistance (R of transparent conductive filmTCO), doped amorphous silicon layer
Bulk resistor (Ra-Si), crystal silicon chip resistance (RSi) and interface resistance composition.Interface resistance can be divided into the interface resistance of p sides
(RInterface resistance, p side) and n sides interface resistance (RInterface resistance, n side).Wherein, the interface electricity of p sides
Hinder (RInterface resistance, p side) including the interface resistance (R between crystal silicon chip and p-type doped amorphous siliconc-Si/a-Si:H, p side) and transparent conductive film and p-type doped amorphous silicon layer between interface resistance (RTCO/p-a-Si:H).The interface resistance of n sides
(RInterface resistance, n side) including the interface resistance (R between crystalline silicon and n-type doping non-crystalline siliconc-Si/a-Si:H, n side) and
Interface resistance (R between transparent conductive film and n-type doping non-crystalline siliconTCO/n-a-Si:H).For the hetero-junctions sun of other structures
The composition of its series resistance (Rs) of energy battery, principle is identical with above-mentioned principle, simply specific to form parameter species difference.
The present inventor is by studying discovery, influence factor of the interface resistance with the physical property of interface both sides
(such as thermal history of amorphous silicon deposition technique, TCO depositing operations and battery etc.) is relevant, and with indirect with interracial contact portion
Part is unrelated.Such as the specific preparation technology of electrode is unrelated.In addition to interface resistance, other each several part resistance have the test hand of maturation
Section.RSi(Ra-Si) can be obtained by the resistivity and their THICKNESS CALCULATION for testing silicon base (amorphous silicon membrane)；RelectrodeCan
By testing the resistance of electrode, and the geometrical pattern for combining electrode is calculated；Rc,TCOCan be by testing contacts of the TCO with electrode
Resistance, and the geometrical pattern for combining electrode is calculated；RTCOCan be by testing TCO square resistance, and combine the geometry of electrode
Pattern is calculated.
Using identical amorphous silicon deposition technique and TCO depositing operations, R may be such thatc,TCO、RTCO、Ra-SiFor mesuring battary
With interface resistance test device for it is all identical；RInterface resistance, p sideFor the boundary of mesuring battary and P-type crystal silicon chip
Surface resistance test device is identical；RInterface resistance, n sideFor mesuring battary and the interface resistance device of N-type crystalline silicon piece
It is identical.By testing the test device all-in resistance of same process parameter, then other resistance are subtracted, and then obtain the boundary of test device
Surface resistance, namely obtain the interface resistance of heterojunction solar battery to be tested.
Referring to Fig. 1, the device 100 for test interface resistance of first embodiment of the invention, it includes device main body, position
In the first electrode 161 of device main body side (upside in Fig. 1) and positioned at device main body opposite side (downside in Fig. 1)
Second electrode 162.Wherein, device main body includes crystal silicon chip 110, is sequentially located at the side of crystal silicon chip 110 (in Fig. 1
Upside) on the first intrinsic layer 121, the first doped amorphous silicon layer 131 and the first transparency conducting layer 151；And it is sequentially located at crystalline substance
Second intrinsic layer 122 of the opposite side (downside in Fig. 1) of body silicon chip 110, the second doped amorphous silicon layer 132, second is transparent leads
Electric layer 152.
In the present embodiment, crystal silicon chip 110, the first doped amorphous silicon layer 131 and the second doped amorphous silicon layer 132 are
Homotype.Due to without special-shaped semiconductor, so PN junction is not present, namely the device 100 can not produce photogenerated current phenomenon.The device
Part is resistance device corresponding to one identical with the side interface resistance of heterojunction solar battery to be tested.
In the present embodiment, device main body is symmetrical structure.Namely device 100 includes two identical interface resistance lists
Member.Specifically, the first intrinsic layer 121, the first doped amorphous silicon layer 131, the first transparency conducting layer 151 form the first interface resistance
Unit.Second intrinsic layer 122, the second doped amorphous silicon layer 132, the second transparency conducting layer 152 form second contact surface resistance unit.
It is, of course, understood that the device 100 of the present invention can also be not provided with the first transparency conducting layer 151 and second
Transparency conducting layer 152, such doped amorphous silicon layer 131 of first intrinsic layer 121 and first form the first interface resistance unit.Second
The doped amorphous silicon layer 132 of intrinsic layer 122 and second forms second contact surface resistance unit.It now can be used for test conductive without first
The heterojunction solar battery of hyaline layer.
In the present embodiment, crystal silicon chip 110, the first doped amorphous silicon layer 131 and the second doped amorphous silicon layer 132 are equal
For N-type.It so can be used for test n sides interface resistance.That is, in the present embodiment, the all-in resistance of device 100 includes two n
Side interface resistance.
It is, of course, also possible to be to understand, crystal silicon chip 110, the first doped amorphous silicon layer 131 and second can also be
Doped amorphous silicon layer 132 is p-type.It so can be used for test p sides interface resistance.
Specifically, crystal silicon chip 110 can be monocrystalline silicon piece or polysilicon chip.In the present embodiment, crystal silicon chip 110 is
N type single crystal silicon piece.
Wherein, first electrode 161 and second electrode 162, those skilled in the art can be independently arranged according to actual conditions.
It is not specifically limited to this by the present invention, will not be repeated here.
Referring to Fig. 2, the device 100 for test interface resistance of second embodiment of the invention, it includes device main body, position
In the first electrode 161 of device main body side (upside in Fig. 2) and positioned at device main body opposite side (downside in Fig. 2)
Second electrode 162.Wherein, device main body includes crystal silicon chip 110, is sequentially located at the side of crystal silicon chip 110 (in Fig. 1
Upside) on the first intrinsic layer 121, the first doped amorphous silicon layer 131 and the first transparency conducting layer 151；And it is sequentially located at crystalline substance
The heavily doped layer 170 of the opposite side (downside in Fig. 1) of body silicon chip 110；Heavily doped layer 170 and the homotype of crystal silicon chip 110.
In the present embodiment, heavily doped layer 170 to crystalline silicon substrates heavy doping by forming.
In the present embodiment, device main body is unsymmetric structure.Namely device 100 only includes an interface resistance unit.
Specifically, the first intrinsic layer 121, the first doped amorphous silicon layer 131, the first transparency conducting layer 151 form interface resistance unit.
It is, of course, understood that the device 100 of the present invention can also be not provided with the first transparency conducting layer 151, such the
One intrinsic layer 121 and the first doped amorphous silicon layer 131 form the first interface resistance unit.Now test can be used for be led without first
The heterojunction solar battery of electric hyaline layer.
In the present embodiment, crystal silicon chip 110, the first doped amorphous silicon layer 131 are N-type.It so can be used for test n sides
Interface resistance.
It is, of course, also possible to be to understand, it can also be that crystal silicon chip 110, the first doped amorphous silicon layer 131 are p-type.
It so can be used for test p sides interface resistance.
Specifically, crystal silicon chip 110 can be monocrystalline silicon piece or polysilicon chip.In the present embodiment, crystal silicon chip 110 is
N type single crystal silicon piece.
In the present embodiment, first electrode, second electrode are grid electrode.It is, of course, understood that the present invention is simultaneously
This is not limited to, can also be other forms.Such as first electrode is grid electrode, second electrode is whole face electrode (such as Fig. 3 institutes
Show).
Above-mentioned device, the interface resistance situation of heterojunction solar battery to be detected can be simulated, and then should by measurement
The all-in resistance of device, other resistance are removed, and then obtain the interface resistance of device, then obtain heterojunction solar to be detected
The interface resistance of battery；Namely the interface resistance of heterojunction solar battery can be tested by above-mentioned device, and carry out nothing
Damage test.
Present invention also offers a kind of interface resistance test mode of heterojunction solar battery.
A kind of interface resistance test mode of heterojunction solar battery, comprises the following steps：
S1, prepare device provided by the present invention；The technological parameter of device technique ginseng corresponding with battery to be tested
Number is identical；
Step S1 purpose is to prepare and cell interface resistance identical resistance device to be tested.It is understood that
Corresponding technological parameter is identical with battery to be tested for the technological parameter of device, refers to the technological parameter phase for influenceing interface resistance
Together, the technological parameter for not influenceing interface resistance can be different.
S2, the J-V curves of test device under light illumination, and obtain the all-in resistance R of deviceAlways。
In step s 2, the test of J-V curves can be used well known to a person skilled in the art method, no longer superfluous herein
State.
S3, according to all-in resistance RAlways, interface resistance is calculated.
In step S3, other resistance (such as bulk resistor, square resistance, contact resistance etc.) of device, this can be used
Method known to art personnel obtains, and will not be repeated here.
Such as：For the interface resistance device (concrete structure such as Fig. 1) of P-type crystal silicon chip:
2Rinterface Resistance, p side=RAlways-RSi-Ra-Si-Rc,TCO-RTCO-Relectrode
In another example：For the interface resistance device (concrete structure such as Fig. 1) of N-type crystalline silicon piece:
2RInterface resistance, n side=RAlways-RSi-Ra-Si-Rc,TCO-RTCO-Relectrode
The interface resistance test mode of above-mentioned heterojunction solar battery, by simulating heterojunction solar electricity to be detected
The device of the interface resistance situation in pond, by measuring the all-in resistance of the device, other resistance are removed, and then obtain the interface of device
Resistance, then obtain the interface resistance of heterojunction solar battery to be detected；Namely can be with quantitative test by above-mentioned device
The interface resistance of heterojunction solar battery, and infringement will not be produced to heterojunction solar battery, i.e. the test is lossless
Test.
Present invention also offers a kind of application of device provided by the present invention.
A kind of application of device provided by the present invention in interface resistance monitoring.
By changing a technological parameter, different devices is prepared, then by calculating the interface resistance of different components, therefore
And influence of the technological parameter to interface resistance can be detected.
Such as under the depositing operation of different transparent conductive film layers, prepare the heterojunction solar of P-type crystal silicon chip
The J-V curves of device corresponding to battery.It so both can intuitively see the depositing operation of different transparent conductive film layers
Influence to interface resistance.
Above-mentioned application, can with monitoring process parameter on influence caused by actual interface resistance, and then can with optimize technique, from
And it can further improve the performance of heterojunction solar battery.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
- A kind of 1. device for test interface resistance, it is characterised in that including：Device main body,First electrode, positioned at the side of the device main body；And second electrode, positioned at the opposite side of the device main body；The device main body includes：Crystal silicon chip,First intrinsic layer, positioned at the crystal silicon chip close to the side of the first electrode；First doped amorphous silicon layer, positioned at first intrinsic layer close to the side of the first electrode；First doping is non- Crystal silicon layer and the crystal silicon chip homotype.
- 2. the device according to claim 1 for test interface resistance, it is characterised in that the device main body is symmetrical Structure.
- 3. the device according to claim 2 for test interface resistance, it is characterised in that the device main body also includes Second intrinsic layer and the second doped amorphous silicon layer；Second intrinsic layer and second doped amorphous silicon layer are respectively positioned on described Between crystal silicon chip and the second electrode；Second intrinsic layer is close to the crystal silicon chip, second doped amorphous silicon Layer is close to the second electrode；Second doped amorphous silicon layer and the crystal silicon chip homotype.
- 4. the device according to claim 3 for test interface resistance, it is characterised in that the device main body also includes The first transparency conducting layer between the first electrode and first doped amorphous silicon layer and positioned at the described second electricity The second transparency conducting layer between pole and second doped amorphous silicon layer.
- 5. the device according to claim 1 for test interface resistance, it is characterised in that the device main body also includes Heavily doped layer between the crystal silicon chip and the second electrode；The heavily doped layer and the crystal silicon chip homotype.
- 6. the device according to claim 5 for test interface resistance, it is characterised in that it is right that the heavily doped layer passes through Crystalline silicon substrates heavy doping is formed.
- 7. the device for test interface resistance according to claim any one of 1-6, it is characterised in that the crystalline silicon Piece is N-type.
- 8. the device for test interface resistance according to claim any one of 1-6, it is characterised in that the crystalline silicon Piece is p-type.
- 9. the interface resistance test mode of a kind of heterojunction solar battery, it is characterised in that comprise the following steps：Prepare the device described in any one of claim 1~8；The technological parameter of device work corresponding with battery to be tested Skill parameter is identical；The J-V curves of the device under light illumination are tested, and obtain the all-in resistance of the device；According to the all-in resistance, interface resistance is calculated.
- A kind of 10. application of the device in interface resistance monitoring described in any one of claim 1~8.
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| CN201710608281.2A CN107465391B (en) | 2017-07-24 | 2017-07-24 | For the device of test interface resistance, interface resistance test mode and application |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243274A (en) * | 2011-05-05 | 2011-11-16 | 昆明理工大学 | Method for measuring and calculating interface resistivity of Pb-Sn-Al laminated composite material |
| CN104007319A (en) * | 2014-06-10 | 2014-08-27 | 湖北工业大学 | Method for measuring equivalent parallel-connection resistance value of multi-junction concentrating solar battery |
| CN104977470A (en) * | 2014-04-14 | 2015-10-14 | 日置电机株式会社 | Measurement apparatus and method of measurement |
| EP2966124A1 (en) * | 2014-07-09 | 2016-01-13 | Heraeus Deutschland GmbH & Co. KG | Electro-conductive paste with characteristic weight loss for low temperature application |
| CN205609535U (en) * | 2016-04-28 | 2016-09-28 | 苏州协鑫集成科技工业应用研究院有限公司 | Solar cell with heterojunction |
-
2017
- 2017-07-24 CN CN201710608281.2A patent/CN107465391B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243274A (en) * | 2011-05-05 | 2011-11-16 | 昆明理工大学 | Method for measuring and calculating interface resistivity of Pb-Sn-Al laminated composite material |
| CN104977470A (en) * | 2014-04-14 | 2015-10-14 | 日置电机株式会社 | Measurement apparatus and method of measurement |
| CN104007319A (en) * | 2014-06-10 | 2014-08-27 | 湖北工业大学 | Method for measuring equivalent parallel-connection resistance value of multi-junction concentrating solar battery |
| EP2966124A1 (en) * | 2014-07-09 | 2016-01-13 | Heraeus Deutschland GmbH & Co. KG | Electro-conductive paste with characteristic weight loss for low temperature application |
| CN205609535U (en) * | 2016-04-28 | 2016-09-28 | 苏州协鑫集成科技工业应用研究院有限公司 | Solar cell with heterojunction |
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