CN104600157A - Manufacturing method of hetero-junction solar cell and hetero-junction solar cell - Google Patents
Manufacturing method of hetero-junction solar cell and hetero-junction solar cell Download PDFInfo
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- CN104600157A CN104600157A CN201510016061.1A CN201510016061A CN104600157A CN 104600157 A CN104600157 A CN 104600157A CN 201510016061 A CN201510016061 A CN 201510016061A CN 104600157 A CN104600157 A CN 104600157A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
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- 238000000576 coating method Methods 0.000 claims description 118
- 238000000034 method Methods 0.000 claims description 51
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 43
- 238000000151 deposition Methods 0.000 claims description 21
- 230000008021 deposition Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910000085 borane Inorganic materials 0.000 claims description 3
- UORVGPXVDQYIDP-UHFFFAOYSA-N trihydridoboron Substances B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 20
- 239000010410 layer Substances 0.000 description 166
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 51
- 229910052710 silicon Inorganic materials 0.000 description 50
- 239000010703 silicon Substances 0.000 description 50
- 238000005240 physical vapour deposition Methods 0.000 description 16
- 239000013078 crystal Substances 0.000 description 14
- 230000000694 effects Effects 0.000 description 13
- 210000002268 wool Anatomy 0.000 description 12
- 235000008216 herbs Nutrition 0.000 description 11
- 238000004140 cleaning Methods 0.000 description 8
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- 238000002161 passivation Methods 0.000 description 8
- 239000002131 composite material Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 229910021419 crystalline silicon Inorganic materials 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000005286 illumination Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
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- 230000008901 benefit Effects 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
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- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
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- 230000007613 environmental effect Effects 0.000 description 1
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- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000001795 light effect Effects 0.000 description 1
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- -1 tetramethyl oxyammonia Chemical compound 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a manufacturing method of a hetero-junction solar cell. The manufacturing method of the hetero-junction solar cell comprises the steps that a substrate is provided; first intrinsic buffer layers are formed on one side or two sides of the substrate; second intrinsic buffer layers are formed on the two sides of the substrate with the first intrinsic buffer layers; doping layers, namely the first doping layer and the second doping layer, are formed on the two sides of the substrate with the second intrinsic buffer layers; transparent conducting layers are formed on the two sides of the substrate with the doping layers; or a transparent conducting layer is formed on one side of the substrate with the doping layers, and a transparent conducting oxide/metal composite layer is formed on the other side of the substrate with the doping layers. Therefore, the photoelectric conversion efficiency of the hetero-junction solar cell is improved. In addition, the invention provides the hetero-junction solar cell.
Description
Technical field
The application relates to new energy field, is specifically related to a kind of manufacture method and heterojunction solar battery of heterojunction solar battery.
Background technology
Solar cell also can be referred to as photovoltaic cell, its a kind of new-generation technology utilizing photovoltaic effect solar radiation to be directly converted to electric energy.Because it has the advantages such as raw material abundance, clean, safety, life-span be long, be considered to one of the most promising reproducible energy technology.
Current crystal silicon solar energy battery comprises monocrystaline silicon solar cell, polysilicon solar cell and high efficiency crystalline silicon solar cell etc.
The conversion efficiency of monocrystaline silicon solar cell is very high, and technology is comparatively ripe, but needs with high-purity silicon single crystal rod for raw material due to it, and the manufacturing cost making battery comparatively greatly, is difficult to large-scale promotion application.
Almost, it is lower than monocrystaline silicon solar cell in manufacturing cost for the manufacture craft of polysilicon solar cell and single crystal silicon solar cell.But it is then lower that the photoelectric conversion efficiency of polysilicon solar cell compares monocrystaline silicon solar cell, and the useful life of polysilicon solar cell is also short than monocrystaline silicon solar cell.
High efficiency crystalline silicon solar cell comprises: HIT (Hetero-junction with Intrinsic Thin layer, amorphous silicon/silicon/crystalline silicon heterojunction) battery, IBC (Interdigitated back contact, all back-contact electrodes contact crystal silicon) battery etc.; Wherein, HIT solar cell is a kind of mixed type solar battery utilizing crystalline silicon substrates and amorphous silicon membrane to make, and it is in conjunction with the advantage of monocrystaline silicon solar cell and non-crystal silicon solar cell.This HIT solar cell has the features such as preparation technology's temperature is low, conversion efficiency is high, hot properties is good, is a kind of lower price high efficiency battery, therefore, and one of HIT solar cell several high performance solar batteries technology becoming current main flow.
So-called amorphous silicon/silicon/crystalline silicon heterojunction solar battery (HIT:Hetero-junction with intrinsic Thinlayer) structure is exactly between P type amorphous silicon hydride and N-shaped silicon substrate, and increases the intrinsic hydrogenated amorphous silicon membrane of one deck between N-shaped amorphous silicon hydride and N-shaped silicon substrate respectively.After taking this technological measure, change the performance of PN junction.Thus make conversion efficiency reach 25.57%, open circuit voltage reaches 740mV, and all technique can realize below 230 DEG C.
As can be seen here, why HIT battery can obtain photoelectric conversion efficiency high is like this that the passivation of this intrinsic amorphous silicon layer to crystal silicon surface makes its interfacial characteristics be improved owing to inserting an intrinsic amorphous silicon layer in the p-n junction of solar cell.Therefore, intrinsic amorphous silicon layer needs to have certain thickness and wider optical band gap, makes illumination as much as possible be transmitted to polysilicon regions, and then reaches high performance HIT battery.But the thickness of intrinsic amorphous silicon layer affects HIT battery performance key factor, on the one hand, because the conductance of intrinsic amorphous silicon layer own is lower, therefore, the too thick series resistance that will increase battery of intrinsic amorphous silicon layer, make the corresponding reduction of fill factor, curve factor, and then battery conversion efficiency is reduced; For making crystal silicon, there is good sunken light effect, need to carry out making herbs into wool process to crystal silicon, because its surface roughness after crystal silicon making herbs into wool process increases, if intrinsic amorphous silicon layer is too thin, it is difficult to uniform deposition at crystal silicon on the surface, and then good passivation effect can not be played to heterojunction boundary, also just cannot reduce the battery efficiency loss caused because of Interface composites; On the other hand, because intrinsic amorphous silicon layer is directly formed at crystal silicon deposited on silicon, crystal silicon epitaxial growth and mixed phase growth can be caused, cause producing high defect state density in silicon atom structure, and then cause interface quality lower.
Based on above-mentioned, how a kind of manufacture method and heterojunction solar battery of heterojunction solar battery are provided, the impact of intrinsic amorphous silicon layer thickness on battery performance can be reduced, and prevent intrinsic amorphous silicon layer from growing mutually with blending together at crystal silicon Epitaxial growth, become technical problem urgently to be resolved hurrily.
Summary of the invention
The application provides a kind of manufacture method of heterojunction solar battery, to solve the problems of the technologies described above.
The application provides a kind of manufacture method of heterojunction solar battery, comprising: provide substrate; The first intrinsic resilient coating is formed in described substrate one or both sides; The second intrinsic resilient coating is formed in the both sides of the substrate with described first intrinsic resilient coating; Form doped layer in the both sides of the substrate with described second intrinsic resilient coating, be called the first doped layer and the second doped layer; Transparency conducting layer is formed respectively in the both sides of the substrate with described doped layer; Or forming transparency conducting layer in the side of the substrate with described doped layer, opposite side forms transparent conductive oxide/metal composite layer.
Preferably, described first intrinsic resilient coating and/or the second intrinsic resilient coating are set to single or multiple lift, and adopt chemical vapour deposition technique, heated filament chemical vapor deposition or thermal oxidation method to deposit formation.
Preferably, described first intrinsic resilient coating is a-SiOx:H intrinsic layer, and sedimentary condition is: the reacting gas selected is SiH
4and CO
2; Deposition temperature range is more than or equal to 200 DEG C, is less than or equal to 230 DEG C; Deposition pressure scope, for being more than or equal to 0.2mbar, is less than or equal to 0.8mbar; SiH
4flow be scope for being more than or equal to 200sccm, be less than or equal to 800sccm; CO
2range of flow, for being more than or equal to 20sccm, is less than or equal to 50sccm; 40MHz very high frequency(VHF) power density scope is for being more than or equal to 0.012W/cm
2, be less than or equal to 0.025W/cm
2.
Preferably, the thickness range of described first intrinsic resilient coating is more than or equal to 1nm, is less than or equal to 25nm.
Preferably, described second intrinsic resilient coating is a-Si:H intrinsic layer, and sedimentary condition is: the reacting gas selected is SiH
4, depositing temperature be scope for being more than or equal to 220 DEG C, be less than or equal to 230 DEG C, deposition pressure be scope for being more than or equal to 0.5, be less than or equal to 0.7mbar, SiH
4range of flow, for being more than or equal to 400sccm, is less than or equal to 800sccm, and 40MHz very high frequency(VHF) power density scope is for being more than or equal to 0.012W/cm
2, be less than or equal to 0.025W/cm
2.
Preferably, the thickness range of described second intrinsic resilient coating, for being more than or equal to 1nm, is less than or equal to 25nm.
Preferably, described first doped layer is P type doped layer, and the second doped layer is N-type doped layer; Or first doped layer be N-type doped layer, the second doped layer is P type doped layer.
Preferably, described first doped layer is the amorphous silicon layer of doping phosphine, and described second doped layer is the amorphous silicon layer of doping trimethyl borine.
Preferably, be tin indium oxide at the deposition materials of described transparency conducting layer; The deposition materials of described transparent conductive oxide/metal composite layer is tin indium oxide/silver.
The application also provides a kind of heterojunction solar battery, comprising: substrate; First intrinsic resilient coating is set in the one or both sides of described substrate; The second intrinsic resilient coating is formed in the both sides of the substrate with described first intrinsic resilient coating; In the both sides of the substrate with described second intrinsic resilient coating, doped layer is set; In the both sides of the substrate with described doped layer, transparency conducting layer is set respectively; Or transparency conducting layer is set in the side of the substrate with described doped layer, opposite side forms transparent conductive oxide/metal composite layer.
Preferably, described first intrinsic resilient coating and/or the second intrinsic resilient coating are set to single or multiple lift structure.
Preferably, described first doped layer is P type doped layer, and the second doped layer is N-type doped layer; Or first doped layer be N-type doped layer, the second doped layer is P type doped layer.
Compared with prior art, the application has the following advantages: by first depositing the first intrinsic resilient coating on substrate, to provide higher energy gap, illumination can be projected in substrate, promotes photoelectric conversion efficiency; Form the second intrinsic resilient coating in the both sides of the substrate with this first intrinsic resilient coating again, thus prevent the second intrinsic resilient coating at substrate Epitaxial growth or mixed growth; Therefore, the heterojunction solar battery side manufacture method that the application provides can avoid battery to be subject to the impact of the factor such as intrinsic layer thickness and epitaxial growth, and the photoelectric conversion efficiency caused declines, thus promotes battery performance.
Accompanying drawing explanation
Fig. 1 is the flow chart of a kind of heterojunction solar battery manufacture method that the application provides;
Fig. 2 is the first embodiment flow chart of a kind of heterojunction solar battery manufacture method that the application provides;
Fig. 3 is the second embodiment flow chart of a kind of heterojunction solar battery manufacture method that the application provides;
Fig. 4 is the structural representation of the first embodiment of a kind of heterojunction solar battery that the application provides;
Fig. 5 is the structural representation of the second embodiment of a kind of heterojunction solar battery that the application provides.
Embodiment
Set forth a lot of detail in the following description so that fully understand the application.But the application can be much different from alternate manner described here to implement, those skilled in the art can when doing similar popularization without prejudice to when the application's intension, and therefore the application is by the restriction of following public concrete enforcement.
Heterojunction solar battery (HIT) requires to have good passivation effect to heterojunction boundary, thus the battery efficiency reducing to cause because of Interface composites is lost.And when deposition on substrate intrinsic layer, need intrinsic layer to have applicable thickness and wider optical band gap, to make more illumination can project substrate region by intrinsic layer, thus improve battery conversion efficiency.Therefore, this application provides a kind of manufacture method of heterojunction solar battery, as follows:
Please refer to shown in Fig. 1, Fig. 1 is the flow chart that the application provides a kind of manufacture method of heterojunction solar battery, and this manufacture method comprises step:
Step S100: substrate is provided;
Step S110: form the first intrinsic resilient coating in described substrate one or both sides;
Step S120: form the second intrinsic resilient coating in the both sides of the substrate with described first intrinsic resilient coating;
Step S130: form doped layer in the both sides of the substrate with described second intrinsic resilient coating, be called the first doped layer and the second doped layer;
Step S140: form transparency conducting layer respectively in the both sides of the substrate with described doped layer, or form transparency conducting layer in the side of the substrate with described doped layer; Or forming transparency conducting layer in the side of the substrate with described doped layer, opposite side forms transparent conductive oxide/metal composite layer.
Above-mentioned manufacture method, by first depositing the first intrinsic resilient coating on substrate, to provide higher energy gap, makes illumination can project in substrate, promotes photoelectric conversion efficiency; On the substrate with this first intrinsic resilient coating, form the second intrinsic resilient coating again, thus prevent the second intrinsic resilient coating at substrate Epitaxial growth or mixed growth.
The specific implementation of above-mentioned steps is as follows:
Please refer to shown in Fig. 2, Fig. 2 is the first embodiment flow chart of a kind of heterojunction solar battery manufacture method that the application provides; This embodiment specifically comprises the steps:
Step S100-1: substrate is provided;
Crystal silicon material selected by this substrate, and this crystal silicon material can be monocrystalline silicon body or polysilicon body, can select n type single crystal silicon sheet in the present embodiment, and its thickness range is more than or equal to 150um, and be less than or equal to 300um, and be preferably 180um, resistivity is 3 Ω cm.Silicon chip is needed first to carry out making herbs into wool and cleaning to it, the object of making herbs into wool is the reflection reducing battery surface, make more photon can by substrate absorption, usual making herbs into wool is that silicon chip surface is treated to Pyramid, this shape is more conducive to light and slants silicon chip inside, reduce the light reflectance of battery surface, make light path become large, the number of photons quantitative change that silicon chip absorbs as active layer is many; Making herbs into wool also has the effect can removing silicon chip surface damage simultaneously.
Wherein, making herbs into wool mode can adopt wet-method etching or dry method making herbs into wool; Wet-method etching can use the alkaline solution of certain proportioning (such as: KOH, NaOH, tetramethyl oxyammonia etc.) to carry out the anisotropic etch of certain hour; Dry method making herbs into wool mainly obtains figure by mask blank and re-uses reactive ion etching (RIE:Reactive Ion Etching) and carry out etching (mainly through C
2h
4and SF
6); Dry method making herbs into wool can carry out reactive ion etching (RIE) by machine when not having mask, and use gas is SF
6and O
2.
To needing silicon chip to clean after silicon wafer wool making, the Main Function of cleaning remains in the metal ion of silicon chip surface and the natural oxide film of silicon chip surface formation after being to remove making herbs into wool.In addition, when cleaning, the chemical liquid for removing silicon chip surface oxide-film can also play the effect to wafer sections passivation.For the cleaning of silicon chip, chemical cleaning can be adopted, such as: use RCA washing lotion (alkalescence and acid hydrogen peroxide solution), No. RCAI is alkaline hydrogen peroxide solution, and proportioning can be, H
2o:H
2o
2: NH
4oH=5:1:1-5:2:1; No. RCAII is acid hydrogen peroxide solution, and proportioning can be, H
2o:H
2o
2: HC
1=6:1:1-8:2:1; RCA washing lotion service condition is: 75 DEG C-85 DEG C, scavenging period 10-20 minute, is using RCAII after cleaning sequence first uses RCAI.
It should be noted that, silicon chip can adopt N-type or P type, adopts N-type to be described this manufacture method in the present embodiment, but is not limited to N-type.Cleaning way for silicon chip is also not limited to above-mentioned RCA mode, and when adopting RCA to clean, required cleaning condition also can set according to actual needs.
Step S110-1: form the first intrinsic resilient coating in described substrate side;
In this step, the first intrinsic resilient coating can adopt amorphous silica material (a-SiOx:H), by chemical vapour deposition technique by the side of amorphous silicon oxide deposition of material at silicon chip, forms the first intrinsic resilient coating.This chemical vapour deposition technique can strengthen chemical vapour deposition technique (PECVD:PlasmaEnhanced Chemical Vapor Deposition) or hot filament CVD (HWCVD:Hotwire Chemical Vapor Deposition) or very high frequency plasma and strengthens chemical gaseous phase and sink method (VHF-PECVD) or other preparation methods by using plasma, adopt very high frequency plasma to strengthen chemical gaseous phase in the present embodiment and sink method (VHF-PECVD), deposit the first intrinsic resilient coating, sedimentary condition can be: adopt SiH
4and CO
2for reacting gas; Depositing temperature is more than or equal to 200 DEG C, is less than or equal to 230 DEG C, is preferably 220 DEG C; Deposition pressure scope, for being more than or equal to 0.2mbar, is less than or equal to 0.8mbar, is preferably 0.5mbar; Thickness range, for being more than or equal to 1nm, is less than or equal to 25nm, SiH
4range of flow, for being more than or equal to 200sccm, is less than or equal to 800sccm, is preferably 400sccm; CO
2range of flow, for being more than or equal to 20sccm, is less than or equal to 50sccm, is preferably 33sccm; 40MHz very high frequency(VHF) power density scope is for being more than or equal to 0.012W/cm
2, be less than or equal to 0.025W/cm
2, be preferably 0.015W/cm
2.
Because the first intrinsic resilient coating a-SiOx:H energy gap is at more than 1.8ev, and its absorption system is less, therefore, the introducing of the first intrinsic resilient coating a-SiOx:H, sunlight can be made to enter in silicon chip through doped layer more fully, thus improve the light conversion efficiency of solar cell.
Step S120-1: form the second intrinsic resilient coating in the both sides of the substrate with described first intrinsic resilient coating;
In this step, the second intrinsic resilient coating can select hydrogen amorphous silicon material (a-Si:H), and the sedimentary condition of this second intrinsic resilient coating is: reacting gas is SiH
4, deposition temperature range, for being more than or equal to 220 DEG C, is less than or equal to 230 DEG C; Deposition pressure scope, for being more than or equal to 0.5, is less than or equal to 0.7mbar; SiH
4range of flow, for being more than or equal to 400sccm, is less than or equal to 800sccm; 40MHz very high frequency(VHF) power density scope is for being more than or equal to 0.012W/cm
2, be less than or equal to 0.025W/cm
2; Deposit thickness scope, for being more than or equal to 1nm, is less than or equal to 25nm.A large amount of hydrogen atom is there is due in amorphous silicon (a-Si:H) material that the second intrinsic resilient coating adopts, therefore, can well the defect state of passivation silicon chip surface, and a-Si:H second intrinsic resilient coating energy gap is probably between 1.7-1.8ev.
The deposit thickness summation of described first intrinsic resilient coating and the second intrinsic resilient coating is in and is greater than 2nm and is less than 50nm.
Because the first intrinsic resilient coating and the second intrinsic resilient coating all have higher energy gap, therefore, it is possible to make silicon chip absorb the irradiation of sunlight more fully, and then realize better photoelectric conversion efficiency, improve battery performance.
Be provided with the first intrinsic resilient coating in the side of silicon chip, the second resilient coating can be optimized on the one hand and cause light conversion efficiency to decline owing to being subject to the impact of thickness; The second resilient coating can also be prevented in silicon chip epitaxial growth on the other hand.
Step S130-1: form doped layer, that is: the first doped layer and the second doped layer in the both sides of the substrate with described second intrinsic resilient coating;
In this step, form doped layer in the described substrate both sides with the second intrinsic resilient coating, being positioned at on-chip can be the first doped layer, and being positioned under substrate can be the second doped layer.Described first doped layer is P type doped amorphous silicon layer, and it can as Window layer, and dopant material can choose trimethyl borine (TMB), and thickness, for being more than or equal to 4nm, is less than or equal to 40nm, is preferably 10nm.Described second doped layer is N-type doped amorphous silicon layer, and dopant material can choose phosphine (PH
3), thickness, for being more than or equal to 4nm, is less than or equal to 40nm, is preferably 30nm.
Be understandable that, described first doped layer and the second doped layer position can exchange, that is: the N-type doped amorphous silicon layer of can choosing as Window layer is the first doped layer, and the second doped layer can be P type doped amorphous silicon layer.
Step S140-1: form transparency conducting layer respectively in the both sides of the substrate with described doped layer; Or forming transparency conducting layer in the side of the substrate with described doped layer, opposite side forms transparent conductive oxide/metal composite layer.
In this step, be positioned at the side of the substrate with described first doped layer, that is: on P type doped amorphous silicon layer, adopt physical vapour deposition (PVD) (PVD:Physical Vapor Deposition) mode deposit transparent conductive layer as front electrode, the thickness range of this transparency conducting layer is more than or equal to 50nm, and be less than or equal to 120nm, can be preferably 80nm, material can be tin indium oxide (ITO) conducting film, and sheet resistance is 30 Ω.Be positioned at the side of the substrate with described second doped layer, that is:, on N-type doped amorphous silicon layer, physical vapour deposition (PVD) (PVD:Physical Vapor Deposition) mode is adopted to deposit the transparency conducting layer identical with the transparency conducting layer on described first doped layer as back electrode.And then form the heterojunction solar battery of double-side photic.
By forming transparency conducting layer respectively in doped layer both sides, and then form the heterojunction solar battery of multiaspect light.
For this step, be understandable that, only can also form transparency conducting layer in the side of doped layer, at the composite bed that opposite side formation transparent conductive oxide and metal are formed, such as: on P type doped amorphous silicon layer, physical vapour deposition (PVD) (PVD:Physical Vapor Deposition) mode deposit transparent conductive layer is adopted; On N-type doped amorphous silicon layer, adopt physical vapour deposition (PVD) (PVD:Physical VaporDeposition) mode deposit transparent conductive oxide and metal, and then the composite bed formed, as back electrode.The compound (ITO/Ag) that this composite bed can select tin indium oxide (transparent conductive oxide) to form with silver (metal), thickness range is more than or equal to 10nm, and be less than or equal to 120nm, and then form the heterojunction solar battery of one side light.
The composite back electrode using above-mentioned transparent conductive oxide (TCO) and metal to form, can improve back reflection effect, improves photoelectric conversion efficiency.
In step S140-1, according to practical application needs and ambient conditions, the utilance that different sensitive surfaces has improved heterojunction solar battery can be set.
The description of the first execution mode of the manufacture method of a kind of heterojunction solar battery provided for the application above, what it illustrated is the manufacture method that substrate side forms the first resilient coating, be understandable that, the first resilient coating that substrate is formed, not only can be positioned at the side of substrate, also the both sides of substrate can be positioned at, as shown in Figure 3, Fig. 3 is the second embodiment flow chart of a kind of heterojunction solar battery manufacture method that the application provides, that is: form the step of the first resilient coating respectively in substrate both sides.
Still form the first resilient coating respectively in substrate both sides can manufacture according to actual needs for forming the first resilient coating in substrate side, therefore, the first resilient coating is not limited to only be formed in substrate side or formed in the both sides of substrate.
The step of the second embodiment that Fig. 3 provides is as follows:
Step S100-2: substrate is provided;
This step can with reference to the step S100-1 in the first embodiment.
Step S110-2: form the first intrinsic resilient coating respectively in described substrate both sides;
Step S110-1 in this step and the first embodiment is similar, difference is, this step forms the first intrinsic resilient coating respectively in the both sides of substrate, that is: chemical vapor deposition amorphous silica material (a-SiOx:H) is adopted respectively in the both sides of silicon chip, and then form the first intrinsic resilient coating, concrete depositional mode refer step S110-1.
Step S120-2: form the second intrinsic resilient coating in the both sides of the substrate with described first intrinsic resilient coating;
This step can with reference to the step S120-1 in the first embodiment.
Step S130-2: form doped layer, that is: the first doped layer and the second doped layer in the both sides of the substrate with described second intrinsic resilient coating;
This step can with reference to the step S120-1 in the first embodiment.
Step S140-2: form transparency conducting layer respectively in the both sides of the substrate with described doped layer, or form transparency conducting layer in the side of the substrate with described doped layer, opposite side forms transparent conductive oxide/metal composite layer.
This step can with reference to the step S140-1 in the first embodiment.
The difference of the second embodiment and the first embodiment is only the first resilient coating, and the first embodiment is formed in substrate side, and the second embodiment is formed respectively in substrate both sides, so, second embodiment concrete form mode with reference to the first embodiment, therefore, can not repeated.
It should be noted that, two kinds of execution modes can be selected according to heterojunction solar battery applied environment situation, such as: when applied environment is applicable to one side light, first intrinsic resilient coating can be set in the side of sensitive surface, and in sensitive surface side, transparency conducting layer is set, opposite side is without the need to arranging the first resilient coating and transparency conducting layer, and the composite bed that can consist of transparent conductive oxide and metal substitutes transparency conducting layer.When applied environment is applicable to double-side photic, the first intrinsic resilient coating can be formed respectively in substrate both sides, and form transparency conducting layer in the substrate both sides with this first intrinsic resilient coating.
Disclosed above the manufacture method embodiment of a kind of heterojunction solar battery that the application provides, corresponding with described embodiment of the method, disclosed herein as well is a kind of heterojunction solar battery embodiment, please refer to Fig. 4, Fig. 4 is the structural representation of a kind of heterojunction solar battery first embodiment that the application provides.
A kind of heterojunction solar battery that the application provides comprises: substrate 300, the first intrinsic resilient coating 310, second intrinsic resilient coating 320, first doped layer 330, second doped layer 340, transparency conducting layer 350, transparent conductive oxide/metal composite layer 360.
Described substrate 300 can adopt monocrystalline silicon piece or polysilicon chip, can be N-type or P type.Because the performance of N-type silicon chip is more superior, and the light-induced degradation phenomenon of battery on P-type silicon sheet can be overcome, and in N-type silicon chip material the density at high efficiency composition center far below P-type material, make electronics have higher life-span and diffusion length, so normal conditions lower silicon slice selects N-type, what select in the embodiment of the present application is n type single crystal silicon sheet, its thickness range is more than or equal to 150um, and be less than or equal to 300um, be preferably 180um, resistivity is 3 Ω cm.
In the side of described substrate 300, described first intrinsic resilient coating 310 is set, described first intrinsic resilient coating 310 not only plays the effect of the defect of passivation silicon chip surface, also make sunlight enter in silicon chip through doped layer more fully, thus improve the light conversion efficiency of solar cell.This first intrinsic resilient coating 310 can adopt amorphous silica material (a-SiOx:H), and its thickness range, for being more than or equal to 1nm, is less than or equal to 25nm.Described first intrinsic resilient coating 310 can be set to multilayer or single layer structure as required.
Form the second intrinsic resilient coating 320 respectively in the both sides of the described substrate 300 with described first intrinsic resilient coating 310, described second intrinsic resilient coating 320 plays the effect of passivation silicon chip surface too.Hydrogen amorphous silicon material (a-Si:H) can be selected.
In the both sides of the substrate 300 with described second intrinsic resilient coating 320, doped layer is set respectively, that is: the first doped layer 330 and the second doped layer 340; On substrate 300 and the side with described first intrinsic resilient coating 310 is the first doped layer 330, what be positioned at described substrate 300 opposite side is the second doped layer 340, described first and second doped layers 340 can be doped amorphous silicon layer, described first doped layer 330 is N-type doped amorphous silicon layer, and described second doped layer 340 is P type doped amorphous silicon layer.Be understandable that, described first doped layer 330 can be P type doped amorphous silicon layer, and described second doped layer 340 can be N-type amorphous silicon doped layer.
In the present embodiment, transparency conducting layer 350 is arranged on to be had on the first doped layer 330, and the second doped layer 340 is set to transparent conductive oxide/metal composite layer 360, forms one side Colony structure (shown in figure 4).But, be understandable that, also can arrange on described first doped layer 330 respectively at described transparency conducting layer 350 and on the second doped layer 340, form double-side photic structure.Fig. 4 is only a kind of structural representation of one side light, and the structure of the heterojunction solar battery that the application provides is not limited to shown in Fig. 4.
Based on above-mentioned, please refer to shown in Fig. 5, Fig. 5 is the structural representation of a kind of heterojunction solar battery second embodiment that the application provides.
The heterojunction solar battery that this second embodiment provides, comprising: substrate 300, the first intrinsic resilient coating 310, second intrinsic resilient coating 320, doped layer (first doped layer 330 and the second doped layer 340), transparency conducting layer 350.
The difference of this second embodiment and the first embodiment is: described first intrinsic resilient coating 310 is positioned at the both sides of described substrate 300.According to user demand and environmental aspect, transparency conducting layer 350 is set respectively in the both sides of described doped layer, forms the double-side photic structure of heterojunction solar battery; Or in the side of substrate 300 with doped layer, transparency conducting layer 350 is set, transparent conductive oxide/metal composite layer 360 is set at opposite side, and then form the one side Colony structure of heterojunction solar battery.
Be understandable that, when described heterojunction solar battery has one side Colony structure, first intrinsic resilient coating 310 can be set at substrate 300 sensitive side, in the both sides of the substrate 300 with the first intrinsic resilient coating 310, the second intrinsic resilient coating 320 is set respectively, in the both sides of the substrate 300 with described second intrinsic resilient coating 320, doped layer is set respectively, in the side of substrate 300 with doped layer, and this side is be positioned at the side with described first intrinsic resilient coating 310 to arrange transparency conducting layer 350, and then form one side Colony structure.
When described heterojunction solar battery has double-side photic structure, first intrinsic resilient coating 310 can be set respectively in the both sides of substrate 300, or also only the first intrinsic resilient coating 310 can be set in the side of substrate 300, in the both sides of the substrate 300 with the first intrinsic resilient coating 310, the second intrinsic resilient coating 320 is set respectively, in the both sides of the substrate 300 with the second intrinsic resilient coating 320, doped layer is set respectively, transparency conducting layer 350 is set respectively in the both sides of the substrate 300 with doped layer, and then forms double-side photic structure.
These are only in one side Colony structure and double-side photic structure, about the facilities of the first intrinsic resilient coating 310, in fact, the first intrinsic resilient coating 310 can arrange it as required and be positioned at position on substrate 300, is not limited to foregoing.
It should be noted that, as shown in Figure 5, be described with double-side photic structure in the present embodiment, but be not limited to shown in Fig. 5.
A kind of manufacture method of heterojunction solar battery provided the application above and the structure of heterojunction solar battery are described in detail, according to foregoing, the manufacture method of the heterojunction solar battery that the application provides and the operation principle of heterojunction solar battery are described, specific as follows:
Heterojunction is the contact transition region that a kind of semiconductor material growing is formed on another kind of semi-conducting material.The basis of heterojunction solar battery power conversion is the photovoltaic effect of heterojunction, and so-called photovoltaic effect is exactly the effect producing electromotive force after semi-conducting material absorbs luminous energy on p-n junction.Because electronics in N-type region is many, hole is few, and in p type island region, hole polyelectron is few, and electronics and hole diffuse to form space charge region and p-n junction along with concentration gradient, and forms an internal electric field in space charge region.When radiation of visible light is to when having N-type first doped layer 330 and P type the second doped layer 340, the charge carrier generated near semiconductor internal junction is not owing to being arrived space charge region by compound, under the attraction being subject to this internal electric field, electronics is made to flow into n district, hole flows into p district, result is that n district stores superfluous electronics, and there is superfluous hole in p district.Electronics and hole form the photoproduction electric field contrary with potential barrier direction near p-n/n-p ties, that is, photoproduction electric field is contrary with internal electric field direction, when connection external circuit, get final product output current.
The manufacture method of the heterojunction solar battery that the application provides and heterojunction solar battery, using substrate 300 as absorbed layer, its effect is: one, form p-n junction, produces built-in battery; Two, produce at charge carrier; Three, the first intrinsic resilient coating 310 and on the second doped layer 340 and/or the second intrinsic resilient coating 320 are formed carries on the back electric field.First intrinsic resilient coating 310 1 aspect is used for passivation substrate 300, prevents the second intrinsic resilient coating 320 at substrate 300 Epitaxial growth on the other hand, thus improves the light conversion efficiency of solar cell.Second doped layer 340 is N-type as back of the body electric field, forms n-n+ structure with the substrate 300 of N-type, forms the internal electric field that n+ district points to n district, reduces the compound of charge carrier.
Be understandable that, for enabling more sunlights enter into substrate 300 as absorbed layer, the optical band gap of transparency conducting layer 350, first intrinsic resilient coating 310, second intrinsic resilient coating 320 should be greater than the optical band gap of substrate 300.That is, optical band gap should meet more visible ray is entered in substrate 300.
The manufacture method of the heterojunction solar battery that the application provides and heterojunction solar battery, double-deck intrinsic resilient coating (first intrinsic resilient coating 310 and the second intrinsic resilient coating 320) is formed in the one or both sides of substrate 300, on the one hand: the problem that intrinsic layer causes conversion efficiency to decline by thickness effect can be improved: on the other hand: the second intrinsic resilient coating 320 can be prevented at substrate 300 Epitaxial growth or mixed growth, cause the problem that interface quality is lower.
Therefore, the manufacture method of the heterojunction solar battery that the application provides and heterojunction solar battery, effectively can improve the photoelectric conversion efficiency of heterojunction solar battery.
Although the application with preferred embodiment openly as above; but it is not for limiting the application; any those skilled in the art are not departing from the spirit and scope of the application; can make possible variation and amendment, the scope that therefore protection range of the application should define with the application's claim is as the criterion.
Claims (12)
1. a manufacture method for heterojunction solar battery, is characterized in that, comprising:
Substrate is provided;
The first intrinsic resilient coating is formed in described substrate one or both sides;
The second intrinsic resilient coating is formed in the both sides of the substrate with described first intrinsic resilient coating;
Form doped layer in the both sides of the substrate with described second intrinsic resilient coating, be called the first doped layer and the second doped layer;
Transparency conducting layer is formed respectively in the both sides of the substrate with described doped layer; Or forming transparency conducting layer in the side of the substrate with described doped layer, opposite side forms transparent conductive oxide/metal composite layer.
2. the manufacture method of heterojunction solar battery according to claim 1, it is characterized in that: described first intrinsic resilient coating and/or the second intrinsic resilient coating are set to single or multiple lift, and adopt chemical vapour deposition technique, heated filament chemical vapor deposition or thermal oxidation method to deposit formation.
3. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that: described first intrinsic resilient coating is a-SiOx:H intrinsic layer, and sedimentary condition is: the reacting gas selected is SiH
4and CO
2; Deposition temperature range is more than or equal to 200 DEG C, is less than or equal to 230 DEG C; Deposition pressure scope, for being more than or equal to 0.2mbar, is less than or equal to 0.8mbar; SiH
4range of flow, for being more than or equal to 200sccm, is less than or equal to 800sccm; CO
2range of flow, for being more than or equal to 20sccm, is less than or equal to 50sccm; 40MHz very high frequency(VHF) power density scope is for being more than or equal to 0.012W/cm
2, be less than or equal to 0.025W/cm
2.
4. the manufacture method of heterojunction solar battery according to claim 3, is characterized in that: the thickness range of described first intrinsic resilient coating, for being more than or equal to 1nm, is less than or equal to 25nm.
5. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that: described second intrinsic resilient coating is a-Si:H intrinsic layer, and sedimentary condition is: reacting gas is SiH
4, deposition temperature range, for being more than or equal to 220 DEG C, is less than or equal to 230 DEG C; Deposition pressure scope, for being more than or equal to 0.5mbar, is less than or equal to 0.7mbar; SiH
4range of flow, for being more than or equal to 400sccm, is less than or equal to 800sccm; 40MHz very high frequency(VHF) power density scope is for being more than or equal to 0.012W/cm
2, be less than or equal to 0.025W/cm
2.
6. the manufacture method of heterojunction solar battery according to claim 5, is characterized in that: the thickness range of described second intrinsic resilient coating, for being more than or equal to 1nm, is less than or equal to 25nm.
7. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that: described first doped layer is P type doped layer, and the second doped layer is N-type doped layer; Or first doped layer be N-type doped layer, the second doped layer is P type doped layer.
8. the manufacture method of heterojunction solar battery according to claim 1, it is characterized in that: described first doped layer is the amorphous silicon layer of doping trimethyl borine, form P type doped layer, described second doped layer is the amorphous silicon layer of doping phosphine, forms N-type doped layer.
9. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that: be tin indium oxide at the deposition materials of described transparency conducting layer; The deposition materials of described transparent conductive oxide/metal composite layer is tin indium oxide/silver.
10. a heterojunction solar battery, is characterized in that, comprising:
Substrate;
First intrinsic resilient coating is set in the one or both sides of described substrate;
The second intrinsic resilient coating is formed in the both sides of the substrate with described first intrinsic resilient coating;
In the both sides of the substrate with described second intrinsic resilient coating, doped layer is set;
In the both sides of the substrate with described doped layer, transparency conducting layer is set respectively; Or transparency conducting layer is set in the side of the substrate with described doped layer, opposite side forms transparent conductive oxide/metal composite layer.
11. heterojunction solar batteries according to claim 10, is characterized in that: described first intrinsic resilient coating and/or the second intrinsic resilient coating are set to single or multiple lift structure.
12. heterojunction solar batteries according to claim 10, is characterized in that: described first doped layer is P type doped layer, and the second doped layer is N-type doped layer; Or first doped layer be N-type doped layer, the second doped layer is P type doped layer.
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