CN106449850A - High efficiency silicon-based heterojunction double-sided battery and its preparation method - Google Patents
High efficiency silicon-based heterojunction double-sided battery and its preparation method Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 109
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 109
- 239000010703 silicon Substances 0.000 title claims abstract description 109
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 214
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims description 23
- 239000011248 coating agent Substances 0.000 claims description 20
- 238000000576 coating method Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 13
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 10
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000004044 response Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000009738 saturating Methods 0.000 claims 2
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract description 8
- 230000004888 barrier function Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 60
- 239000007789 gas Substances 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000009466 transformation Effects 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
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- 230000008033 biological extinction Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 235000008216 herbs Nutrition 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 210000002268 wool Anatomy 0.000 description 1
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Y02E10/50—Photovoltaic [PV] energy
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Abstract
The invention discloses a high efficiency silicon-based heterojunction double-sided battery and its preparation method. The high efficiency silicon-based heterojunction double-sided battery comprises an N type silicon chip. On the front side of the N type silicon chip, a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a P type doped amorphous silicon layer, a transparent conductive film layer and a metal gate wire electrode are arranged in succession. The electron band gap of the second intrinsic amorphous silicon layer is greater than that of the first intrinsic amorphous silicon layer. On the back side of the N type silicon chip, a third intrinsic amorphous silicon layer, an N type doped amorphous silicon layer, a transparent conductive film layer and a metal gate wire electrode are arranged in succession. According to the invention, the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are prepared in different chambers respectively, and the preparation temperature of the first intrinsic amorphous silicon layer is lower than that of the second intrinsic amorphous silicon layer so that the second intrinsic amorphous silicon layer has a relatively wider electron band gap which corresponds to the band gap of a crystalline silicon and therefore, can be used as a barrier layer to block the diffusion of electrons into the emitter using the difference in band width; therefore, the combination of electrons with empty cavities can be reduced, improving the electrical performance of the battery.
Description
Technical field
The present invention relates to area of solar cell, more particularly, to a kind of efficient silicon based hetero-junction double-side cell and its
Preparation method.
Background technology
Thin-film solar cells are to deposit a kind of solaode that very thin photoelectric material is formed on substrate.
Still can generate electricity under thin-film solar cells low light condition, its production process energy consumption is low, possess be greatly lowered former
The potentiality of material Manufacturing cost, therefore, market just gradually increases to the demand of thin-film solar cells, and thin
Film solar cell technology even more becomes study hotspot in recent years.Wherein improve photoelectric transformation efficiency, reduce
Cost is the ultimate aim of solar energy industry.
Cost recently as silicon materials reduces, and makes silica-based solar cell more attractive.In order to improve
The conversion efficiency of silica-based solar cell：Two of which technology has been widely studied and has been applied to large-scale production.
One is to remove front grid and busbar, and integrated emitter and collector to the back side is integrated, and the referred to as interdigital back of the body connects
Touched electrode (IBC)；Another is to increase open-circuit voltage based on heteroj unction technologies, is primarily due to thin film non-
The electronic band gap of crystal silicon is higher than crystalline silicon.Thin film silicon contains hydrogen, typically by the side of chemical vapor deposition
Method deposits to the surface of crystal silicon chip, and its thickness is less than 10nm, for being passivated the dangling bonds of silicon face.Heterogeneous
The advantage of knot technology is the process is simple forming PN junction, the positive and negative symmetrical configuration of outer viewing, and therefore tow sides are equal
Can extinction, by optimize cell piece placed angle, reverse side also can absorb environment in scattered light be used for increasing
Short circuit current is so that cell piece output can increase by 10～20%.
Silicon/crystalline silicon heterojunction solar battery generally adopts N-type crystalline silicon as substrate, is primarily due to N-type brilliant
Body silicon is impure few, and universal minority carrier life time is high, and it is with P-type non-crystalline silicon film layer because contacting in the PN junction being formed
Built-in field is high, so the height being easier to obtain cell piece opens pressure.Because built-in field is high, it is also easier to point
The carrier producing in PN junction and in crystalline silicon is electronics and hole, but the diffusion due to electronics,
Electronics also can move to emitter stage, thus causing electronics compound in emitter region with hole, decreases battery
The short circuit current of piece, the photoelectric transformation efficiency reducing cell piece is output.
Content of the invention
In order to solve the problems of the prior art, it is an object of the invention to provide a kind of efficient silicon based hetero-junction is double
Face battery and preparation method thereof, it can be very good to prevent the electrons spread in carrier to emitter region, subtracts
Few electronics is compound with hole, thus increased the short circuit current of cell piece.
For achieving the above object, the present invention employs the following technical solutions：
A kind of efficient silicon based hetero-junction double-side cell, including：N-type silicon chip；Front in described N-type silicon chip
Sequentially it is provided with the first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer, p-type doped amorphous silicon layer, transparent lead
Electrolemma layer, metal grid lines electrode；The electronic band gap of described second intrinsic amorphous silicon layer is more than the first intrinsic amorphous
Silicon layer；The reverse side of described N-type silicon chip be sequentially provided with the 3rd intrinsic amorphous silicon layer, n-type doping amorphous silicon layer,
Transparent conductive film layer, metal grid lines electrode.
Preferably, the thickness of described second intrinsic amorphous silicon film layer is less than 1nm, the first intrinsic amorphous silicon film layer
It is respectively 5-10nm with the thickness of the 3rd intrinsic amorphous silicon film layer, described p-type doped amorphous silicon layer and N-type are mixed
The thickness of miscellaneous amorphous silicon layer is respectively 5-10nm, and the thickness being located at the nesa coating in N-type silicon chip front is
70-110nm, the thickness being located at the nesa coating of N-type silicon chip reverse side is 25-110nm.
Present invention also offers a kind of preparation method of efficient silicon based hetero-junction double-side cell, comprise the following steps：
One N-type silicon chip is provided；Under the first temperature conditionss, chemistry is passed through on the tow sides of N-type silicon chip respectively
Vapour deposition process, deposition the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon film layer；Intrinsic non-the 3rd
Deposited n-type doped amorphous silicon layer on crystal silicon layer；Under the conditions of second temperature, in the first intrinsic amorphous silicon film layer
Upper deposition the second intrinsic amorphous silicon film layer and p-type doped amorphous silicon layer, the electricity of described second intrinsic amorphous silicon layer
Subband gap is more than the first intrinsic amorphous silicon layer；Respectively in p-type doped amorphous silicon layer and n-type doping amorphous silicon layer
Above pass through PVD magnetron sputtering deposition nesa coating；On the double-edged nesa coating of N-type silicon chip
Form metal grid lines electrode.
Preferably, described on the tow sides of N-type silicon chip respectively pass through chemical vapor deposition first
Intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon film layer are specially：Under the first temperature conditionss, by N-type silicon
In piece placing response chamber, toward in reaction chamber, it is passed through SiH4And H2Mixed gas, by chemical vapour deposition technique
Formation the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon are sequentially depositing on the tow sides of N-type silicon chip
Film layer.
Preferably, described in the 3rd intrinsic amorphous silicon layer deposited n-type doped amorphous silicon layer be specially：By shape
The first intrinsic amorphous silicon film layer and the N-type silicon chip of the 3rd intrinsic amorphous silicon film layer is become to put into the first doping intracavity,
It is passed through SiH toward in the first doping chamber4、H2And the gas containing dopant, thus in the 3rd intrinsic amorphous silicon layer
Upper deposited n-type doped amorphous silicon layer.
Preferably, described deposit the second intrinsic amorphous silicon film layer in the first intrinsic amorphous silicon film layer and p-type is mixed
Miscellaneous amorphous silicon layer is specially：Under the conditions of second temperature, N-type will be formed on the 3rd intrinsic amorphous silicon layer and mix
The N-type silicon chip of miscellaneous amorphous silicon layer puts into the second doping intracavity, is first passed through SiH in the second doping intracavity4And H2's
Mixed gas, deposit second by the method for chemical vapor deposition intrinsic non-in the first intrinsic amorphous silicon film layer
After crystal silicon film layer；Continue to be passed through SiH4And H2Mixed gas, and the synchronous gas being passed through containing dopant,
P-type doped amorphous silicon layer is formed on the second intrinsic amorphous silicon film layer.
Preferably, described dopant is P or B.
Preferably, described first temperature is 150-250 DEG C, and described first temperature is higher at least than second temperature
20℃.
The present invention also provides the preparation method of another kind of efficiently silicon based hetero-junction double-side cell, comprises the following steps：
One N-type silicon chip is provided；Under the first temperature conditionss, chemical vapor deposition is passed through on the reverse side of N-type silicon chip
Method deposits the 3rd intrinsic amorphous silicon film layer respectively；Deposited n-type doped amorphous silicon in the 3rd intrinsic amorphous silicon layer
Layer；The front of N-type silicon chip deposits the first intrinsic amorphous silicon film respectively by the method for chemical vapor deposition
Layer；Under the conditions of second temperature, the first intrinsic amorphous silicon film layer deposits the second intrinsic amorphous silicon film layer and
P-type doped amorphous silicon layer；The electronic band gap of described second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；
Lead by PVD magnetron sputtering deposition is transparent on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively
Electrolemma；Metal grid lines electrode is formed on the double-edged nesa coating of N-type silicon chip simultaneously.
The present invention also provides the preparation method of another kind of efficiently silicon based hetero-junction double-side cell, comprises the following steps：
One N-type silicon chip is provided；Under the first temperature conditionss, chemical vapor deposition is passed through on the front of N-type silicon chip
Method deposits the first intrinsic amorphous silicon film layer respectively；Under the conditions of second temperature, in the first intrinsic amorphous silicon film layer
Upper deposition the second intrinsic amorphous silicon film layer and p-type doped amorphous silicon layer；The electricity of described second intrinsic amorphous silicon layer
Subband gap is more than the first intrinsic amorphous silicon layer；By the method for chemical vapor deposition on the reverse side of N-type silicon chip
Deposit the 3rd intrinsic amorphous silicon film layer respectively；Deposited n-type doped amorphous silicon layer in the 3rd intrinsic amorphous silicon layer；
Respectively on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer by way of PVD magnetron sputtering deposition
Form nesa coating；Metal grid lines electricity is formed on the double-edged nesa coating of N-type silicon chip simultaneously
Pole.
The present invention adopts above technical scheme, is provided with the first intrinsic amorphous by the one side in described N-type silicon chip
Silicon layer, the second intrinsic amorphous silicon layer, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer exist respectively
Different within the chamber preparations completes, and the preparation temperature of the first intrinsic amorphous silicon layer is than the second intrinsic amorphous silicon layer
Preparation temperature is high, so that the second intrinsic amorphous silicon layer has larger electronic band gap, therefore can be used to
Stopping that electrons spread arrives emitter stage as barrier layer, decreasing the compound, thus improve of electronics and hole
The electric property of cell piece, the photoelectric transformation efficiency that increased cell piece is output.
Brief description
Fig. 1 is the structural representation of the present invention efficient silicon based hetero-junction double-side cell；
Fig. 2 is the schematic flow sheet of the preparation method embodiment one of the present invention；
Fig. 3 is the schematic flow sheet of the preparation method embodiment two of the present invention；
Fig. 4 is the schematic flow sheet of the preparation method embodiment three of the present invention.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with accompanying drawing and reality
Apply example, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only
Only in order to explain the present invention, it is not intended to limit the present invention.
As shown in figure 1, the invention discloses a kind of efficient silicon based hetero-junction double-side cell, it includes：
N-type silicon chip 1；
Sequentially it is provided with the first intrinsic amorphous silicon layer 2, the second intrinsic amorphous silicon in the front of described N-type silicon chip 1
Layer 3, p-type doped amorphous silicon layer 4, transparent conductive film layer 5, metal grid lines electrode 6；
The reverse side of described N-type silicon chip be sequentially provided with the 3rd intrinsic amorphous silicon layer 7, n-type doping amorphous silicon layer 8,
Transparent conductive film layer 9, metal grid lines electrode 10.
Wherein, the electronic band gap of described second intrinsic amorphous silicon layer 3 is more than the first intrinsic amorphous silicon layer 2.Institute
The thickness stating the second intrinsic amorphous silicon film layer is less than 1nm, the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous
The thickness of silicon film is respectively 5-10nm, the thickness of described n-type doping amorphous silicon layer and p-type doped amorphous silicon layer
Degree is respectively 5-10nm, and the thickness being located at the nesa coating in N-type silicon chip front is 70-110nm, is located at N
The thickness of the nesa coating of type silicon chip reverse side is 25-110nm.
Heretofore described N-type silicon chip can be monocrystalline silicon piece or polysilicon chip, and the battery of the present invention exists
Under the irradiation of sunlight, substantial amounts of electronics and sky in its PN junction and in the N-type crystalline silicon of substrate, can be produced
Cave, electronics and hole that the built-in field in usual PN junction can separately produce.For N-type crystalline silicon, its
Few son is hole, and therefore hole is moved to sensitive surface, and how sub- electrons move in the opposite direction and produce
Electric current.But the effect due to electrons spread, part electronics also can move to sensitive surface, thus increased electricity
Son and hole, in the recombination probability of PN junction area, are caused the loss of electronics, are reduced the short circuit current of cell piece.
The present invention passes through to increase by the second intrinsic amorphous silicon layer 3 in the first intrinsic amorphous silicon layer 2, and the second intrinsic amorphous
The electronic band gap of silicon layer 3 is more than the first intrinsic amorphous silicon layer 2, therefore can be used to stop as barrier layer
Electrons spread to PN junction area, i.e. emitter stage, decreases the compound of electronics and hole, thus improve cell piece
Electric property, the photoelectric transformation efficiency that increased cell piece is output.
Embodiment one：
As shown in Fig. 2 the invention discloses a kind of preparation method of efficient silicon based hetero-junction double-side cell, its
Comprise the following steps：
S101:One N-type silicon chip is provided；
S102:Under the first temperature conditionss, chemical vapor deposition is passed through on the tow sides of N-type silicon chip respectively
Method deposits the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon film layer respectively；
S103:Deposited n-type doped amorphous silicon layer in the 3rd intrinsic amorphous silicon layer；
S104:Under the conditions of second temperature, the first intrinsic amorphous silicon film layer deposits the second intrinsic amorphous silicon film
Layer and p-type doped amorphous silicon layer；
S105：PVD (physics gas is passed through respectively on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer
Phase sedimentation) magnetron sputtering deposition mode deposition of transparent conductive film；
S106：Plated metal gate line electrode simultaneously on the nesa coating on two sides.
Specific step can be as follows：
Step 1：There is provided a N-type silicon chip, to N-type silicon chip cleaning and making herbs into wool, then in 150-220 DEG C of temperature
Under the conditions of, by N-type silicon chip placing response chamber, toward in reaction chamber, it is passed through SiH4And H2Mixed gas, its
Middle H2Content be 5 to 20%, shape is deposited on the two sides of N-type silicon chip by the method for chemical vapor deposition
Become the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon film layer.
Step 2：The N-type silicon chip forming the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon film layer is put
Enter the first doping intracavity, toward in the first doping chamber, be passed through SiH4、H2And the gas containing dopant P, thus
Deposited n-type doped amorphous silicon layer in the 3rd intrinsic amorphous silicon layer；
Step 3：Under the temperature conditionss than 150-220 DEG C at least low 20 DEG C, will be in the 3rd intrinsic amorphous silicon
The N-type silicon chip forming n-type doping amorphous silicon layer on layer puts into the second doping intracavity, first in the second doping intracavity
It is passed through SiH4And H2Mixed gas, deposited in the first intrinsic amorphous silicon film layer by chemical vapour deposition technique
Second intrinsic amorphous silicon film layer；Continue to be passed through SiH4And H2Gas, and the synchronous gas being passed through containing dopant B
Body, forms p-type doped amorphous silicon layer in the second intrinsic amorphous silicon film layer；
Step 4：The p-type doped amorphous silicon layer of sensitive surface and the n-type doping amorphous silicon layer of shady face divide
Transparent conductive film layer and metal laminated, then again metal laminated is not generated by the method for PVD magnetron sputtering
On carry out dry film mask, exposure, development after formed metal grid lines pattern；Pass through electric plating method afterwards to leakage
The metal grid lines pattern going out thickeies.
Step 5：Get rid of dry film, and carry out selective corrosion to metal laminated, metal laminated be not thickened
Region can spill transparent conductive film layer, thus surface formed metal grid lines pattern, so far complete battery system
Standby.
Embodiment two：
As shown in figure 3, from unlike embodiment one, in the present embodiment, it mainly first prepares N-type silicon chip
Wherein the 3rd intrinsic amorphous silicon film layer of one side and n-type doping amorphous silicon layer, then prepares other one side again
First intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer and p-type doped amorphous silicon layer, finally prepare transparent leading
Electrolemma layer and metal grid lines electrode, it specifically includes following steps：
S201：One N-type silicon chip is provided；
S202：Under the first temperature conditionss, by the method for chemical vapor deposition on the reverse side of N-type silicon chip
Deposit the 3rd intrinsic amorphous silicon film layer respectively；
S203：Deposited n-type doped amorphous silicon layer in the 3rd intrinsic amorphous silicon layer；
S204：The front of N-type silicon chip deposits the first intrinsic amorphous silicon respectively by chemical vapour deposition technique
Film layer；
S205：Under the conditions of second temperature, the first intrinsic amorphous silicon film layer deposits the second intrinsic amorphous silicon
Film layer and p-type doped amorphous silicon layer；
S206：PVD magnetron sputtering is passed through respectively on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer
The mode of deposition forms nesa coating；
S207：Plated metal gate line electrode simultaneously on the double-edged nesa coating of N-type silicon chip.
Described first temperature is higher at least 20 DEG C than second temperature.
Embodiment three：
As shown in figure 4, from unlike embodiment one, in the present embodiment, it mainly first prepares N-type silicon chip
Wherein the first intrinsic amorphous silicon layer of one side, the second intrinsic amorphous silicon layer and p-type doped amorphous silicon layer, then
Prepare the 3rd intrinsic amorphous silicon film layer and the n-type doping amorphous silicon layer of another side again, finally prepare electrically conducting transparent
Film layer and metal grid lines electrode, it specifically includes following steps：
S301：One N-type silicon chip is provided；
S302：Under the first temperature conditionss, by the method for chemical vapor deposition on the front of N-type silicon chip
Deposit the first intrinsic amorphous silicon film layer respectively；
S303：Under the conditions of second temperature, the first intrinsic amorphous silicon film layer deposits the second intrinsic amorphous silicon
Film layer and p-type doped amorphous silicon layer；
S304：The reverse side of N-type silicon chip deposits the 3rd intrinsic amorphous silicon respectively by chemical vapour deposition technique
Film layer；
S305：Deposited n-type doped amorphous silicon layer in the 3rd intrinsic amorphous silicon layer；
S306：PVD magnetron sputtering is passed through respectively on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer
The mode of deposition forms nesa coating；
S307：Plated metal gate line electrode simultaneously on the double-edged nesa coating of N-type silicon chip.
Described first temperature is higher at least 20 DEG C than second temperature.
The present invention N-type substrate tow sides be designed with metal grid lines electrode so that cell piece just,
Anti- two sides all can extinction, increase the output of cell piece, be provided with the by the one side in described N-type silicon chip
One intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous
Silicon layer completes in different within the chamber preparations respectively, and the preparation temperature of the first intrinsic amorphous silicon layer is more intrinsic than the second
The preparation temperature of amorphous silicon layer is high, so that the second intrinsic amorphous silicon layer has larger electronic band gap, because
This can be used to stop that electrons spread, to PN junction area, i.e. emitter stage, decreases the stream of electronics as barrier layer
Lose, improve photoelectric transformation efficiency.Wherein, " silicon based hetero-junction double-side cell chip technology " disclosed by the invention,
English is " Silicon-based Heterojunction Double-sided Solar Cell
Technology ", is abbreviated as " HDT ".
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all at this
Any modification, equivalent and improvement made within bright spirit and principle etc., should be included in the present invention
Protection domain within.
Claims (10)
1. a kind of efficient silicon based hetero-junction double-side cell it is characterised in that：Including：
N-type silicon chip；
Sequentially it is provided with the first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer, P in the front of described N-type silicon chip
Type doped amorphous silicon layer, transparent conductive film layer, metal grid lines electrode；The electricity of described second intrinsic amorphous silicon layer
Subband gap is more than the first intrinsic amorphous silicon layer；
The reverse side of described N-type silicon chip be sequentially provided with the 3rd intrinsic amorphous silicon layer, n-type doping amorphous silicon layer,
Transparent conductive film layer, metal grid lines electrode.
2. efficient silicon based hetero-junction double-side cell according to claim 1 it is characterised in that：Described
The thickness of two intrinsic amorphous silicon film layers is less than 1nm, the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon film
The thickness of layer is respectively 5-10nm, and the thickness of described p-type doped amorphous silicon layer and n-type doping amorphous silicon layer divides
Not Wei 5-10nm, be located at N-type silicon chip front nesa coating thickness be 70-110nm, be located at N-type silicon
The thickness of the nesa coating of piece reverse side is 25-110nm.
3. a kind of preparation method of efficient silicon based hetero-junction double-side cell is it is characterised in that comprise the following steps：
One N-type silicon chip is provided；
Under the first temperature conditionss, the tow sides of N-type silicon chip pass through chemical vapour deposition technique respectively,
Deposit the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon film layer；
Deposited n-type doped amorphous silicon layer in the 3rd intrinsic amorphous silicon layer；
Under the conditions of second temperature, the first intrinsic amorphous silicon film layer deposits the second intrinsic amorphous silicon film layer and
P-type doped amorphous silicon layer, the electronic band gap of described second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；
PVD magnetron sputtering deposition is passed through on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer saturating respectively
Bright conducting film；
Metal grid lines electrode is formed on the double-edged nesa coating of N-type silicon chip.
4. according to claim 3 efficiently silicon based hetero-junction double-side cell preparation method it is characterised in that：
Described on the tow sides of N-type silicon chip respectively pass through chemical vapor deposition first intrinsic amorphous silicon film
Layer and the 3rd intrinsic amorphous silicon film layer are specially：Under the first temperature conditionss, by N-type silicon chip placing response chamber
In, it is passed through SiH toward in reaction chamber4And H2Mixed gas, by chemical vapour deposition technique in N-type silicon chip
Formation the first intrinsic amorphous silicon film layer and the 3rd intrinsic amorphous silicon film layer are sequentially depositing on tow sides.
5. according to claim 3 efficiently silicon based hetero-junction double-side cell preparation method it is characterised in that：
Described in the 3rd intrinsic amorphous silicon layer deposited n-type doped amorphous silicon layer be specially：First will be formed intrinsic non-
The N-type silicon chip of crystal silicon film layer and the 3rd intrinsic amorphous silicon film layer puts into the first doping intracavity, toward the first doping chamber
In be passed through SiH4、H2And the gas containing dopant, thus in the 3rd intrinsic amorphous silicon layer, deposited n-type is mixed
Miscellaneous amorphous silicon layer.
6. according to claim 3 efficiently silicon heterogenous double-side cell preparation method it is characterised in that：
Described deposit in the first intrinsic amorphous silicon film layer the second intrinsic amorphous silicon film layer and p-type doped amorphous silicon layer tool
Body is：Under the conditions of second temperature, n-type doping amorphous silicon layer will be formed on the 3rd intrinsic amorphous silicon layer
N-type silicon chip puts into the second doping intracavity, is first passed through SiH in the second doping intracavity4And H2Mixed gas, lead to
Cross chemical vapor deposition method deposit the second intrinsic amorphous silicon film layer in the first intrinsic amorphous silicon film layer after；
Continue to be passed through SiH4And H2Mixed gas, and the synchronous gas being passed through containing dopant, intrinsic non-second
P-type doped amorphous silicon layer is formed on crystal silicon film layer.
7. according to claim 5 or 6 efficient silicon based hetero-junction double-side cell preparation method, its feature
It is：Described dopant is P or B.
8. according to claim 3 efficiently silicon based hetero-junction double-side cell preparation method it is characterised in that：
Described first temperature is 150-250 DEG C, and described first temperature is higher at least 20 DEG C than second temperature.
9. a kind of preparation method of efficient silicon based hetero-junction double-side cell is it is characterised in that comprise the following steps：
One N-type silicon chip is provided；
Under the first temperature conditionss, the reverse side of N-type silicon chip deposits respectively by chemical vapour deposition technique
Three intrinsic amorphous silicon film layers；
Deposited n-type doped amorphous silicon layer in the 3rd intrinsic amorphous silicon layer；
The front of N-type silicon chip deposits the first intrinsic amorphous silicon film respectively by the method for chemical vapor deposition
Layer；
Under the conditions of second temperature, the first intrinsic amorphous silicon film layer deposits the second intrinsic amorphous silicon film layer and
P-type doped amorphous silicon layer；The electronic band gap of described second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；
PVD magnetron sputtering deposition is passed through on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer saturating respectively
Bright conducting film；
Metal grid lines electrode is formed on the double-edged nesa coating of N-type silicon chip simultaneously.
10. a kind of preparation method of efficient silicon based hetero-junction double-side cell is it is characterised in that include following walking
Suddenly：
One N-type silicon chip is provided；
Under the first temperature conditionss, the front of N-type silicon chip deposits respectively by chemical vapour deposition technique
One intrinsic amorphous silicon film layer；
Under the conditions of second temperature, the first intrinsic amorphous silicon film layer deposits the second intrinsic amorphous silicon film layer and
P-type doped amorphous silicon layer；The electronic band gap of described second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；
The reverse side of N-type silicon chip deposits the 3rd intrinsic amorphous silicon film respectively by the method for chemical vapor deposition
Layer；
Deposited n-type doped amorphous silicon layer in the 3rd intrinsic amorphous silicon layer；
PVD magnetron sputtering deposition is passed through respectively on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer
Mode forms nesa coating；
Metal grid lines electrode is formed on the double-edged nesa coating of N-type silicon chip simultaneously.
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