CN112466989A - Preparation process of heterojunction solar cell - Google Patents
Preparation process of heterojunction solar cell Download PDFInfo
- Publication number
- CN112466989A CN112466989A CN202011262587.5A CN202011262587A CN112466989A CN 112466989 A CN112466989 A CN 112466989A CN 202011262587 A CN202011262587 A CN 202011262587A CN 112466989 A CN112466989 A CN 112466989A
- Authority
- CN
- China
- Prior art keywords
- silicon wafer
- film layer
- amorphous silicon
- back surface
- front surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 41
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 32
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000011574 phosphorus Substances 0.000 claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000005247 gettering Methods 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 239000002253 acid Substances 0.000 claims abstract description 5
- 239000003513 alkali Substances 0.000 claims abstract description 5
- 238000004140 cleaning Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000012360 testing method Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 32
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000000243 solution Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 5
- 238000004050 hot filament vapor deposition Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 25
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 33
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 238000010248 power generation Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- YWWDBCBWQNCYNR-UHFFFAOYSA-N trimethylphosphine Chemical compound CP(C)C YWWDBCBWQNCYNR-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910021654 trace metal Inorganic materials 0.000 description 1
- RXJKFRMDXUJTEX-UHFFFAOYSA-N triethylphosphine Chemical compound CCP(CC)CC RXJKFRMDXUJTEX-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1876—Particular processes or apparatus for batch treatment of the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Abstract
The invention discloses a preparation process of a heterojunction solar cell, which comprises the following steps: carrying out phosphorus gettering treatment on the silicon wafer, depositing a phosphorus diffusion layer on the front surface and the back surface of the silicon wafer, and then removing the phosphorus diffusion layer through acid etching; cleaning the surface of the silicon wafer through an alkali solution to form texturing of the surface of the silicon wafer; depositing an amorphous silicon film layer on the front surface and the back surface of the textured silicon wafer; depositing a conductive thin film layer on the front surface and the back surface of the amorphous silicon thin film layer; covering metal electrodes on the front surface and the back surface of the conductive film layer; solidifying the metal electrode; and (6) testing and sorting. According to the preparation process of the heterojunction solar cell, the influence caused by the quality problem of the silicon wafer in the production process is greatly improved, so that the conversion efficiency of the heterojunction solar cell is further improved.
Description
Technical Field
The invention relates to the technical field of solar cell manufacturing, in particular to a preparation process of a heterojunction solar cell.
Background
With the development of solar cell technology, the development of high-efficiency cells is more and more emphasized. Among them, a silicon-based heterojunction solar cell (HJT cell) passivated with an amorphous silicon intrinsic layer (a-Si: h (i)) is one of the major research directions. As is well known, the silicon-based heterojunction solar cell not only has high conversion efficiency and high open-circuit voltage, but also has the advantages of low temperature coefficient, no Light Induced Degradation (LID), no induced degradation (PID), low preparation process temperature and the like. In addition, the silicon-based heterojunction battery ensures high conversion efficiency, and the thickness of the silicon wafer can be reduced to 100 mu m, so that the consumption of silicon materials is effectively reduced, and the silicon-based heterojunction battery can be used for preparing a bendable battery component.
The average efficiency of the ultra-high efficiency heterojunction battery mass production HJT battery of the applicant reaches 23.8%, the highest efficiency breaks through to 24.73%, and the double-sided rate reaches 93%. Due to the characteristic of double-sided power generation, 10% -30% of extra power generation can be generated on the back of the module in scenes such as grasslands, cement grounds, snowfields and reflective cloth. The power temperature coefficient is as low as-0.27%/DEG C, and compared with a common polycrystalline assembly, the heterojunction assembly of the applicant can recover 34% of power generation loss at the working temperature of 75 ℃.
Based on the advantages of the heterojunction battery, rapid development is achieved in recent years, a plurality of leading enterprises in the industry begin to perform layout, and after the efficiency reaches the level of 23.8%, the current pursuit for the conversion efficiency of the battery cannot be met based on the original process route, so that how to break through the existing process preparation flow to further improve the mass production efficiency of the HJT battery is a challenge facing the HJT battery at present, and the acceleration of the large-area industrialization process is a challenge.
Therefore, how to provide a process for manufacturing a heterojunction solar cell is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the invention provides a preparation process of a heterojunction solar cell, which greatly improves the influence caused by the quality problem of a silicon wafer in the production process, thereby further improving the conversion efficiency of the heterojunction solar cell.
In order to achieve the purpose, the invention adopts the following technical scheme:
a preparation process of a heterojunction solar cell comprises the following steps:
(1) carrying out phosphorus gettering treatment on the silicon wafer, depositing a phosphorus diffusion layer on the front surface and the back surface of the silicon wafer, and then removing the phosphorus diffusion layer through acid etching;
(2) cleaning the surface of the silicon wafer through an alkali solution to form texturing of the surface of the silicon wafer;
(3) depositing an amorphous silicon film layer on the front surface and the back surface of the textured silicon wafer;
(4) depositing a conductive thin film layer on the front surface and the back surface of the amorphous silicon thin film layer;
(5) covering metal electrodes on the front surface and the back surface of the conductive film layer;
(6) solidifying the metal electrode;
(7) and (6) testing and sorting.
Preferably, in the above process for manufacturing a heterojunction solar cell, the silicon wafer in step (1) is a monocrystalline silicon substrate, and the conductivity type is N-type or P-type, and is more preferably N-type.
The beneficial effects of the above technical scheme are: the N-type monocrystalline silicon wafer has higher minority carrier lifetime than the P-type monocrystalline silicon wafer under the same doping concentration, is easier to passivate than the P-type monocrystalline silicon wafer, and has no B-O composite attenuation in the aspect of optics, so the N-type monocrystalline silicon wafer is comprehensively considered and is preferred.
Preferably, in the above preparation process of the heterojunction solar cell, the silicon wafer in the step (1) is a quasi-square monocrystalline silicon wafer with a side length of 156-210mm, the thickness of the silicon wafer is 50-200 μm, and the silicon wafer cost and the yield of the production line are comprehensively considered, and the silicon wafer is preferably 150-180 μm.
The beneficial effects of the above technical scheme are: if the thickness of the silicon wafer is less than 50 μm, the chipping rate increases, and if the thickness is more than 200 μm, the cost is affected.
Preferably, in the above process for manufacturing a heterojunction solar cell, the phosphorus gettering process in step (1) is: passing a phosphorus source through N2And introducing the silicon wafer into a furnace tube in a carrying mode, controlling the deposition temperature at 800 ℃ for 600 plus materials, setting the propulsion temperature at 1000 ℃ for 800 plus materials, and enabling the phosphorus source to react with oxygen and silicon to form simple substance phosphorus which is deposited on the surface layers of the front surface and the back surface of the silicon wafer to obtain a phosphorus diffusion layer.
Preferably, in the above process for manufacturing a heterojunction solar cell, the depth of the phosphorus diffusion layer in step (1) is 0.3-2um, and the sheet resistance is controlled to be 30-100 Ω.
Preferably, in the above process for manufacturing a heterojunction solar cell, the phosphorus source in step (1) is selected from any one of phosphorus oxychloride, trimethylphosphorus and triethylphosphine.
Preferably, in the above process for manufacturing a heterojunction solar cell, the acid in step (1) is HNO in a volume ratio of (8-9) to (1-2)3And a mixed solution of HF.
Preferably, in the above process for manufacturing a heterojunction solar cell, step (2) is: texturing the surface of the silicon wafer by using an alkali solution to form surface texturing, wherein the size of the textured surface is 1-7 mu m; the alkali solution is NaOH or KOH, preferably KOH.
The beneficial effects of the above technical scheme are: although NaOH has lower price, the risk of potential induced attenuation PID is increased, therefore, KOH solution is preferred, the formed crystal face is (111), the light receiving face is of a textured structure and is of a pyramid structure, so that the reflection loss of light on the surface of a silicon wafer is reduced, the size of the textured face is 1-7 mu m, and the consideration of balance of several parameters of the comprehensive electrical property method is preferably 3-5 mu m.
Preferably, in the above process for manufacturing a heterojunction solar cell, the step (3) includes:
A. depositing intrinsic amorphous silicon on the front side and the back side of the textured silicon wafer through plasma chemical vapor deposition or catalytic chemical vapor deposition, wherein the thickness of the intrinsic amorphous silicon layer is 5-20 nm;
B. and depositing doped amorphous silicon on the front surface and the back surface of the intrinsic amorphous silicon layer through plasma chemical vapor deposition or catalytic chemical vapor deposition, wherein the doped amorphous silicon is in an N/P or P/N heterotype symmetrical structure (namely, a P-type doped amorphous silicon film layer or an N-type doped amorphous silicon film layer is adopted on the front surface, and an N-type doped amorphous silicon film layer or a P-type doped amorphous silicon layer is adopted on the back surface), the thickness of the P-type doped amorphous silicon film layer is 5-20nm, and the thickness of the N-type doped amorphous silicon film layer is 5-30 nm.
The beneficial effects of the above technical scheme are: as a passivation layer for the heterojunction cell and combines to form a PN junction.
Preferably, in the above process for manufacturing a heterojunction solar cell, the conductive thin film layer is deposited in step (4) by magnetron sputtering or reactive plasma deposition.
Preferably, in the above fabrication process of a heterojunction solar cell, the conductive thin film layer includes, but is not limited to, ITO, IWO, AZO, and the conductive thin film layer has a thickness of 60-120nm and a sheet resistance of 30-80 Ω.
The beneficial effects of the above technical scheme are: the above definition can exert the functions of light transmission and electric conduction of the TCO transparent conductive film to the maximum extent.
Preferably, in the above preparation process of the heterojunction solar cell, the step (5) of covering the metal electrode is implemented by screen printing, the metal electrode comprises a main grid and an auxiliary grid which are vertically distributed, the number of the main grid lines is 0-20, the width of the grid lines is 0-1.2mm, the number of the auxiliary grid lines is 80-200, and the width of the grid lines is 20-60 μm.
The beneficial effects of the above technical scheme are: the above definition allows for better collection of minority carriers.
Preferably, in the above process for manufacturing a heterojunction solar cell, the metal electrode is a silver electrode.
The beneficial effects of the above technical scheme are: the metallic silver electrode can realize better conductive performance.
Preferably, in the above-mentioned process for manufacturing a heterojunction solar cell, the curing temperature in step (6) does not exceed 200 ℃.
According to the technical scheme, compared with the prior art, the invention discloses a preparation process of a heterojunction solar cell, which has the following advantages:
(1) adding a phosphorus diffusion gettering process, aiming at trace metal elements existing in a silicon wafer, wherein the elements can form minority carriers, namely a recombination center of electrons and holes in the heterojunction battery processing process, so that the quantity of the electrons and the holes reaching two ends of the battery piece and conveyed to the outside is greatly reduced, and the gettering principle is that metal impurities are high in solubility in a phosphorus diffusion layer, silicon self-interstitial atoms are injected, impurity diffusion and formation of a surface area dislocation network are promoted, and capture of the impurity atoms in a surface layer is promoted;
(2) by introducing the combination steps of high temperature and phosphorus gettering, a new heterojunction cell production flow is formed, the quality of silicon wafers of silicon wafer suppliers of various manufacturers is improved to the same level, the stability of the manufacturing process in the production line production process is improved, the discreteness of the efficiency of finished cell products is reduced, and meanwhile, the conversion efficiency of a heterojunction solar cell is improved through gettering treatment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
A. Carrying out phosphorus gettering treatment on an N-type monocrystalline silicon wafer with the thickness of 180 mu m, wherein the deposition temperature is 750 ℃, the propulsion temperature is 900 ℃, the depth of a formed diffusion layer is 0.5 mu m, the sheet resistance is 70 omega, a phosphorus diffusion layer is formed on the front surface and the back surface of the silicon wafer, and then HNO is carried out3And HF removes the diffusion layer;
B. and (3) texturing the silicon wafer on which the surface of the working procedure A is finished by using KOH, wherein the size of the textured surface is 3 microns.
C. Preparing a double-intrinsic amorphous silicon layer and a doped amorphous silicon layer on the front surface and the back surface by plasma chemical vapor deposition, wherein the thickness of the intrinsic amorphous silicon on the front surface and the back surface is 10nm, the thickness of the P-type amorphous silicon on the front surface and the back surface is 15nm, and the thickness of the N-type amorphous silicon on the back surface is 20 nm;
D. and an ITO film is deposited by magnetron sputtering, the thickness of the ITO film on the front surface and the back surface is 100nm, and the sheet resistance is 60 omega.
E. Forming front and back silver metal electrodes by screen printing, wherein the width of a main grid is 0.9mm, the number of the main grids is 9, the width of a front and back silver auxiliary grid line is 40 mu m, and the number of the lines is 100;
F. the curing temperature is 200 ℃;
the electrical performance of the cell was tested, and the average efficiency of mass production of the cell was 24.0%.
Example 2
A. Carrying out phosphorus gettering treatment on an N-type monocrystalline silicon wafer with the thickness of 180 mu m, depositing at 800 ℃, advancing at 900 ℃, forming a diffusion layer with the depth of 0.7 mu m and the sheet resistance of 50 omega, forming a phosphorus diffusion layer on the front surface and the back surface of the silicon wafer, and then passing through HNO3And HF removes the diffusion layer;
B. and (3) texturing the silicon wafer on which the surface of the working procedure A is finished by using KOH, wherein the size of the textured surface is 3 microns.
C. Preparing a double-intrinsic amorphous silicon layer and a doped amorphous silicon layer on the front surface and the back surface by plasma chemical vapor deposition, wherein the thickness of the intrinsic amorphous silicon on the front surface and the back surface is 10nm, the thickness of the P-type amorphous silicon on the front surface and the back surface is 15nm, and the thickness of the N-type amorphous silicon on the back surface is 20 nm;
D. and an ITO film is deposited by magnetron sputtering, the thickness of the ITO film on the front surface and the back surface is 100nm, and the sheet resistance is 60 omega.
E. Forming front and back silver metal electrodes by screen printing, wherein the width of a main grid is 0.9mm, the number of the main grids is 9, the width of a front and back silver auxiliary grid line is 40 mu m, and the number of the lines is 100;
F. the curing temperature is 200 DEG C
G. The electrical performance of the cell was tested and the average efficiency of mass production of the cell was 24.1%.
Comparative example 1
A. Carrying out texturing treatment on an N-type monocrystalline silicon wafer with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;
B. preparing a double-intrinsic amorphous silicon layer and a doped amorphous silicon layer on the front surface and the back surface by plasma chemical vapor deposition, wherein the thickness of the intrinsic amorphous silicon on the front surface and the back surface is 10nm, the thickness of the P-type amorphous silicon on the front surface and the back surface is 15nm, and the thickness of the N-type amorphous silicon on the back surface is 20 nm;
C. the ITO film is deposited by magnetron sputtering, the thickness of the ITO film on the front surface and the back surface is 100nm, and the sheet resistance is 60 omega
D. Forming front and back silver metal electrodes by screen printing, wherein the width of a main grid is 0.9mm, the number of the main grids is 9, the width of a front and back silver auxiliary grid line is 40 mu m, and the number of the lines is 100;
E. the curing temperature was 200 ℃.
F. The electrical property of the cell is tested, and the average efficiency of the mass production of the cell is 23.8%.
As can be seen from examples 1-2 and comparative example 1, the HJT cell prepared by the preparation process of the heterojunction solar cell disclosed by the invention has more excellent electrical property, and the average efficiency of the cell is improved by about 0.2-0.3%.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the scheme disclosed by the embodiment, the scheme corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A preparation process of a heterojunction solar cell is characterized by comprising the following steps:
(1) carrying out phosphorus gettering treatment on the silicon wafer, depositing a phosphorus diffusion layer on the front surface and the back surface of the silicon wafer, and then removing the phosphorus diffusion layer through acid etching;
(2) cleaning the surface of the silicon wafer through an alkali solution to form texturing of the surface of the silicon wafer;
(3) depositing an amorphous silicon film layer on the front surface and the back surface of the textured silicon wafer;
(4) depositing a conductive thin film layer on the front surface and the back surface of the amorphous silicon thin film layer;
(5) covering metal electrodes on the front surface and the back surface of the conductive film layer;
(6) solidifying the metal electrode;
(7) and (6) testing and sorting.
2. The process according to claim 1, wherein the silicon wafer in step (1) is a monocrystalline silicon substrate and the conductivity type is N-type or P-type.
3. The process according to claim 1, wherein the silicon wafer in step (1) is a quasi-square monocrystalline silicon wafer with a side length of 156-210mm, and the thickness of the silicon wafer is 50-200 μm.
4. The process according to claim 1, wherein the phosphorous gettering step (1) is: passing a phosphorus source through N2And introducing the silicon wafer into a furnace tube in a carrying mode, controlling the deposition temperature at 800 ℃ for 600 plus materials, setting the propulsion temperature at 1000 ℃ for 800 plus materials, and enabling the phosphorus source to react with oxygen and silicon to form simple substance phosphorus which is deposited on the surface layers of the front surface and the back surface of the silicon wafer to obtain a phosphorus diffusion layer.
5. The process according to claim 1, wherein the depth of the phosphorus diffusion layer is 0.3-2um, and the sheet resistance is controlled to 30-100 Ω.
6. The process of claim 1, wherein the acid in step (1) is HNO in a volume ratio of (8-9) to (1-2)3And a mixed solution of HF.
7. The process according to claim 1, wherein step (3) comprises:
A. depositing intrinsic amorphous silicon on the front side and the back side of the textured silicon wafer through plasma chemical vapor deposition or catalytic chemical vapor deposition, wherein the thickness of the intrinsic amorphous silicon layer is 5-20 nm;
B. and depositing doped amorphous silicon on the front surface and the back surface of the intrinsic amorphous silicon layer through plasma chemical vapor deposition or catalytic chemical vapor deposition, wherein the doped amorphous silicon is in an N/P or P/N heterotype symmetrical structure, the thickness of a film layer of the P-type doped amorphous silicon is 5-20nm, and the thickness of a film layer of the N-type doped amorphous silicon is 5-30 nm.
8. The process according to claim 1, wherein the conductive thin film layer is deposited in step (4) by magnetron sputtering or reactive plasma deposition; the conductive film layer comprises ITO, IWO and AZO, the thickness of the conductive film layer is 60-120nm, and the sheet resistance is 30-80 omega.
9. The process according to claim 1, wherein the step (5) of covering the metal electrode is realized by screen printing, the metal electrode comprises a main grid and a secondary grid which are vertically distributed, the number of the main grid lines is 0-20, the width of the grid lines is 0-1.2mm, the number of the secondary grid lines is 80-200, and the width of the grid lines is 20-60 μm.
10. The process according to claim 1, wherein the curing temperature in step (6) does not exceed 200 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011262587.5A CN112466989A (en) | 2020-11-12 | 2020-11-12 | Preparation process of heterojunction solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011262587.5A CN112466989A (en) | 2020-11-12 | 2020-11-12 | Preparation process of heterojunction solar cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112466989A true CN112466989A (en) | 2021-03-09 |
Family
ID=74825652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011262587.5A Pending CN112466989A (en) | 2020-11-12 | 2020-11-12 | Preparation process of heterojunction solar cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112466989A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114188443A (en) * | 2021-11-18 | 2022-03-15 | 晋能清洁能源科技股份公司 | Preparation method of thin silicon slice HJT battery capable of reducing fragment rate |
| CN114284395A (en) * | 2021-12-15 | 2022-04-05 | 江苏爱康能源研究院有限公司 | Preparation method of silicon-based heterojunction solar cell with first texturing and then gettering |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820378A (en) * | 2012-08-27 | 2012-12-12 | 晶澳（扬州）太阳能科技有限公司 | Gettering method for prolonging effective service life of crystalline silicon substrate |
| CN103094423A (en) * | 2013-01-31 | 2013-05-08 | 英利集团有限公司 | P-type heterojuction solar battery and manufacturing method thereof |
| JP2013225619A (en) * | 2012-04-23 | 2013-10-31 | Sumco Corp | Method of manufacturing wafer for solar battery, and method of manufacturing solar battery cell |
| CN103904151A (en) * | 2014-04-22 | 2014-07-02 | 河北工业大学 | HIT solar cell and preparing method thereof |
| CN109935645A (en) * | 2019-02-27 | 2019-06-25 | 镇江仁德新能源科技有限公司 | A kind of efficient volume production preparation method of the black silicon wafer of dry method |
| CN110993700A (en) * | 2019-10-16 | 2020-04-10 | 晋能清洁能源科技股份公司 | Heterojunction solar cell and preparation process thereof |
-
2020
- 2020-11-12 CN CN202011262587.5A patent/CN112466989A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013225619A (en) * | 2012-04-23 | 2013-10-31 | Sumco Corp | Method of manufacturing wafer for solar battery, and method of manufacturing solar battery cell |
| CN102820378A (en) * | 2012-08-27 | 2012-12-12 | 晶澳（扬州）太阳能科技有限公司 | Gettering method for prolonging effective service life of crystalline silicon substrate |
| CN103094423A (en) * | 2013-01-31 | 2013-05-08 | 英利集团有限公司 | P-type heterojuction solar battery and manufacturing method thereof |
| CN103904151A (en) * | 2014-04-22 | 2014-07-02 | 河北工业大学 | HIT solar cell and preparing method thereof |
| CN109935645A (en) * | 2019-02-27 | 2019-06-25 | 镇江仁德新能源科技有限公司 | A kind of efficient volume production preparation method of the black silicon wafer of dry method |
| CN110993700A (en) * | 2019-10-16 | 2020-04-10 | 晋能清洁能源科技股份公司 | Heterojunction solar cell and preparation process thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114188443A (en) * | 2021-11-18 | 2022-03-15 | 晋能清洁能源科技股份公司 | Preparation method of thin silicon slice HJT battery capable of reducing fragment rate |
| CN114284395A (en) * | 2021-12-15 | 2022-04-05 | 江苏爱康能源研究院有限公司 | Preparation method of silicon-based heterojunction solar cell with first texturing and then gettering |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101000064B1 (en) | Hetero-junction silicon solar cell and fabrication method thereof | |
| Lee | Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry | |
| US20150040975A1 (en) | Heterojunction solar cell based on epitaxial crystalline-silicon thin film on metallurgical silicon substrate design | |
| KR20080002657A (en) | Photovoltaic device which includes all-back-contact configuration and related processes | |
| Taguchi | Development history of high efficiency silicon heterojunction solar cell: from discovery to practical use | |
| JP2009503848A (en) | Composition gradient photovoltaic device, manufacturing method and related products | |
| US20120222731A1 (en) | Heterojunction Solar Cell Having Amorphous Silicon Layer | |
| CN112466990A (en) | Preparation process of high-efficiency heterojunction solar cell | |
| CN101976710A (en) | Method for preparing crystalline silicon hetero-junction solar cell based on hydrogenated microcrystalline silicon film | |
| CN111710748B (en) | Method for manufacturing SHJ solar cell by using heat-treated N-type monocrystalline silicon wafer | |
| CN103346214B (en) | A kind of silica-based radial homogeneity heterojunction solar cell and preparation method thereof | |
| CN111883621A (en) | TCO (transparent conductive oxide) coating process method of high-efficiency crystalline silicon heterojunction solar cell | |
| CN112466989A (en) | Preparation process of heterojunction solar cell | |
| RU2590284C1 (en) | Solar cell | |
| Muñoz et al. | Key aspects on development of high efficiency heterojunction and IBC heterojunction solar cells: Towards 22% efficiency on industrial size | |
| CN116682891A (en) | Preparation method of efficient double-POLO IBC battery structure | |
| KR101612133B1 (en) | Metal Wrap Through type solar cell and method for fabricating the same | |
| CN114765235A (en) | Heterojunction solar cell and manufacturing method thereof | |
| CN218788382U (en) | High-efficiency heterojunction solar cell | |
| CN106887483A (en) | Silicon substrate heterojunction solar cell and preparation method thereof | |
| CN106449850A (en) | High efficiency silicon-based heterojunction double-sided battery and its preparation method | |
| KR102049604B1 (en) | Solar cell and Method of manufacturing the same | |
| TWI415272B (en) | Method of fabricating rear surface point contact of solar cells | |
| JP5645734B2 (en) | Solar cell element | |
| CN211238272U (en) | Crystalline silicon/amorphous silicon heterojunction battery |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210309 |
|
| RJ01 | Rejection of invention patent application after publication |