CN211238272U

CN211238272U - Crystalline silicon/amorphous silicon heterojunction battery

Info

Publication number: CN211238272U
Application number: CN201922106506.1U
Authority: CN
Inventors: 黄金; 李高非; 王继磊; 杨骥; 张娟; 白焱辉; 贾慧君; 刘学飞; 李文敏
Original assignee: Jinneng Photovoltaic Technology Co Ltd
Current assignee: Jinneng Photovoltaic Technology Co Ltd
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2020-08-11
Anticipated expiration: 2029-11-29

Abstract

The utility model discloses a crystal silicon/amorphous silicon heterojunction battery, include: the substrate is a crystal silicon wafer; the i-type intrinsic amorphous silicon thin film, the P-type amorphous silicon thin film and the multilayer TCO thin film are sequentially grown on the front surface of the substrate; an i-type intrinsic amorphous silicon thin film, an N-type amorphous silicon thin film and a multilayer TCO thin film are sequentially grown on the back of the substrate; and a metal electrode disposed on the TCO film. The utility model discloses well battery is through making multilayer TCO film, further strengthens holistic passivation effect by a wide margin, makes this key parameter of minority carrier lifetime promoted by a wide margin, can reach the purpose that improves open circuit voltage, short-circuit current and fill factor, makes the efficiency of HJT battery promote by a wide margin.

Description

Crystalline silicon/amorphous silicon heterojunction battery

Technical Field

The utility model relates to a solar cell technical field, more specifically the utility model relates to a crystal silicon/amorphous silicon heterojunction battery that says so.

Background

Heterojunction (HJT) refers to a junction composed of two different semiconductor materials, and the interface formed by amorphous silicon/crystalline silicon belongs to the heterojunction interface. The concept of heterojunction has been proposed by Grigorovici as early as 1951, but successful heterojunction devices were not first fabricated until 1960.

There are several milestone events in the study of amorphous/crystalline silicon-based heterojunctions: (1) and a first amorphous silicon/crystalline silicon heterojunction device. The amorphous silicon/crystalline silicon heterojunction is firstly reported to be realized on a monocrystalline silicon substrate in 1968 by Grigorovici and the like, and then amorphous silicon is deposited by adopting a thermal evaporation method, so that an amorphous silicon layer does not contain hydrogen, and the defect density of the prepared amorphous silicon film is higher. (2) And a first hydrogenated amorphous silicon/crystalline silicon heterojunction device. With the development of the PECVD technology, the amorphous silicon film deposited by adopting the PECVD method has low defect density because the amorphous silicon film contains hydrogen and can saturate dangling bonds to realize good passivation effect. In 1974, Fuhs et al first realized a hydrogenated amorphous silicon/crystalline silicon (aSi: HcSi) heterojunction device. (3) And the first amorphous silicon/crystalline silicon heterojunction is used for the solar cell.The photovoltaic response of amorphous/crystalline silicon heterojunctions has been mentioned from the outset and has attracted considerable interest. In 1983, Okuda et al obtained a laminate battery (battery area of 0.25 cm) having a conversion efficiency of 12.3%²) This is the first reported application of a-Si: H/c-Si heterojunctions. (4) And the first amorphous silicon/crystalline silicon heterojunction solar cell with the intrinsic thin film layer. In 1991, an intrinsic amorphous silicon thin film is firstly used for an amorphous silicon/crystalline silicon heterojunction solar cell by a Japan Sanyo motor (incorporated into Songhua corporation), a layer of intrinsic amorphous silicon is inserted between p-n heterojunction of p-type amorphous silicon and n-type monocrystalline silicon, good passivation effect of heterojunction interface is realized, and the obtained cell efficiency reaches 18.1% (the cell area is 1 cm)²) At a low temperature of (<200 ℃ C.) to form the highest efficiency of PN junction solar cells. They named the cell as an HIT (Heterojunction with intrinsic thin-layer) cell. Taking different initials, also called HJT cells. (5) And the amorphous silicon/crystalline silicon heterojunction solar cells realize batch production. In 1997, the HIT cells of the san yang company were mass-produced and proposed HJT cell modules for different applications. (6) And the conversion efficiency of the amorphous silicon/crystalline silicon heterojunction solar cell is continuously improved. The Sanyo company has been in the leading position in the research and development and production fields of amorphous silicon/bulk silicon heterojunction solar cells with intrinsic thin film layers, and the research and development area size is 100cm²The conversion efficiency of the HJT batteries on the left and the right continuously breaks through 20%, 21%, 22% and 23% of important gateways. In 2 months 2013, panasonic corporation (having purchased the Sanyo company) announced that the conversion efficiency of HJT cells, which had an area of 1018cm, was 24.7% at the highest, exceeding the maximum efficiency (24.2%) of Sunpower corporation's IBC cells and breaking the world record of large area solar cells²Open circuit voltage of 750mV and short circuit current density of 39.5mA cm²The fill factor was 83.2%.

Since the break of UNSW by 25.6% of Panasonic in early 2014 maintained the record for nearly 20 years, Panasonic, shrarp and Kaneka surpassed 25% one after the other. Researchers from Kaneka Corporation, a japanese chemical manufacturer, promoted the photoelectric conversion rate of HJT cells to 26.3% by 2016, breaking the previous record of 25.6% loose. Currently, HJT cells stacked with IBC technology can exhibit more striking conversion efficiency, which is currently up to 26.63%.

In order to greatly improve the efficiency of the HJT battery, a need exists in the art for a heterojunction battery that can greatly improve the minority carrier lifetime as a key parameter.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a improve open circuit voltage, short-circuit current and fill factor's mesh to make the crystal silicon/amorphous silicon heterojunction battery that the efficiency of HJT battery promoted by a wide margin.

In order to achieve the above purpose, the utility model adopts the following technical scheme: a crystalline/amorphous silicon heterojunction cell, comprising:

the substrate is a crystal silicon wafer;

the i-type intrinsic amorphous silicon thin film, the P-type amorphous silicon thin film and the multilayer TCO thin film are sequentially grown on the front surface of the substrate;

an i-type intrinsic amorphous silicon thin film, an N-type amorphous silicon thin film and a multilayer TCO thin film are sequentially grown on the back of the substrate;

and a metal electrode disposed on the TCO film.

The utility model has the advantages that: the utility model discloses well battery is through making multilayer TCO film, further strengthens holistic passivation effect by a wide margin, makes this key parameter of minority carrier lifetime promoted by a wide margin, can reach the purpose that improves open circuit voltage, short-circuit current and fill factor, makes the efficiency of HJT battery promote by a wide margin.

Preferably, the crystal silicon wafer is an N-type single crystal silicon wafer or a P-type single crystal silicon wafer; the thickness of the i-type intrinsic amorphous silicon film is 5-20 nm; the metal electrode is a metal silver electrode.

By adopting the preferable scheme, the thickness of the i-layer amorphous silicon film is designed to be 5-20nm, so that a better passivation effect can be achieved, the open-circuit voltage is improved, the passivation effect is reduced when the thickness is less than 5nm, the conductivity is reduced when the thickness is more than 20nm, and the filling factor value is reduced. The metal silver electrode is adopted mainly because of the conductivity of the metal silver electrode and the maturity of the screen printing scheme, and is considered from the perspective of being suitable for mass production.

More preferably, the crystalline silicon wafer is an N-type monocrystalline silicon wafer, and the thickness of the crystalline silicon wafer is 130-200 μm; compared with a P-type monocrystalline silicon wafer, the N-type monocrystalline silicon wafer has longer minority carrier lifetime and easier passivation under the same doping concentration, and the N-type monocrystalline silicon wafer is selected to have no B-O composite attenuation in the aspect of optics. More preferably, the thickness is 150-.

More preferably, the thickness of the i-type intrinsic amorphous silicon thin film is 5-10nm, and the radicals in the thickness range are favorable for the transmission of carriers and can reduce the absorption of short-wave light.

Preferably, the number of the TCO thin films is 2-4; the TCO film is a low-power sputtering TCO film and a high-power sputtering TCO film; the thickness of the low-power sputtering TCO film is 10-40nm, and the thickness of the high-power sputtering TCO film is 50-100 nm.

More preferably, the number of TCO film layers is 2.

With the above preferred scheme, 2 layers are preferred, mainly aiming at the amorphous silicon thin film contact layer, i.e. the first layer (in the utility model, the first layer must be selected to use a low-power thin film for reducing the damage of the amorphous silicon layer), and 2 layers are the best scheme from this angle, and more than 2 layers affect the film forming quality of the TCO film layer.

Preferably, the thickness of the superposition of the low-power sputtering TCO film and the high-power sputtering TCO film is 60-140nm, and more preferably, the thickness of the superposition is 80-110 nm.

By adopting the preferable scheme, the conductive capability of the film with the thickness of less than 80nm is reduced, the filling value is lost, the cost of the film with the thickness of more than 110nm is increased, and the achieved effect is kept equal to that of 110nm

The TCO film is an ITO film, an AZO film or an ITIO film. More preferably an ITO thin film.

According to the technical scheme, compare with prior art, the utility model discloses a crystal silicon/amorphous silicon heterojunction battery and preparation method thereof has realized the further optimization at the positive back of HJT battery, the very big passivation characteristic who has kept original amorphous silicon layer of notion through introducing the power layering, simultaneously very big improvement the passivation effect that TCO layer itself brought, make minority carrier life-span obtain increasing substantially, cooperate sufficient high power kinetic energy simultaneously, make light transmission increase, therefore several electrical property parameters all can obtain promoting, the improvement to efficiency has played very big promotion effect.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a TCO film provided in a comparative example as a layer;

FIG. 2 is a schematic diagram of a two-layered TCO film according to the present invention;

1. the thin film solar cell comprises a silver metal electrode, 2 parts of a low-power sputtering ITO thin film, 3 parts of a P-type amorphous silicon thin film, 4 parts of an N-type amorphous silicon thin film, 5 parts of an i-type intrinsic amorphous silicon thin film, 6 parts of an N-type monocrystalline silicon piece and 7 parts of a high-power sputtering ITO thin film.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Experimental example 1

A crystalline/amorphous silicon heterojunction cell, comprising: a substrate of an N-type monocrystalline silicon wafer 6 with a thickness of 180 μm;

an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, a P-type amorphous silicon thin film 3 with the thickness of 10nm, a low-power sputtering ITO thin film 4 with the thickness of 20nm and two high-power sputtering ITO thin films 7 with the thickness of 40nm are sequentially grown on the front surface of an N-type monocrystalline silicon wafer 6;

an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, an N-type amorphous silicon thin film 4 with the thickness of 8nm, a low-power sputtering ITO thin film 4 with the thickness of 20nm and two high-power sputtering ITO thin films 7 with the thickness of 40nm are sequentially grown on the back surface of an N-type monocrystalline silicon wafer 6;

and a silver metal electrode 1 provided on the high-power sputtered ITO film 7.

The preparation method of the crystalline silicon/amorphous silicon heterojunction battery comprises the following steps:

step (1): carrying out texturing treatment on an N-type monocrystalline silicon wafer 6 with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;

step (2): growing an i-type intrinsic amorphous silicon film 5 with the thickness of 10nm on the front surface and the back surface of the N-type monocrystalline silicon wafer 6 in the step (1) by utilizing plasma chemical vapor deposition;

and (3): growing a P-type amorphous silicon film 3 with the thickness of 10nm on the surface of the i-type intrinsic amorphous silicon film 5 growing on the front surface in the step (2) by utilizing plasma chemical vapor deposition; and (3) growing an N-type amorphous silicon thin film 4 with the thickness of 8nm on the surface of the i-type intrinsic amorphous silicon thin film 5 grown on the back surface in the step (2).

And (4): and (3) depositing an ITO film by magnetron sputtering, respectively depositing and sputtering a first low-power sputtering ITO film 4 with the thickness of 20nm on the surfaces of the P-type amorphous silicon and the N-type amorphous silicon in the step (3) by adopting low sputtering power of 2.5kw, and depositing and sputtering a second layer with the same thickness and the thickness of 40nm and a three-layer high-power sputtering ITO film 7 with the total thickness of 80nm by adopting high power of 5 kw.

And (5): forming silver metal electrodes 1 on the front surface and the back surface by screen printing, wherein the width of a main grid is 0.8mm, the number of the main grids is 5, the width of silver auxiliary grid lines on the front surface and the back surface is 50 mu m, and the number of the lines is 100; and sintering to obtain the crystalline silicon/amorphous silicon heterojunction battery. And testing the electrical property of the cell by using the crystalline silicon/amorphous silicon heterojunction cell.

Experimental example 2

an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, a P-type amorphous silicon thin film 3 with the thickness of 10nm, two low-power sputtering ITO thin films 4 with the thickness of 25nm and a high-power sputtering ITO thin film 7 with the thickness of 50nm are sequentially grown on the front surface of an N-type monocrystalline silicon wafer 6;

an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, an N-type amorphous silicon thin film 4 with the thickness of 8nm, two low-power sputtering ITO thin films 4 with the thickness of 25nm and a high-power sputtering ITO thin film 7 with the thickness of 50nm are sequentially grown on the back surface of an N-type monocrystalline silicon wafer 6;

and a silver metal electrode 1 provided on the high-power sputtered ITO film 7.

step (1): carrying out texturing treatment on an N-type monocrystalline silicon wafer 6 with the thickness of 180 mu m, selecting KOH solution as alkali liquor, wherein the volume concentration is 3%, the temperature of a liquid medicine tank is 80 ℃, forming a pyramid textured surface, removing a surface mechanical damage layer through the KOH solution with the volume concentration of 1%, removing residual alkali liquor through RCA cleaning, and cleaning the surface;

And (4): and (3) depositing an ITO film by magnetron sputtering, respectively depositing and sputtering a first layer and a second layer of low-power sputtering ITO film 4 with the thickness of 25nm on the surfaces of the P-type amorphous silicon and the N-type amorphous silicon in the step (3) by adopting low sputtering power of 2.5kw, and depositing and sputtering a third layer of high-power sputtering ITO film 7 with the thickness of 50nm by adopting high power of 5 kw.

And (5): forming front and back silver metal electrodes by screen printing, wherein the width of a main grid is 0.8mm, the number of the main grids is 5, the width of a front and back silver auxiliary grid line is 50 mu m, and the number of lines is 100; and sintering to obtain the crystalline silicon/amorphous silicon heterojunction battery. And testing the electrical property of the cell by using the crystalline silicon/amorphous silicon heterojunction cell.

Experimental example 3

the method comprises the following steps of sequentially growing an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, a P-type amorphous silicon thin film 3 with the thickness of 10nm, a low-power sputtering ITO thin film 4 with the thickness of 13.4nm, a high-power sputtering ITO thin film 7 with the thickness of 26.6nm and a high-power sputtering ITO thin film 7 with the thickness of 60nm on the front surface of an N-type monocrystalline silicon wafer 6;

an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, an N-type amorphous silicon thin film 4 with the thickness of 8nm, two low-power sputtering ITO thin films 4 with the thickness of 25nm and a high-power sputtering ITO thin film 7 with the thickness of 40nm are sequentially grown on the back surface of an N-type monocrystalline silicon wafer 6;

and a silver metal electrode 1 provided on the high-power sputtered ITO film 7.

And (4): and (3) depositing an ITO film by magnetron sputtering, depositing and sputtering a first layer of low-power sputtering ITO film 4 with the thickness of 13.4nm on the surfaces of the P-type amorphous silicon and the N-type amorphous silicon in the step (3) by adopting low sputtering power of 2kw, depositing and sputtering a second layer of high-power sputtering ITO film 7 with the thickness of 26.6nm by adopting high power of 4kw, depositing and sputtering a third layer of high-power sputtering ITO film 7 with the thickness of 60nm by adopting high power of 9kw, wherein the total thickness of the high-power sputtering ITO film 7 is 86.6 nm.

Comparative example

an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, a P-type amorphous silicon thin film 3 with the thickness of 10nm and an ITO thin film 4 with the thickness of 100nm are sequentially grown on the front surface of an N-type monocrystalline silicon wafer 6;

an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm and an ITO thin film 4 with the thickness of 100nm are sequentially grown on the back of an N-type monocrystalline silicon wafer 6;

and a silver metal electrode 1 provided on the ITO film 4.

step (1): carrying out texturing treatment on an N-type monocrystalline silicon wafer with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;

step (2): growing an i-type intrinsic amorphous silicon film with the thickness of 10nm on the front surface and the back surface of the N-type monocrystalline silicon wafer in the step (1) by utilizing plasma chemical vapor deposition;

and (3): growing a P-type amorphous silicon film with the thickness of 10nm on the surface of the i-type intrinsic amorphous silicon film grown on the front surface in the step (2) by utilizing plasma chemical vapor deposition; and (3) growing an N-type amorphous silicon film with the thickness of 8nm on the surface of the i-type intrinsic amorphous silicon film grown on the back surface in the step (2).

And (4): and (3) depositing an ITO film by magnetron sputtering, and depositing and sputtering the ITO film with the thickness of 100nm on the surfaces of the P-type amorphous silicon and the N-type amorphous silicon in the step (3) by adopting sputtering power of 5 kw.

Performance testing

The electrical performance results of the cells of experimental examples 1-3 and comparative example are shown in table 1:

the embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A crystalline/amorphous silicon heterojunction cell, comprising:

the substrate is a crystal silicon wafer;

and a metal electrode disposed on the TCO film.

2. The crystalline silicon/amorphous silicon heterojunction cell according to claim 1, wherein the crystalline silicon wafer is an N-type monocrystalline silicon wafer or a P-type monocrystalline silicon wafer; the thickness of the i-type intrinsic amorphous silicon film is 5-20 nm; the metal electrode is a metal silver electrode.

3. The crystalline silicon/amorphous silicon heterojunction cell as claimed in claim 1, wherein the number of TCO thin films is 2-4; the TCO film is a low-power sputtering TCO film and a high-power sputtering TCO film; the thickness of the low-power sputtering TCO film is 10-40nm, and the thickness of the high-power sputtering TCO film is 50-100 nm.

4. The crystalline silicon/amorphous silicon heterojunction cell as claimed in claim 3, wherein the TCO film is an ITO film, an AZO film or an ITiO film.