CN113707734B - Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure - Google Patents
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- 238000002161 passivation Methods 0.000 title claims abstract description 53
- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 38
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 48
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052796 boron Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 32
- 230000005641 tunneling Effects 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000011574 phosphorus Substances 0.000 claims abstract description 16
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical class N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000000243 solution Substances 0.000 claims description 35
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- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 21
- 230000005525 hole transport Effects 0.000 claims description 20
- 238000002360 preparation method Methods 0.000 claims description 18
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 14
- 239000003945 anionic surfactant Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 11
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 10
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 10
- 238000010521 absorption reaction Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000003960 organic solvent Substances 0.000 claims description 8
- 239000002243 precursor Substances 0.000 claims description 8
- 238000007650 screen-printing Methods 0.000 claims description 8
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- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
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- 238000004140 cleaning Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 150000004820 halides Chemical class 0.000 claims description 4
- 229910001507 metal halide Inorganic materials 0.000 claims description 4
- 150000005309 metal halides Chemical class 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 229910000480 nickel oxide Inorganic materials 0.000 claims description 4
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims description 4
- 238000003756 stirring Methods 0.000 claims description 4
- XMWRBQBLMFGWIX-UHFFFAOYSA-N C60 fullerene Chemical class C12=C3C(C4=C56)=C7C8=C5C5=C9C%10=C6C6=C4C1=C1C4=C6C6=C%10C%10=C9C9=C%11C5=C8C5=C8C7=C3C3=C7C2=C1C1=C2C4=C6C4=C%10C6=C9C9=C%11C5=C5C8=C3C3=C7C1=C1C2=C4C6=C2C9=C5C3=C12 XMWRBQBLMFGWIX-UHFFFAOYSA-N 0.000 claims description 3
- 229920000144 PEDOT:PSS Polymers 0.000 claims description 3
- 229910000085 borane Inorganic materials 0.000 claims description 3
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 3
- 239000004408 titanium dioxide Substances 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 239000002002 slurry Substances 0.000 claims description 2
- WXRGABKACDFXMG-UHFFFAOYSA-N trimethylborane Chemical compound CB(C)C WXRGABKACDFXMG-UHFFFAOYSA-N 0.000 claims description 2
- 239000011787 zinc oxide Substances 0.000 claims description 2
- 239000000969 carrier Substances 0.000 abstract description 8
- 238000005215 recombination Methods 0.000 abstract description 6
- 230000006798 recombination Effects 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
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- 210000002268 wool Anatomy 0.000 description 4
- 239000003513 alkali Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000011066 ex-situ storage Methods 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000006096 absorbing agent Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- -1 sodium alkyl sulfate Chemical class 0.000 description 2
- GVGUFUZHNYFZLC-UHFFFAOYSA-N dodecyl benzenesulfonate;sodium Chemical compound [Na].CCCCCCCCCCCCOS(=O)(=O)C1=CC=CC=C1 GVGUFUZHNYFZLC-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229940080264 sodium dodecylbenzenesulfonate Drugs 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
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- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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Abstract
A crystalline silicon/perovskite stacked solar cell with a hole selective passivation structure, comprising: an n-type crystalline silicon TOPCon structure as a bottom cell, a perovskite structure as a top cell, and a transparent conductive film as an intermediate layer, wherein the n-type crystalline silicon TOPCon structure comprises any one of the following structures: ① The back metal electrode, the hydrogenated silicon nitride, the phosphorus doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, the tunneling silicon oxide and the boron doped thin polysilicon are sequentially arranged, or the back metal electrode, the hydrogenated silicon nitride, the phosphorus doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, the intrinsic amorphous silicon and the boron doped amorphous silicon are sequentially arranged ②. According to the invention, by utilizing the characteristic that the photo-generated carriers of the n-type solar cell are mainly concentrated on one side of the emitter on the front surface of the cell and adopting the passivation layer with excellent performance, the carrier recombination loss can be reduced, and the rapid and effective collection of minority carriers can be realized; meanwhile, the method is simple and feasible, and has industrial feasibility.
Description
Technical Field
The invention relates to a technology in the field of solar cells, in particular to a crystalline silicon/perovskite laminated solar cell with a hole selective passivation structure.
Background
The conversion efficiency of the existing crystalline silicon/perovskite laminated solar cell is limited by low short-circuit current density, and the magnitude of the short-circuit current is often influenced by front surface reflection loss, film parasitic absorption loss and interface carrier recombination loss, wherein the interface carrier recombination loss is the biggest difficulty of technical improvement. Because the photo-generated carriers are mainly generated near the emitter region on the front surface of the cell, improving the passivation performance of the surface of the emitter region can effectively enhance the collection capability of positive electrode to minority carriers, and further improve the short-circuit current density and conversion efficiency of the laminated solar cell.
The existing crystalline silicon solar cell has a narrow solar spectrum utilization range and does not consider the problem of matching of a top cell and a bottom cell in the laminated cell, so that the improvement degree of the conversion efficiency of the solar cell is limited, the existing perovskite solar cell has a longer preparation process and a complex preparation process, and the laminated cell is more difficult to prepare due to the complex process.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the crystalline silicon/perovskite laminated solar cell with the hole selective passivation structure, and the characteristics that the photo-generated carriers of the n-type solar cell are mainly concentrated on one side of the emitter on the front surface of the cell are utilized, and the passivation layer with excellent performance is adopted, so that the carrier recombination loss can be reduced, and the rapid and effective collection of minority carriers can be realized; meanwhile, the method is simple and feasible, and has industrial feasibility.
The invention is realized by the following technical scheme:
The invention relates to a crystalline silicon/perovskite laminated solar cell with a hole selective passivation structure, comprising: an n-type crystalline silicon tunneling oxidation passivation contact (Tunnel Oxide Passivated Contact, TOPCon) structure as a bottom cell, a perovskite structure as a top cell, and a transparent conductive film as an intermediate layer.
The front side emitter surface of the bottom cell adopts a tunneling silicon oxide/boron doped polycrystalline silicon stacked structure or an intrinsic amorphous silicon/boron doped amorphous silicon stacked structure.
The front side emitter surface of the top cell adopts a surface active agent passivation layer/hole transport layer stacked structure.
The n-type crystalline silicon TOPCon structure comprises any one of the following structures: ① The back metal electrode, the hydrogenated silicon nitride, the phosphorus doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, the tunneling silicon oxide and the boron doped thin polysilicon are sequentially arranged, or the back metal electrode, the hydrogenated silicon nitride, the phosphorus doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, the intrinsic amorphous silicon and the boron doped amorphous silicon are sequentially arranged ②.
The perovskite battery includes: the electron transport layer, the perovskite, the surfactant passivation layer, the hole transport layer, the antireflection layer and the positive metal electrode are sequentially arranged.
The invention relates to a preparation method of the solar cell, which comprises the steps of preparing an n-type crystalline silicon TOPCon structure on a substrate, depositing a transparent conductive film on a front surface passivation layer of the n-type crystalline silicon TOPCon structure by adopting a magnetron sputtering method, taking the transparent conductive film as an intermediate layer for connecting a bottom cell and a top cell, and preparing a perovskite cell on the intermediate layer.
The n-type crystalline silicon TOPCon structure is prepared by the following steps:
Step 1) preparation of a bottom cell crystalline silicon substrate: n-type monocrystalline silicon is used as a substrate, after damage layer removal and cleaning, the substrate is placed in a mixed solution of NaOH and isopropanol for texturing,
The concentration of the NaOH alkali solution is 1-3%, and the concentration of the isopropanol solution is 2-10%;
Step 2), preparing a passivation layer of a tunneling silicon oxide/boron doped thin polycrystalline silicon stacked structure or an intrinsic amorphous silicon/boron doped amorphous silicon stacked structure on the front surface of the bottom cell;
a) A layer of tunneling silicon oxide is deposited by a low-pressure chemical vapor deposition (Low pressure chemical vapor deposition, LPCVD) method, a layer of thin amorphous silicon is deposited by silane thermal decomposition, and the boron doped amorphous silicon is annealed at high temperature to form polysilicon with the thickness of 10-50 nm, wherein the boron impurity concentration in the polysilicon layer is 5 multiplied by 10 19～5×1020cm-3.
The boron doping includes in-situ doping and ex-situ doping, wherein: in-situ doping is to introduce silane and borane in the process of depositing thin amorphous silicon, and introduce silane only in the process of ex-situ doping, and then to carry out boron doping by adopting high-temperature boron diffusion.
The deposition temperature of the tunneling silicon oxide is 550-650 ℃.
The deposition temperature of the thin polysilicon is 600-700 ℃.
The high-temperature boron diffusion is carried out at 800-1100 ℃.
B) An intrinsic amorphous silicon layer is deposited by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, the thickness of the amorphous silicon layer is 1-5 nm, then a boron doped amorphous silicon layer is deposited by a PECVD method, the doping source gas is borane or trimethylboron, the thickness is 2-10 nm, and the boron impurity concentration is more than 1X 10 20cm-3.
The deposition temperature of the intrinsic amorphous silicon is 100-300 ℃.
Step 3) preparation of bottom cell back surface TOPCon structure: after etching the back of the silicon wafer, firstly growing a layer of tunneling silicon oxide by an LPCVD method, and then depositing polysilicon with phosphorus doping, wherein the thickness of the tunneling silicon oxide is 0.5-2 nm, the thickness of the polysilicon is 50-200 nm, and the phosphorus doping concentration is more than 2X 10 19cm-3.
Step 4) preparation of a passivation layer and a metal electrode on the back surface of the bottom battery: and depositing a layer of hydrogenated silicon nitride with the thickness of 50-150 nm on the back surface of the silicon wafer by adopting a PECVD method, preparing a metal Ag grid electrode by adopting metal slurry with burning-through property on the hydrogenated silicon nitride by adopting a screen printing method, and thus obtaining the bottom layer battery.
The working pressure of the magnetron sputtering of the intermediate layer is 0.1-1 Pa, the sputtering power is 0.2-2 kW, and the thickness of the intermediate layer is 5-20 nm.
The perovskite battery is prepared by the following steps:
step i) preparation of a top cell back surface electron transport layer: and spin-coating a solution of titanium dioxide or fullerene derivative material on the surface of the intermediate layer, and curing at high temperature to form an electron transport layer with the thickness of 20-80 nm.
Step ii) preparation of top cell perovskite substrate: dissolving metal halide and organic halide in an organic solvent, stirring to obtain a perovskite precursor solution, spin-coating the perovskite precursor solution on an electron transport layer, and annealing to obtain a perovskite absorption layer with the thickness of 300-600 nm.
Step iii) preparation of a top cell front surface active agent passivation layer/hole transport layer stack: dissolving an anionic surfactant in an organic solvent to obtain an anionic surfactant solution, spin-coating the anionic surfactant solution on the surface of perovskite twice in vacuum equipment, and drying to form a surfactant passivation layer with the thickness of 1-5 nm; and spin-coating a solution of nickel oxide or PEDOT: PSS material on the surface of the surfactant passivation layer, and then performing heat treatment to solidify the solution to form a hole transport layer with the thickness of 20-80 nm.
The two spin coating steps are as follows: low-speed spin coating at 400-600 rpm and high-speed spin coating at 3000-5000 rpm.
And the temperature of the surfactant layer is 50-100 ℃ after being dried.
The anionic surfactant solution is not limited to sodium dodecyl benzene sulfonate, sodium alkyl sulfate or sodium alkylaryl sulfonate.
And the temperature of the heat treatment of the hole transport layer is not higher than 100 ℃.
Step iv) preparation of transparent conductive layer and metal electrode on front surface of top cell: and depositing a transparent conductive layer, namely an Indium Tin Oxide (ITO) film or an aluminum-doped zinc oxide (AZO) film, on the surface of the hole transport layer by adopting a magnetron sputtering method, and finally preparing a metal Ag grid electrode by adopting a screen printing method, thereby obtaining the top-layer battery.
Technical effects
According to the invention, TOPCon technology, heterojunction technology and perovskite surface passivation technology are adopted, and interface passivation layer design is carried out on one end of the emitter of the bottom battery and one end of the emitter of the top battery, so that the conversion efficiency of the battery is improved, and meanwhile, the existing process technology of a production line can be compatible. Aiming at the situation that photo-generated carriers are gathered at one end of an emitter near the surface of the battery, a TOPCon structure which selectively transmits the carriers is adopted at one end of the emitter of the bottom battery, wherein the doped polysilicon layer is thinner and has the thickness of less than 50nm, so that excellent passivation characteristics can be ensured, more photon parasitic absorption loss can be avoided, and the TOPCon structure can be realized by an LPCVD method or a magnetron sputtering method; amorphous silicon has excellent passivation characteristics, the defect of higher carrier recombination loss can be greatly improved by the application of the amorphous silicon in a laminated battery, the thickness of the doped amorphous silicon layer is lower than 10nm, and the amorphous silicon can be realized by PECVD or physical vapor deposition (Physical vapor deposition, PVD) methods; the surfactant layer is introduced between the top cell and the hole transport layer, so that the carrier recombination loss at one end of the emitter of the perovskite layer can be improved, and the structure can be realized by a spin coating method in vacuum equipment.
Drawings
FIG. 1 is a schematic diagram of a crystalline silicon/perovskite stacked solar cell with a tunneling silicon oxide/boron doped polysilicon stacked layer on the front surface of the crystalline silicon bottom cell of example 1;
FIG. 2 is a schematic diagram of a crystalline silicon/perovskite stacked solar cell with an intrinsic amorphous silicon/boron doped amorphous silicon stacked layer on the front surface of the crystalline silicon bottom cell of example 2;
FIG. 3 is a schematic diagram of a conventional stacked solar cell structure without passivation stack and surfactant layers at the emitter ends of the bottom and top cells;
In the figure: hydrogenated silicon nitride 1,2 phosphorus doped polysilicon, 3 tunneling silicon oxide, 4n type crystalline silicon substrate, 5 tunneling silicon oxide, 6 boron doped polysilicon, 7 intermediate layer, 8 electron transport layer, 9 perovskite absorption layer, 10 surfactant passivation layer, 11 hole transport layer, 12 transparent conductive layer, 13 and 14 positive Ag electrode and back Ag electrode respectively, 15 intrinsic amorphous silicon, 16 boron doped amorphous silicon, 17 boron emitter.
Detailed Description
Example 1
As shown in fig. 1, this embodiment relates to a crystalline silicon/perovskite stacked solar cell with a hole selective passivation structure, including: back metal electrode, hydrogenated silicon nitride, phosphorus doped polysilicon, tunnel silicon oxide, n-type crystalline silicon, tunnel silicon oxide, boron doped thin polysilicon, intermediate layer, electron transport layer, perovskite, surfactant passivation layer, hole transport layer, transparent conductive layer and positive metal electrode.
The solar cell in this embodiment is prepared by the following steps:
step one, a crystalline silicon substrate: and (3) selecting n-type monocrystalline silicon 4 as a bottom battery, removing a damaged layer, cleaning, placing in a mixed solution of NaOH and isopropanol, and making wool, wherein the concentration of an alkali solution of NaOH is preferably 2%, and the concentration of an isopropanol solution is preferably 5%, so as to prepare the small pyramid wool.
Step two, a passivation layer is arranged on the front surface of the bottom battery: firstly growing a layer of tunneling silicon oxide 5 by an LPCVD method, then depositing a layer of amorphous silicon by silane thermal decomposition, and forming polycrystalline silicon 6 by high-temperature annealing of boron doped amorphous silicon, wherein boron doping comprises in-situ doping and ex-situ doping, the deposition temperature of the tunneling silicon oxide is preferably 600 ℃, the thickness is preferably 0.8nm, the deposition temperature of the thin polycrystalline silicon is preferably 630 ℃, the thickness is preferably 25nm, the boron diffusion temperature in the polycrystalline silicon layer is preferably 1000 ℃, and the boron impurity concentration is preferably 1 multiplied by 10 20cm-3.
Step three, bottom cell back surface TOPCon structure: after etching the back of the silicon wafer, a layer of tunneling silicon oxide 3 is grown by an LPCVD method, and then phosphorus doped polysilicon 2 is deposited, wherein the thickness of the tunneling silicon oxide is preferably 1nm, the thickness of the polysilicon is preferably 100nm, and the phosphorus doping concentration is 2 multiplied by 10 20cm-3.
Step four, a passivation layer and a metal electrode are arranged on the back surface of the bottom battery: depositing a layer of hydrogenated silicon nitride 1 on the back surface of the silicon wafer by adopting a PECVD method, wherein the thickness is preferably 100nm; the metal Ag gate line electrode 14 was prepared by screen printing using a metal paste having a burn-through type to hydrogenated silicon nitride, thereby obtaining a bottom layer battery.
Fifth, the middle layer: and a transparent conductive film 7 is deposited on the passivation layer on the front surface of the bottom cell by a magnetron sputtering method and is used as an intermediate layer for connecting the bottom cell and the top cell, wherein the working pressure is preferably 0.7Pa, the sputtering power is preferably 1kW, and the thickness of the intermediate layer is 10nm.
Step six, electron transport layer on the back surface of the top cell: and spin-coating a titanium dioxide solution on the surface of the intermediate layer, and curing at high temperature to form an electron transport layer 8 with the thickness of 60nm.
Step seven, top cell perovskite absorber layer: dissolving metal halide and organic halide in an organic solvent, stirring to obtain a perovskite precursor solution, spin-coating the perovskite precursor solution on an electron transport layer, and annealing to obtain a perovskite absorption layer 9 with the thickness of 500nm.
Step eight, top cell front surface active agent passivation layer: dissolving an anionic surfactant in an organic solvent to obtain an anionic surfactant solution, spin-coating the anionic surfactant solution on the surface of perovskite in vacuum equipment, and drying to form a surfactant passivation layer, wherein the low-speed spin-coating is performed firstly, the spin-coating parameter is preferably 550rmp, then the high-speed spin-coating is performed, the spin-coating parameter is preferably 4500rmp, the drying temperature is preferably 75 ℃, and the thickness of the prepared surfactant passivation layer is preferably 2nm;
Step nine, a top cell front surface hole transport layer: and (3) spin-coating a nickel oxide solution on the surface of the surfactant passivation layer, and then performing heat treatment to solidify the nickel oxide solution to form the hole transport layer, wherein the heat treatment temperature is preferably 80 ℃, and the thickness is preferably 70nm.
Step ten, top cell front surface antireflection layer and metal electrode: depositing an ITO film on the surface of the hole transport layer by adopting a magnetron sputtering method, wherein the thickness is preferably 30nm; finally, preparing the metal Ag grid line electrode by a screen printing method, thereby obtaining the top-layer battery.
Through specific practical experiments, under the standard specific environment setting, the bottom cell and the top cell are respectively tested, the front surface of the bottom cell adopts a tunneling silicon oxide/thin polycrystalline silicon stacked structure, and compared with the cells with the polycrystalline silicon thickness of 25nm and 80nm, the result shows that the passivation performance of the bottom cell and the polycrystalline silicon is consistent, but the short-circuit current of the cell with the thinner polycrystalline silicon is 4-5 mA/cm 2, the conversion efficiency of the corresponding bottom cell can be improved by more than 2% (absolute value), and the open-circuit voltage of the cell with the stacked passivation layer is higher than that of the cell without the stacked passivation layer. The front surface of the top cell is compared with the front surface of the top cell, whether the surface active agent passivation layer is adopted or not, the open-circuit voltage, the short-circuit current and the filling factor of the perovskite cell with the surface active agent are respectively 0.06V, 1.8mA/cm 2 and more than 5 percent higher than those of the reference cell, and the conversion efficiency of the corresponding top cell can be improved by more than 3.8 percent (absolute value).
Compared with the prior art, the battery obtained by the embodiment has more excellent interface passivation property, higher open-circuit voltage and lower parasitic absorption, and also has higher carrier collection efficiency and higher corresponding short-circuit current.
Example 2
As shown in fig. 2, compared with embodiment 1, the tunnel oxide and the boron doped thin polysilicon of the solar cell of this embodiment below the intermediate layer may be replaced with intrinsic amorphous silicon and boron doped amorphous silicon.
The solar cell in this embodiment is prepared by the following steps:
step one, a crystalline silicon substrate: and (3) selecting n-type monocrystalline silicon 4 as a bottom battery, removing a damaged layer, cleaning, placing in a mixed solution of NaOH and isopropanol, and making wool, wherein the concentration of an alkali solution of NaOH is preferably 2%, and the concentration of an isopropanol solution is preferably 5%, so as to prepare the small pyramid wool.
Step two, a passivation layer is arranged on the front surface of the bottom battery: an intrinsic amorphous silicon layer 15 is deposited by a PECVD method, the thickness is preferably 2nm, the deposition temperature is preferably 200 ℃, and a boron doped amorphous silicon layer 16 is deposited, the thickness is preferably 5nm, and the boron impurity concentration is 2 multiplied by 10 20cm-3.
Step three, bottom cell back surface TOPCon structure: after etching the back of the silicon wafer, a layer of tunneling silicon oxide 3 is grown by an LPCVD method, and then phosphorus doped polysilicon 2 is deposited, wherein the thickness of the tunneling silicon oxide is preferably 1nm, the thickness of the polysilicon is preferably 100nm, and the phosphorus doping concentration is 2 multiplied by 10 20cm-3.
Step four, a passivation layer and a metal electrode are arranged on the back surface of the bottom battery: depositing a layer of hydrogenated silicon nitride 1 on the back surface of the silicon wafer by adopting a PECVD method, wherein the thickness is preferably 100nm; the metal Ag gate line electrode 14 was prepared by screen printing using a metal paste having a burn-through type to hydrogenated silicon nitride, thereby obtaining a bottom layer battery.
Fifth, the middle layer: and a transparent conductive film 7 is deposited on the passivation layer on the front surface of the bottom cell by a magnetron sputtering method and is used as an intermediate layer for connecting the bottom cell and the top cell, wherein the working pressure is preferably 0.7Pa, the sputtering power is preferably 1kW, and the thickness of the intermediate layer is 10nm.
Step six, electron transport layer on the back surface of the top cell: the surface of the intermediate layer was spin-coated with a solution of fullerene derivative material and cured at high temperature to form an electron transport layer 8 having a thickness of 50nm.
Step seven, top cell perovskite absorber layer: dissolving metal halide and organic halide in an organic solvent, stirring to obtain a perovskite precursor solution, spin-coating the perovskite precursor solution on an electron transport layer, and annealing to obtain a perovskite absorption layer 9 with the thickness of 500nm.
Step eight, top cell front surface active agent passivation layer: dissolving an anionic surfactant in an organic solvent to obtain an anionic surfactant solution, spin-coating the anionic surfactant solution on the surface of perovskite in vacuum equipment, and drying to form a surfactant passivation layer with the thickness of preferably 2nm;
Step nine, a top cell front surface hole transport layer: and spin-coating PEDOT: PSS solution on the surface of the surfactant passivation layer, and performing heat treatment to solidify the solution to form a hole transport layer, wherein the thickness is preferably 60nm.
Step ten, top cell front surface antireflection layer and metal electrode: depositing an AZO film on the surface of the hole transport layer by adopting a magnetron sputtering method, wherein the thickness is preferably 20nm; finally, preparing the metal Ag grid line electrode by a screen printing method, thereby obtaining the top-layer battery.
Through specific practical experiments, under the standard specific environment setting, the bottom battery and the top battery are respectively tested, the front surface of the bottom battery adopts an intrinsic amorphous silicon/boron doped amorphous silicon stacking structure, and as a result, when the thickness of the boron doped amorphous silicon is changed from 1nm to 10nm, the open circuit voltage and the filling factor of the battery are both improved when the thickness of the amorphous silicon is increased from 1nm to 5nm, but when the thickness of the amorphous silicon is increased from 5nm to 10nm, the open circuit voltage and the filling factor of the battery are both stable and unchanged; because the amorphous silicon layer has parasitic absorption on incident photons, the short-circuit current of the battery is reduced along with the increase of the thickness of the amorphous silicon, and when the thickness is increased by 1nm, the short-circuit current density is reduced by 0.13mA/cm 2, and the conversion efficiency of the bottom battery is optimal when the thickness of the boron doped amorphous silicon is 5 nm. The top cell also has various electrical parameter advantages.
Compared with the prior art, the optimized structural parameters obtained by the embodiment enable the battery to have higher open-circuit voltage and filling factor, so that the battery has higher conversion efficiency.
The foregoing embodiments may be partially modified in numerous ways by those skilled in the art without departing from the principles and spirit of the invention, the scope of which is defined in the claims and not by the foregoing embodiments, and all such implementations are within the scope of the invention.
Claims (1)
1. A method for preparing a crystalline silicon/perovskite laminated solar cell with a hole selective passivation structure, the method comprising: an n-type crystalline silicon TOPCon structure as a bottom cell, a perovskite structure as a top cell, and a transparent conductive film as an intermediate layer;
The n-type crystalline silicon TOPCon structure comprises any one of the following structures: ① The back metal electrode, the hydrogenated silicon nitride, the phosphorus doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, the tunneling silicon oxide and the boron doped thin polysilicon are sequentially arranged, or the back metal electrode, the hydrogenated silicon nitride, the phosphorus doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, the intrinsic amorphous silicon and the boron doped amorphous silicon are sequentially arranged ②;
The front side emitter surface of the bottom cell adopts a tunneling silicon oxide/boron doped polycrystalline silicon stacked structure or an intrinsic amorphous silicon/boron doped amorphous silicon stacked structure;
The front side emitter surface of the top battery adopts a surface active agent passivation layer/hole transport layer stacking structure;
The perovskite battery includes: the electron transport layer, the perovskite, the surfactant passivation layer, the hole transport layer, the antireflection layer and the positive metal electrode are sequentially arranged;
the preparation method comprises the steps of preparing an n-type crystalline silicon TOPCon structure on a substrate, depositing a transparent conductive film on a front surface passivation layer of the n-type crystalline silicon TOPCon structure by adopting a magnetron sputtering method, taking the transparent conductive film as an intermediate layer for connecting a bottom battery and a top battery, and preparing a perovskite battery on the intermediate layer;
The n-type crystalline silicon TOPCon structure is prepared by the following steps:
Step 1) preparation of a bottom cell crystalline silicon substrate: n-type monocrystalline silicon is used as a substrate, after damage layer removal and cleaning, the substrate is placed in a mixed solution of NaOH and isopropanol for texturing,
Step 2), preparing a passivation layer of a tunneling silicon oxide/boron doped thin polycrystalline silicon stacked structure or an intrinsic amorphous silicon/boron doped amorphous silicon stacked structure on the front surface of the bottom cell;
a) Depositing a layer of tunneling silicon oxide by an LPCVD method, and then depositing a layer of thin amorphous silicon by silane thermal decomposition, wherein the boron doped amorphous silicon is annealed at a high temperature to form polycrystalline silicon with the thickness of 10-50 nm, and the boron impurity concentration in the polycrystalline silicon layer is 5 multiplied by 10 19~5×1020 cm-3;
b) Depositing a layer of intrinsic amorphous silicon by a PECVD method, wherein the thickness of the amorphous silicon is 1-5 nm, then depositing a layer of boron doped amorphous silicon by a PECVD method, wherein the doping source gas is borane or trimethylboron, the thickness is 2-10 nm, and the boron impurity concentration is more than 1X 10 20 cm-3;
Step 3) preparation of bottom cell back surface TOPCon structure: after etching the back surface of the silicon wafer, firstly growing a layer of tunneling silicon oxide by an LPCVD method, and then depositing polysilicon with phosphorus doping, wherein the thickness of the tunneling silicon oxide is 0.5-2 nm, the thickness of the polysilicon is 50-200 nm, and the phosphorus doping concentration is more than 2 multiplied by 10 19 cm-3;
Step 4) preparation of a passivation layer and a metal electrode on the back surface of the bottom battery: depositing a layer of hydrogenated silicon nitride with the thickness of 50-150 nm on the back surface of the silicon wafer by adopting a PECVD method, preparing a metal Ag grid electrode by adopting metal slurry with burning-through property on the hydrogenated silicon nitride by adopting a screen printing method, and thus obtaining a bottom layer battery;
The perovskite battery is prepared by the following steps:
Step i) preparation of a top cell back surface electron transport layer: spin-coating a solution of titanium dioxide or fullerene derivative material on the surface of the intermediate layer, and curing at high temperature to form an electron transport layer with the thickness of 20-80 nm;
Step ii) preparation of top cell perovskite substrate: dissolving metal halide and organic halide in an organic solvent, stirring to obtain a perovskite precursor solution, spin-coating the perovskite precursor solution on an electron transport layer, and annealing to obtain a perovskite absorption layer with the thickness of 300-600 nm;
Step iii) preparation of a top cell front surface active agent passivation layer/hole transport layer stack: dissolving an anionic surfactant in an organic solvent to obtain an anionic surfactant solution, spin-coating the anionic surfactant solution on the surface of perovskite twice in vacuum equipment, and drying to form a surfactant passivation layer with the thickness of 1-5 nm; spin-coating a solution of nickel oxide or PEDOT: PSS material on the surface of the surfactant passivation layer, and curing the solution under the high-temperature annealing condition to form a hole transport layer with the thickness of 20-80 nm;
Step iv) preparation of transparent conductive layer and metal electrode on front surface of top cell: depositing a transparent conductive layer, namely an indium tin oxide film or an aluminum-doped zinc oxide film, on the surface of the hole transport layer by adopting a magnetron sputtering method, and finally preparing a metal Ag grid electrode by adopting a screen printing method so as to obtain a top-layer battery;
the two spin coating steps are as follows: low-speed spin coating at 400-600 rpm and high-speed spin coating at 3000-5000 rpm.
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| CN116014032A (en) * | 2023-02-14 | 2023-04-25 | 通威太阳能(眉山)有限公司 | Method for preparing solar cell |
| CN117253927A (en) * | 2023-11-14 | 2023-12-19 | 无锡华晟光伏科技有限公司 | Solar laminated cell and preparation method thereof |
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