CN113707734A - Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure - Google Patents

Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure Download PDF

Info

Publication number
CN113707734A
CN113707734A CN202110973198.1A CN202110973198A CN113707734A CN 113707734 A CN113707734 A CN 113707734A CN 202110973198 A CN202110973198 A CN 202110973198A CN 113707734 A CN113707734 A CN 113707734A
Authority
CN
China
Prior art keywords
layer
silicon
perovskite
cell
boron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110973198.1A
Other languages
Chinese (zh)
Other versions
CN113707734B (en
Inventor
沈文忠
丁东
李正平
高超
裴骏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Linyang Photovoltaic Technology Co ltd
Shanghai Jiaotong University
Original Assignee
Jiangsu Linyang Photovoltaic Technology Co ltd
Shanghai Jiaotong University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Linyang Photovoltaic Technology Co ltd, Shanghai Jiaotong University filed Critical Jiangsu Linyang Photovoltaic Technology Co ltd
Priority to CN202110973198.1A priority Critical patent/CN113707734B/en
Publication of CN113707734A publication Critical patent/CN113707734A/en
Application granted granted Critical
Publication of CN113707734B publication Critical patent/CN113707734B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/10—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising heterojunctions between organic semiconductors and inorganic semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/10—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising heterojunctions between organic semiconductors and inorganic semiconductors
    • H10K30/15—Sensitised wide-bandgap semiconductor devices, e.g. dye-sensitised TiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/10—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising heterojunctions between organic semiconductors and inorganic semiconductors
    • H10K30/15—Sensitised wide-bandgap semiconductor devices, e.g. dye-sensitised TiO2
    • H10K30/151—Sensitised wide-bandgap semiconductor devices, e.g. dye-sensitised TiO2 the wide bandgap semiconductor comprising titanium oxide, e.g. TiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/80—Constructional details
    • H10K30/88—Passivation; Containers; Encapsulations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Electromagnetism (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Sustainable Energy (AREA)
  • Sustainable Development (AREA)
  • Photovoltaic Devices (AREA)

Abstract

A crystalline silicon/perovskite tandem solar cell with a hole selective passivation structure, comprising: the solar cell comprises an n-type crystalline silicon TOPCon structure as a bottom cell, a perovskite structure as a top cell and a transparent conductive thin film as an intermediate layer, wherein the n-type crystalline silicon TOPCon structure comprises any one of the following structures: the thin polysilicon film comprises a back metal electrode, hydrogenated silicon nitride, phosphorus-doped polysilicon, tunneling silicon oxide, n-type crystalline silicon, tunneling silicon oxide and boron-doped thin polysilicon which are arranged in sequence, or comprises the back metal electrode, the hydrogenated silicon nitride, the phosphorus-doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, intrinsic amorphous silicon and the boron-doped amorphous silicon which are arranged in sequence. According to the invention, by utilizing the characteristic that photon-generated carriers of the n-type solar cell are mainly concentrated on one side of the emitter on the front surface of the cell and adopting the passivation layer with excellent performance, the recombination loss of the carriers can be reduced, and the fast and effective collection of minority carriers can be realized; meanwhile, the method is simple and feasible, and has industrial feasibility.

Description

Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure
Technical Field
The invention relates to a technology in the field of solar cells, in particular to a crystalline silicon/perovskite laminated solar cell with a hole selective passivation structure.
Background
The conversion efficiency of the existing crystalline silicon/perovskite laminated solar cell is limited by low short-circuit current density, and the magnitude of the short-circuit current is often influenced by front surface reflection loss, film layer parasitic absorption loss and interface carrier recombination loss, wherein the interface carrier recombination loss is the biggest difficulty in technical improvement. Because the photon-generated carriers are mainly generated near the emitter region on the front surface of the cell, the surface passivation performance of the emitter region is improved, so that the collection capability of the positive electrode on minority carriers can be effectively enhanced, and the short-circuit current density and the conversion efficiency of the laminated solar cell are further improved.
The existing crystalline silicon solar cell has a narrow solar spectrum utilization range and does not consider the problem of matching between a top cell and a bottom cell in a tandem cell, so that the improvement degree of the conversion efficiency of the solar cell is limited, and the existing perovskite solar cell has a long preparation process, a complex preparation process and a complex process, so that the preparation of the tandem cell is more difficult to realize.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the crystalline silicon/perovskite laminated solar cell with the hole selective passivation structure, which utilizes the characteristic that photon-generated carriers of an n-type solar cell are mainly concentrated on one side of an emitter on the front surface of the cell, and can reduce the recombination loss of the carriers and realize the quick and effective collection of minority carriers by adopting the passivation layer with excellent performance; meanwhile, the method is simple and feasible, and has industrial feasibility.
The invention is realized by the following technical scheme:
the invention relates to a crystalline silicon/perovskite laminated solar cell with a hole selective passivation structure, which comprises: the solar cell comprises an n-type crystalline silicon tunneling oxidation passivation Contact (TOPCon) structure serving as a bottom cell, a perovskite structure serving as a top cell and a transparent conductive film serving as an intermediate layer.
The surface of an emitter at the front side of the bottom cell adopts a tunneling silicon oxide/boron-doped polycrystalline silicon stacked structure or an intrinsic amorphous silicon/boron-doped amorphous silicon stacked structure.
The surface of the front emitter of the top cell adopts a surfactant passivation layer/hole transport layer stacking structure.
The n-type crystalline silicon TOPCon structure comprises any one of the following structures: the thin polysilicon film comprises a back metal electrode, hydrogenated silicon nitride, phosphorus-doped polysilicon, tunneling silicon oxide, n-type crystalline silicon, tunneling silicon oxide and boron-doped thin polysilicon which are arranged in sequence, or comprises the back metal electrode, the hydrogenated silicon nitride, the phosphorus-doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, intrinsic amorphous silicon and the boron-doped amorphous silicon which are arranged in sequence.
The perovskite battery comprises: the electron transport layer, the perovskite, the surfactant passivation layer, the hole transport layer, the antireflection layer and the positive metal electrode are sequentially arranged.
The invention relates to a preparation method of the solar cell, which comprises the steps of preparing an n-type crystalline silicon TOPCon structure on a substrate, depositing a layer of transparent conductive film on a front surface passivation layer of the n-type crystalline silicon TOPCon structure by adopting a magnetron sputtering method to serve as an intermediate layer for connecting a bottom cell and a top cell, and preparing a perovskite cell on the intermediate layer.
The n-type crystalline silicon TOPCon structure is prepared by the following steps:
step 1) preparing a crystalline silicon substrate of a bottom cell: n-type monocrystalline silicon is used as a substrate, after damage layer removal and cleaning, the substrate is placed in mixed solution of NaOH and isopropanol for texture surface making,
the concentration of the NaOH aqueous alkali is 1-3 percent, and the concentration of the isopropanol solution is 2-10 percent;
step 2) preparing a tunneling silicon oxide/boron-doped thin polycrystalline silicon stacked structure or an intrinsic amorphous silicon/boron-doped amorphous silicon stacked structure passivation layer on the front surface of the bottom cell;
a) depositing a layer of tunneling silicon oxide by a Low Pressure Chemical Vapor Deposition (LPCVD) method, depositing a layer of thin amorphous silicon by thermal decomposition of silane, annealing the boron-doped amorphous silicon at a high temperature to form polysilicon with a thickness of 10-50 nm, wherein the boron impurity concentration in the polysilicon layer is 5 multiplied by 1019～5×1020cm-3。
The boron doping comprises in-situ doping and ex-situ doping, wherein: in the in-situ doping, silane and borane are introduced in the process of depositing the thin amorphous silicon, only silane is introduced in the ex-situ doping process, and then boron doping is carried out by adopting high-temperature boron diffusion.
The deposition temperature of the tunneling silicon oxide is 550-650 ℃.
The deposition temperature of the thin polysilicon is 600-700 ℃.
And the high-temperature boron is diffused at the temperature of 800-1100 ℃.
b) Depositing a layer of intrinsic amorphous silicon by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, wherein the thickness of the amorphous silicon is 1-5 nm, then depositing a layer of boron-doped amorphous silicon by the PECVD method, wherein the doping source gas is borane or trimethylboron, the thickness of the doping source gas is 2-10 nm, and the boron impurity concentration is 1 multiplied by 1020 cm-3The above.
The deposition temperature of the intrinsic amorphous silicon is 100-300 ℃.
Step 3) preparing a TOPCon structure on the back surface of the bottom battery: after the back surface of the silicon wafer is etched, growing a layer of tunneling silicon oxide by adopting an LPCVD (low pressure chemical vapor deposition) method, and then depositing polysilicon with phosphorus doping, wherein the thickness of the tunneling silicon oxide is 0.5-2 nm, and the thickness of the polysilicon is50-200 nm, and the phosphorus doping concentration is more than 2 multiplied by 1019cm-3。
Step 4), preparing a passivation layer on the back surface of the bottom battery and a metal electrode: depositing a layer of hydrogenated silicon nitride with the thickness of 50-150 nm on the back surface of a silicon wafer by adopting a PECVD (plasma enhanced chemical vapor deposition) method, preparing a metal Ag grid line electrode by adopting metal slurry with a burn-through type on the hydrogenated silicon nitride and adopting a screen printing method, thereby obtaining a bottom layer battery.
The working pressure of magnetron sputtering of the intermediate layer is 0.1-1 Pa, the sputtering power is 0.2-2 kW, and the thickness of the intermediate layer is 5-20 nm.
The perovskite battery is prepared by the following steps:
step i) preparation of the top cell back surface electron transport layer: and spin-coating a solution in which a titanium dioxide or fullerene derivative material is dissolved on the surface of the intermediate layer, and curing at a high temperature to form an electron transport layer with the thickness of 20-80 nm.
Step ii) preparation of the perovskite substrate of the top cell: dissolving metal halide and organic halide in an organic solvent, stirring to obtain a perovskite precursor solution, spin-coating the perovskite precursor solution on an electron transport layer, and annealing to obtain a perovskite absorption layer with the thickness of 300-600 nm.
Step iii) preparation of top cell front surfactant passivation layer/hole transport layer stack structure: dissolving an anionic surfactant in an organic solvent to obtain an anionic surfactant solution, then spin-coating the anionic surfactant solution on the surface of the perovskite twice in vacuum equipment, and drying to form a surfactant passivation layer with the thickness of 1-5 nm; and (3) spin-coating a solution in which a nickel oxide or PEDOT (Poly ethylene glycol ether ketone) PSS material is dissolved on the surface of the surfactant passivation layer, and then carrying out heat treatment to solidify the solution to form a hole transport layer with the thickness of 20-80 nm.
The two-time spin coating refers to: 400-600 rpm low speed spin coating and 3000-5000 rpm high speed spin coating.
And drying the surfactant layer at 50-100 ℃.
The anionic surfactant solution is selected from sodium dodecyl benzene sulfonate, sodium alkyl sulfate or sodium alkyl aryl sulfonate.
And carrying out heat treatment on the hole transport layer at the temperature of not higher than 100 ℃.
Step iv) preparation of the transparent conductive layer and the metal electrode on the front surface of the top cell: a transparent conducting layer, namely an Indium Tin Oxide (ITO) film or an aluminum-doped zinc oxide (AZO) film, is deposited on the surface of the hole transport layer by adopting a magnetron sputtering method, and finally, a metal Ag grid line electrode is prepared by a screen printing method, so that a top layer battery is obtained.
Technical effects
The invention adopts TOPCon technology, heterojunction technology and perovskite surface passivation technology, and carries out interface passivation layer design on one end of the emitter of the bottom battery and one end of the emitter of the top battery, thereby improving the battery conversion efficiency and being compatible with the existing process technology of the production line. Aiming at the condition that photon-generated carriers are more accumulated at one end of an emitter near the surface of the battery, one end of the emitter of the bottom battery adopts a TOPCon structure which is selectively permeable to the carriers, wherein a doped polycrystalline silicon layer is thinner and has the thickness lower than 50nm, so that the excellent passivation characteristic can be ensured, more photon parasitic absorption loss can be avoided, and the TOPCon structure can be realized by an LPCVD method or a magnetron sputtering method; the amorphous silicon also has excellent passivation characteristics, the defect of high carrier recombination loss can be greatly improved by applying the amorphous silicon in a laminated cell, the thickness of the doped amorphous silicon layer is less than 10nm, and the amorphous silicon layer can be realized by a PECVD (plasma enhanced chemical vapor deposition) or Physical Vapor Deposition (PVD) method; the introduction of the surfactant layer between the top cell and the hole transport layer improves the carrier recombination loss at the emitter end of the perovskite layer, and the structure can be realized in a vacuum device by a spin coating method.
Drawings
Fig. 1 is a schematic structural diagram of a crystalline silicon/perovskite tandem solar cell in which the front surface of a crystalline silicon bottom cell is a tunneling silicon oxide/boron-doped polysilicon stack layer in example 1;
FIG. 2 is a schematic structural diagram of a crystalline silicon/perovskite tandem solar cell of which the front surface of a crystalline silicon bottom cell is an intrinsic amorphous silicon/boron-doped amorphous silicon tandem in example 2;
FIG. 3 is a schematic diagram of a conventional tandem solar cell without passivation stack and surfactant layers at the emitter end of the bottom and top cells;
in the figure: 1 hydrogenated silicon nitride, 2 phosphorus doped polysilicon, 3 tunneling silicon oxide, 4 n-type crystalline silicon substrate, 5 tunneling silicon oxide, 6 boron doped polysilicon, 7 intermediate layer, 8 electron transport layer, 9 perovskite absorption layer, 10 surfactant passivation layer, 11 hole transport layer, 12 transparent conductive layer, 13 and 14 positive Ag electrode and back Ag electrode, 15 intrinsic amorphous silicon, 16 boron doped amorphous silicon and 17 boron emitter respectively.
Detailed Description
Example 1
As shown in fig. 1, the present embodiment relates to a crystalline silicon/perovskite tandem solar cell having a hole selective passivation structure, which includes: the solar cell comprises a back metal electrode, hydrogenated silicon nitride, phosphorus-doped polycrystalline silicon, tunneling silicon oxide, n-type crystalline silicon, tunneling silicon oxide, boron-doped thin polycrystalline silicon, an intermediate layer, an electron transport layer, perovskite, a surfactant passivation layer, a hole transport layer, a transparent conductive layer and a positive metal electrode.
The solar cell in the embodiment is prepared by the following steps:
step one, a crystalline silicon substrate: selecting n-type monocrystalline silicon 4 as a bottom battery, removing a damage layer, cleaning, and putting into a mixed solution of NaOH and isopropanol for texturing, wherein the concentration of an NaOH alkaline solution is preferably 2%, and the concentration of an isopropanol solution is preferably 5%, and preparing the small pyramid textured surface.
Step two, passivating layer of front surface of bottom battery: growing a layer of tunneling silicon oxide 5 by an LPCVD method, depositing a layer of amorphous silicon by thermal decomposition of silane, annealing the boron-doped amorphous silicon at a high temperature to form polycrystalline silicon 6, wherein the boron doping comprises in-situ doping and ex-situ doping, the tunneling silicon oxide deposition temperature is preferably 600 ℃, the thickness is preferably 0.8nm, the thin polycrystalline silicon deposition temperature is preferably 630 ℃, the thickness is preferably 25nm, the boron diffusion temperature in the polycrystalline silicon layer is preferably 1000 ℃, and the boron impurity concentration is preferably 1 x 1020cm-3。
Step three, the back of the bottom batterySurface topocon structure: after the back of the silicon chip is etched, a layer of tunneling silicon oxide 3 grows by adopting an LPCVD method, and then polysilicon 2 with phosphorus doping is deposited, wherein the thickness of the tunneling silicon oxide is preferably 1nm, the thickness of the polysilicon is preferably 100nm, and the phosphorus doping concentration is 2 multiplied by 1020cm-3。
Step four, a passivation layer and a metal electrode on the back surface of the bottom battery: depositing a layer of hydrogenated silicon nitride 1 on the back surface of the silicon wafer by adopting a PECVD method, wherein the thickness is preferably 100 nm; the metal Ag grid line electrode 14 is prepared by a silk screen printing method by using metal slurry with a burn-through type on hydrogenated silicon nitride, so that a bottom layer battery is obtained.
Step five, intermediate layer: and depositing a layer of transparent conductive film 7 on the passivation layer on the front surface of the bottom cell by adopting a magnetron sputtering method to serve as an intermediate layer for connecting the bottom cell and the top cell, wherein the working pressure is preferably 0.7Pa, the sputtering power is preferably 1kW, and the thickness of the intermediate layer is 10 nm.
Step six, an electron transport layer on the back surface of the top battery: and spin-coating a titanium dioxide solution on the surface of the middle layer, and curing at high temperature to form an electron transport layer 8 with the thickness of 60 nm.
Step seven, the perovskite absorption layer of the top battery: dissolving metal halide and organic halide in an organic solvent, stirring to obtain a perovskite precursor solution, spin-coating the perovskite precursor solution on the electron transport layer, and annealing to obtain the perovskite absorption layer 9 with the thickness of 500 nm.
Step eight, pushing a surface active agent passivation layer in front of the battery: dissolving an anionic surfactant in an organic solvent to obtain an anionic surfactant solution, then spin-coating the anionic surfactant solution on the surface of perovskite in vacuum equipment, and drying to form a surfactant passivation layer, wherein the low-speed spin coating is performed firstly, the spin coating parameter is preferably 550rmp, then the high-speed spin coating is performed, the spin coating parameter is preferably 4500rmp, the drying temperature is preferably 75 ℃, and the thickness of the prepared surfactant passivation layer is preferably 2 nm;
step nine, a hole transport layer on the front surface of the top cell: and spin-coating a nickel oxide solution on the surface of the surfactant passivation layer, and then carrying out heat treatment to solidify the nickel oxide solution to form the hole transport layer, wherein the heat treatment temperature is preferably 80 ℃ and the thickness is preferably 70 nm.
Step ten, pushing the antireflection layer on the front surface of the battery and the metal electrode: depositing an ITO film on the surface of the hole transport layer by adopting a magnetron sputtering method, wherein the thickness is preferably 30 nm; and finally, preparing the metal Ag grid line electrode by a screen printing method, thereby obtaining the top layer battery.
Through specific practical experiments, under the standard specific environment setting, a bottom battery and a top battery are respectively tested, the front surface of the bottom battery adopts a tunneling silicon oxide/thin polysilicon stack structure, and compared with batteries with the thicknesses of 25nm and 80nm, the results show that the passivation performance of the bottom battery and the passivation performance of the thin polysilicon batteries are consistent, but the short-circuit current of the battery with the thin polysilicon is 4-5 mA/cm higher2The corresponding bottom cell conversion efficiency is improved by more than 2% (absolute value), and the open circuit voltage of the cell with the stacked passivation layer is higher than that of the cell without the stacked passivation layer. Comparing whether a surfactant passivation layer is adopted or not by the front surface of the top battery, and comparing whether the applied voltage is positive scanning or negative scanning, the open-circuit voltage, the short-circuit current and the filling factor of the perovskite battery with the surfactant are respectively 0.06V and 1.8mA/cm higher than those of the reference battery2And 5% or more, the corresponding conversion efficiency of the top cell can be improved by 3.8% or more (absolute value).
Compared with the prior art, the battery obtained by the embodiment has the advantages of more excellent interface passivation property, higher open-circuit voltage, higher carrier collection efficiency due to lower parasitic absorption and higher corresponding short-circuit current.
Example 2
As shown in fig. 2, in comparison with example 1, the tunnel oxide and the boron-doped thin polysilicon of the solar cell of the present embodiment located under the intermediate layer are replaced with intrinsic amorphous silicon and boron-doped amorphous silicon.
The solar cell in the embodiment is prepared by the following steps:
step one, a crystalline silicon substrate: selecting n-type monocrystalline silicon 4 as a bottom battery, removing a damage layer, cleaning, and putting into a mixed solution of NaOH and isopropanol for texturing, wherein the concentration of an NaOH alkaline solution is preferably 2%, and the concentration of an isopropanol solution is preferably 5%, and preparing the small pyramid textured surface.
Step two, passivating layer of front surface of bottom battery: depositing a layer of intrinsic amorphous silicon 15 with a thickness of 2nm and a deposition temperature of 200 ℃ by PECVD method, and depositing a layer of boron-doped amorphous silicon 16 with a thickness of 5nm and a boron impurity concentration of 2 x 1020cm-3。
Step three, a TOPCon structure of the back surface of the bottom battery: after the back of the silicon chip is etched, a layer of tunneling silicon oxide 3 grows by adopting an LPCVD method, and then polysilicon 2 with phosphorus doping is deposited, wherein the thickness of the tunneling silicon oxide is preferably 1nm, the thickness of the polysilicon is preferably 100nm, and the phosphorus doping concentration is 2 multiplied by 1020cm-3。
Step four, a passivation layer and a metal electrode on the back surface of the bottom battery: depositing a layer of hydrogenated silicon nitride 1 on the back surface of the silicon wafer by adopting a PECVD method, wherein the thickness is preferably 100 nm; the metal Ag grid line electrode 14 is prepared by a silk screen printing method by using metal slurry with a burn-through type on hydrogenated silicon nitride, so that a bottom layer battery is obtained.
Step five, intermediate layer: and depositing a layer of transparent conductive film 7 on the passivation layer on the front surface of the bottom cell by adopting a magnetron sputtering method to serve as an intermediate layer for connecting the bottom cell and the top cell, wherein the working pressure is preferably 0.7Pa, the sputtering power is preferably 1kW, and the thickness of the intermediate layer is 10 nm.
Step six, an electron transport layer on the back surface of the top battery: and spin-coating a solution dissolved with a fullerene derivative material on the surface of the intermediate layer, and curing at high temperature to form an electron transport layer 8 with the thickness of 50 nm.
Step seven, the perovskite absorption layer of the top battery: dissolving metal halide and organic halide in an organic solvent, stirring to obtain a perovskite precursor solution, spin-coating the perovskite precursor solution on the electron transport layer, and annealing to obtain the perovskite absorption layer 9 with the thickness of 500 nm.
Step eight, pushing a surface active agent passivation layer in front of the battery: dissolving an anionic surfactant in an organic solvent to obtain an anionic surfactant solution, then spin-coating the anionic surfactant solution on the surface of perovskite in vacuum equipment, and drying to form a surfactant passivation layer, wherein the thickness is preferably 2 nm;
step nine, a hole transport layer on the front surface of the top cell: and spin-coating a PEDOT (Poly ethylene glycol ether ketone) PSS solution on the surface of the surfactant passivation layer, and carrying out heat treatment to solidify the solution to form a hole transport layer, wherein the thickness is preferably 60 nm.
Step ten, pushing the antireflection layer on the front surface of the battery and the metal electrode: depositing an AZO film on the surface of the hole transport layer by adopting a magnetron sputtering method, wherein the thickness is preferably 20 nm; and finally, preparing the metal Ag grid line electrode by a screen printing method, thereby obtaining the top layer battery.
Through specific practical experiments, under the standard specific environment setting, a bottom battery and a top battery are respectively tested, and the front surface of the bottom battery adopts an intrinsic amorphous silicon/boron-doped amorphous silicon stacking structure, so that the result shows that when the thickness of the boron-doped amorphous silicon is changed from 1nm to 10nm, and the thickness of the amorphous silicon is increased from 1nm to 5nm, the open-circuit voltage and the filling factor of the battery are both improved, but when the thickness of the amorphous silicon is increased from 5nm to 10nm, the open-circuit voltage and the filling factor of the battery are both stable and unchanged; because the amorphous silicon layer has parasitic absorption to incident photons, the short-circuit current of the cell is reduced along with the increase of the thickness of the amorphous silicon, and the short-circuit current density is reduced by 0.13mA/cm for every 1nm of the thickness2The bottom cell conversion efficiency is optimal when the boron doped amorphous silicon thickness is 5 nm. The top cell also has the advantage of various electrical parameters.
Compared with the prior art, the optimized structural parameters obtained by the embodiment enable the battery to have higher open-circuit voltage and fill factor, so that the battery has higher conversion efficiency.
The foregoing embodiments may be modified in many different ways by those skilled in the art without departing from the spirit and scope of the invention, which is defined by the appended claims and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (8)

1. A crystalline silicon/perovskite tandem solar cell with a hole selective passivation structure, comprising: an n-type crystalline silicon TOPCon structure as a bottom cell, a perovskite structure as a top cell and a transparent conductive film as an intermediate layer;
the n-type crystalline silicon TOPCon structure comprises any one of the following structures: the thin polysilicon film comprises a back metal electrode, hydrogenated silicon nitride, phosphorus-doped polysilicon, tunneling silicon oxide, n-type crystalline silicon, tunneling silicon oxide and boron-doped thin polysilicon which are arranged in sequence, or comprises the back metal electrode, the hydrogenated silicon nitride, the phosphorus-doped polysilicon, the tunneling silicon oxide, the n-type crystalline silicon, intrinsic amorphous silicon and the boron-doped amorphous silicon which are arranged in sequence.
2. The crystalline silicon/perovskite laminated solar cell with the hole selective passivation structure as claimed in claim 1, wherein a tunneling silicon oxide/boron doped polysilicon stack structure or an intrinsic amorphous silicon/boron doped amorphous silicon stack structure is adopted on the surface of the front side emitter of the bottom cell.
3. The crystalline silicon/perovskite tandem solar cell with the hole selective passivation structure as claimed in claim 1, wherein the front emitter surface of the top cell adopts a surfactant passivation layer/hole transport layer stack structure.
4. A crystalline silicon/perovskite tandem solar cell with a hole selective passivation structure according to claim 1, characterized in that the perovskite cell comprises: the electron transport layer, the perovskite, the surfactant passivation layer, the hole transport layer, the antireflection layer and the positive metal electrode are sequentially arranged.
5. A preparation method for preparing the solar cell as claimed in any one of claims 1 to 4, characterized in that an n-type crystalline silicon TOPCon structure is prepared on a substrate, a transparent conductive film is deposited on a passivation layer on the front surface of the n-type crystalline silicon TOPCon structure by adopting a magnetron sputtering method to serve as an intermediate layer for connecting a bottom cell and a top cell, and a perovskite cell is prepared on the intermediate layer.
6. The method as claimed in claim 5, wherein the TOPCon structure of n-type crystalline silicon is prepared by the following steps:
step 1) preparing a crystalline silicon substrate of a bottom cell: n-type monocrystalline silicon is used as a substrate, after damage layer removal and cleaning, the substrate is placed in mixed solution of NaOH and isopropanol for texture surface making,
step 2) preparing a tunneling silicon oxide/boron-doped thin polycrystalline silicon stacked structure or an intrinsic amorphous silicon/boron-doped amorphous silicon stacked structure passivation layer on the front surface of the bottom cell;
a) depositing a layer of tunneling silicon oxide by an LPCVD method, depositing a layer of thin amorphous silicon by thermal decomposition of silane, forming polycrystalline silicon with the thickness of 10-50 nm by high-temperature annealing of boron-doped amorphous silicon, wherein the concentration of boron impurities in the polycrystalline silicon layer is 5 multiplied by 1019～5×1020cm-3；
b) Depositing a layer of intrinsic amorphous silicon by a PECVD method, wherein the thickness of the amorphous silicon is 1-5 nm, and then depositing a layer of boron-doped amorphous silicon by the PECVD method, wherein a doping source gas is borane or trimethylboron, the thickness of the doping source gas is 2-10 nm, and the concentration of boron impurities is 1 multiplied by 1020cm-3The above;
step 3) preparing a TOPCon structure on the back surface of the bottom battery: after the back of the silicon chip is etched, a layer of tunneling silicon oxide is grown by adopting an LPCVD method, and then polysilicon with phosphorus doping is deposited, wherein the thickness of the tunneling silicon oxide is 0.5-2 nm, the thickness of the polysilicon is 50-200 nm, and the phosphorus doping concentration is more than 2 multiplied by 1019cm-3；
Step 4), preparing a passivation layer on the back surface of the bottom battery and a metal electrode: depositing a layer of hydrogenated silicon nitride with the thickness of 50-150 nm on the back surface of a silicon wafer by adopting a PECVD (plasma enhanced chemical vapor deposition) method, preparing a metal Ag grid line electrode by adopting metal slurry with a burn-through type on the hydrogenated silicon nitride and adopting a screen printing method, thereby obtaining a bottom layer battery.
7. The method according to claim 5, wherein the perovskite battery is prepared by the following steps:
step i) preparation of the top cell back surface electron transport layer: spin-coating a solution in which a titanium dioxide or fullerene derivative material is dissolved on the surface of the intermediate layer, and curing at a high temperature to form an electron transport layer with the thickness of 20-80 nm;
step ii) preparation of the perovskite substrate of the top cell: dissolving metal halide and organic halide in an organic solvent, stirring to obtain a perovskite precursor solution, spin-coating the perovskite precursor solution on an electron transport layer, and annealing to obtain a perovskite absorption layer with the thickness of 300-600 nm;
step iii) preparation of top cell front surfactant passivation layer/hole transport layer stack structure: dissolving an anionic surfactant in an organic solvent to obtain an anionic surfactant solution, then spin-coating the anionic surfactant solution on the surface of the perovskite twice in vacuum equipment, and drying to form a surfactant passivation layer with the thickness of 1-5 nm; spin-coating a solution in which a nickel oxide or PEDOT (Poly ethylene glycol ether ketone) PSS material is dissolved on the surface of the surfactant passivation layer, and curing the solution under a high-temperature annealing condition to form a hole transport layer with the thickness of 20-80 nm;
step iv) preparation of the transparent conductive layer and the metal electrode on the front surface of the top cell: and depositing a transparent conductive layer, namely an indium tin oxide film or an aluminum-doped zinc oxide film, on the surface of the hole transport layer by adopting a magnetron sputtering method, and finally preparing a metal Ag grid line electrode by adopting a screen printing method so as to obtain the top layer battery.
8. The method of claim 7, wherein the two-time spin coating comprises: 400-600 rpm low speed spin coating and 3000-5000 rpm high speed spin coating.
CN202110973198.1A 2021-08-24 2021-08-24 Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure Active CN113707734B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110973198.1A CN113707734B (en) 2021-08-24 2021-08-24 Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110973198.1A CN113707734B (en) 2021-08-24 2021-08-24 Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure

Publications (2)

Publication Number Publication Date
CN113707734A true CN113707734A (en) 2021-11-26
CN113707734B CN113707734B (en) 2024-04-26

Family

ID=78654296

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110973198.1A Active CN113707734B (en) 2021-08-24 2021-08-24 Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure

Country Status (1)

Country Link
CN (1) CN113707734B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114792704A (en) * 2022-03-29 2022-07-26 宣城先进光伏技术有限公司 Perovskite/silicon heterojunction laminated solar cell and preparation method thereof
CN115000189A (en) * 2022-05-30 2022-09-02 西安隆基乐叶光伏科技有限公司 Back contact solar cell and preparation method thereof
CN115050843A (en) * 2022-05-06 2022-09-13 中国科学院宁波材料技术与工程研究所 Tunneling oxide layer passivation contact battery back structure and preparation method and application thereof
CN117253927A (en) * 2023-11-14 2023-12-19 无锡华晟光伏科技有限公司 Solar laminated cell and preparation method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107369767A (en) * 2017-07-20 2017-11-21 南开大学 A kind of perovskite/silicon heterogenous both ends stacked solar cell, cascade solar cell
CN110518127A (en) * 2019-08-16 2019-11-29 上海交通大学 A kind of perovskite solar battery and preparation method based on surfactant passivation
CN111244278A (en) * 2018-11-29 2020-06-05 中国科学院大连化学物理研究所 Non-doped crystalline silicon heterojunction perovskite laminated solar cell structure and preparation method
CN111628050A (en) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 Method for realizing electronic local passivation contact, crystalline silicon solar cell and preparation method thereof
CN111628049A (en) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 Method for realizing local hole passivation contact, crystalline silicon solar cell and preparation method thereof
CN113013277A (en) * 2021-04-25 2021-06-22 天合光能股份有限公司 Laminated solar cell and preparation method thereof
CN113206123A (en) * 2021-04-22 2021-08-03 南京大学 Perovskite/crystalline silicon laminated cell and preparation method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107369767A (en) * 2017-07-20 2017-11-21 南开大学 A kind of perovskite/silicon heterogenous both ends stacked solar cell, cascade solar cell
CN111244278A (en) * 2018-11-29 2020-06-05 中国科学院大连化学物理研究所 Non-doped crystalline silicon heterojunction perovskite laminated solar cell structure and preparation method
CN110518127A (en) * 2019-08-16 2019-11-29 上海交通大学 A kind of perovskite solar battery and preparation method based on surfactant passivation
CN111628050A (en) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 Method for realizing electronic local passivation contact, crystalline silicon solar cell and preparation method thereof
CN111628049A (en) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 Method for realizing local hole passivation contact, crystalline silicon solar cell and preparation method thereof
CN113206123A (en) * 2021-04-22 2021-08-03 南京大学 Perovskite/crystalline silicon laminated cell and preparation method thereof
CN113013277A (en) * 2021-04-25 2021-06-22 天合光能股份有限公司 Laminated solar cell and preparation method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114792704A (en) * 2022-03-29 2022-07-26 宣城先进光伏技术有限公司 Perovskite/silicon heterojunction laminated solar cell and preparation method thereof
CN114792704B (en) * 2022-03-29 2023-04-07 宣城先进光伏技术有限公司 Perovskite/silicon heterojunction laminated solar cell and preparation method thereof
CN115050843A (en) * 2022-05-06 2022-09-13 中国科学院宁波材料技术与工程研究所 Tunneling oxide layer passivation contact battery back structure and preparation method and application thereof
CN115000189A (en) * 2022-05-30 2022-09-02 西安隆基乐叶光伏科技有限公司 Back contact solar cell and preparation method thereof
CN115000189B (en) * 2022-05-30 2023-12-05 西安隆基乐叶光伏科技有限公司 Back contact solar cell and preparation method thereof
CN117253927A (en) * 2023-11-14 2023-12-19 无锡华晟光伏科技有限公司 Solar laminated cell and preparation method thereof

Also Published As

Publication number Publication date
CN113707734B (en) 2024-04-26

Similar Documents

Publication Publication Date Title
CN113707734B (en) Crystalline silicon/perovskite laminated solar cell with hole selective passivation structure
CN110707159A (en) P-type crystalline silicon solar cell with front surface and back surface in full-area contact passivation and preparation method thereof
CN114975691A (en) Passivated contact solar cell with selective emitter and preparation method, assembly and system thereof
TW201547044A (en) Conductive polymer/Si interfaces at the backside of solar cells
CN114256387B (en) Preparation method of perovskite-heterojunction three-terminal MWT structure laminated solar cell
CN113644142A (en) Solar cell with passivation contact and preparation method thereof
CN217881546U (en) Passivated contact solar cells with selective emitters and assemblies and systems
CN113206123A (en) Perovskite/crystalline silicon laminated cell and preparation method thereof
CN113013277A (en) Laminated solar cell and preparation method thereof
KR100990864B1 (en) Solar cell and method for manufacturing the same
CN115458612A (en) Solar cell and preparation method thereof
WO2024060933A1 (en) Solar cell and manufacturing method therefor
CN211238272U (en) Crystalline silicon/amorphous silicon heterojunction battery
CN116130558B (en) Preparation method of novel all-back electrode passivation contact battery and product thereof
CN111564505A (en) Heterojunction solar cell with passivated double intrinsic layers and preparation method thereof
CN115172602B (en) Doped metal oxide composite layer structure
CN114188429B (en) Homogeneous heterojunction battery with tunneling tunnel junction and preparation method thereof
CN214753765U (en) Perovskite tandem solar cell
CN212323018U (en) Laminated battery structure
CN211654834U (en) High-efficiency P-type crystalline silicon solar cell
CN114520288A (en) Preparation method of crystalline silicoperovskite laminated solar cell
CN113066874A (en) Heterojunction solar cell and preparation method thereof
CN113130702A (en) Back contact type solar cell and preparation method thereof
CN111430475A (en) Efficient P-type crystalline silicon solar cell and preparation method thereof
CN220604704U (en) Double-sided doped polycrystalline silicon passivation contact battery

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant