CN217280794U

CN217280794U - Photovoltaic cell

Info

Publication number: CN217280794U
Application number: CN202220415189.0U
Authority: CN
Inventors: 魏科胜; 薛建峰; 徐磊; 王金; 王永洁; 余义; 苏世杰
Original assignee: Tongwei Solar Anhui Co Ltd
Current assignee: Tongwei Solar Anhui Co Ltd
Priority date: 2022-02-25
Filing date: 2022-02-25
Publication date: 2022-08-23
Anticipated expiration: 2032-02-25

Abstract

The embodiment of the application provides a photovoltaic cell, and relates to the field of solar cells. The photovoltaic cell comprises a silicon wafer, wherein a passivation layer, a TCO layer and a copper layer are sequentially stacked on the front surface of the silicon wafer, the passivation layer, the TCO layer and the copper layer are also sequentially stacked on the back surface of the silicon wafer, and a copper grid line is arranged on the surface, away from the TCO layer, of each copper layer. The copper layer can be used as the substrate of the copper grid line, and compared with a battery printed with silver paste, the manufacturing cost of the photovoltaic battery in the embodiment of the application is greatly reduced, the energy conversion efficiency of the battery cannot be excessively influenced, and the large-scale production of the photovoltaic battery is facilitated.

Description

Photovoltaic cell

Technical Field

The application relates to the field of solar cells, in particular to a photovoltaic cell.

Background

The solar cell can convert light energy into electric energy, has the advantages of low carbon and environmental protection, and has wide application prospect.

However, at present, when the solar cell is prepared, silver paste is required to be used for printing the grid line, so that the manufacturing cost is high, and further development of the solar cell is restricted.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a photovoltaic cell, which can reduce the manufacturing cost of the photovoltaic cell and is beneficial to large-scale production of the photovoltaic cell.

The embodiment of the application provides a photovoltaic cell, which comprises a silicon wafer, wherein a passivation layer, a TCO layer and a copper layer are sequentially stacked on the front side of the silicon wafer, the passivation layer, the TCO layer and the copper layer are also sequentially stacked on the back side of the silicon wafer, and a copper grid line is arranged on the surface, away from the TCO layer, of each copper layer.

In the implementation process, the outermost layer of the photovoltaic cell is a copper layer, the resistance of copper is slightly larger than that of silver, but the manufacturing cost of copper is far lower than that of silver, and the copper is used as a grid line, so that the preparation cost of the photovoltaic cell can be greatly reduced, the large-scale production of the photovoltaic cell is facilitated, and the efficiency of the produced photovoltaic cell is hardly influenced; the copper layer can provide a substrate for laying or growing the copper grid line and can also protect other layer structures from being damaged.

The TCO layer is a transparent oxide (transparent conductive oxide) layer, has high light transmittance and low resistivity, and does not hinder the light absorption efficiency of the photovoltaic cell or increase the internal resistance of the cell when used for preparing the photovoltaic cell. In addition, the TCO layer can also play a certain protection role on the passivation layer. The passivation layer can play a role in protecting the silicon wafer and ensure that a subsequently manufactured battery has higher open-circuit voltage, so that the energy conversion efficiency of the battery is improved; and an electrode can be arranged on the passivation layer to ensure that the current on the battery can be output to the outside. The silicon wafer can generate current carriers after being irradiated by sunlight, and the current carriers can ensure that the photovoltaic cell generates current after being manufactured into a cell.

In one possible implementation, the thickness of each copper layer is 150-250 nm.

In the above implementation process, because the light transmittance of the copper layer is poor, the thickness of the copper layer is preferably not more than 250nm, which would affect the efficiency of the battery; the copper layer also needs to serve as a protective layer for the other layers, and its thickness should not be too small, preferably not less than 150 nm.

In one possible implementation, the thickness of the copper layer is 180-220 nm.

In the realization process, the thickness of the copper layer is 200nm, so that the light transmission and the protection can be simultaneously considered.

In one possible implementation mode, the thickness of each silicon wafer is 100-200 μm.

In the implementation process, the silicon wafer is too thick, so that the transmission of current carriers is greatly hindered, the current carriers are not easy to diffuse, the silicon wafer is too thin, the quantity of the generated current carriers is small, and the efficiency of the battery manufactured by the silicon wafer is not high.

In one possible implementation, the thickness of the TCO layer is 80-140 nm.

In the implementation process, too thick TCO layer can reduce the transmittance of sunlight and the conversion efficiency of the cell, and too thin TCO layer can reduce the electrical performance of the photovoltaic cell and has adverse effect on the performance of the photovoltaic cell.

In a possible implementation manner, the material of the passivation layer is amorphous silicon, and the thickness of the passivation layer is 10-20 nm.

In the implementation process, the amorphous silicon is used as a material of the passivation layer, so that the silicon wafer is protected, the function of an electrode is achieved, and carriers are collected conveniently; moreover, the thickness of the passivation layer cannot be too large or too small, so that the contact performance with the TCO is poor when the thickness is too large, and the passivation effect is poor when the thickness is too small.

In one possible implementation manner, each passivation layer comprises a p-type amorphous silicon layer and an i-type amorphous silicon layer which are arranged in a stacked mode, and the i-type amorphous silicon layer is arranged on the surface of the silicon wafer in an overlapped mode.

In the implementation process, the p-type amorphous silicon layer can provide electrodes for the photovoltaic cell and plays a role in outwards conveying current, and the i-type amorphous silicon layer can play a role in protecting a silicon wafer and improving the open-circuit voltage of the solar cell.

In a possible implementation manner, the thickness of the p-type amorphous silicon layer is 5-15 nm.

In the implementation process, the p-type amorphous silicon layer has an excessively large thickness, so that the light transmittance is reduced, and an excessively small thickness affects the electric field inside the battery, so that the battery performance is deteriorated, and therefore, the thickness of the p-type amorphous silicon layer needs to be kept within a range of 5-15 nm.

In one possible implementation mode, the i-type amorphous silicon layer is 5-10 nm.

In the implementation process, the passivation effect cannot be achieved when the thickness of the i-type amorphous silicon layer is too large or too small, so that the thickness of the i-type amorphous silicon layer needs to be kept within the range of 5-10 nm.

In one possible implementation manner, the width of the copper grid lines is 20-60 μm, and the number of the copper grid lines on the surface of each copper layer is 50-150.

In the implementation process, the width of the copper grid line cannot be too small, otherwise, the internal resistance of the photovoltaic cell can be increased, the width of the copper grid line cannot be too large, and otherwise, the light absorption efficiency of the photovoltaic cell can be influenced; and too much copper grid line's quantity can influence photovoltaic cell's extinction efficiency equally, and the quantity can not fully collect the carrier too little.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a photovoltaic cell provided in an embodiment of the present application.

Icon: 001-photovoltaic cell; 100-a silicon wafer; 200-a passivation layer; 210-i type amorphous silicon layer; 220-p type amorphous silicon layer; 300-TCO layer; 400-a copper layer; 410-copper grid lines.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it should be noted that the terms "upper", "lower", and the like refer to orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, are only used for convenience of description and simplification of description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

First embodiment

Referring to fig. 1, a photovoltaic cell 001 according to the present embodiment includes a silicon wafer 100, the silicon wafer 100 generates carriers after being irradiated by sunlight, the carriers generate current after being processed into a cell on the photovoltaic cell 001, a passivation layer 200, a TCO layer 300, and a copper layer 400 are respectively stacked on the front and back surfaces of the silicon wafer 100, a copper grid line 410 is disposed on a surface of the copper layer 400 away from the TCO layer 300, and the copper grid line 410 is used for collecting current generated on the photovoltaic cell 001.

The photovoltaic cell 001 in the embodiment of the present application has a symmetrical structure with respect to the silicon wafer 100, and the same layer structures are provided on the front and back surfaces of the silicon wafer 100, and the thickness and the area of the layer structures are the same, so that the photovoltaic cell 001 can be conveniently prepared. Of course, in other embodiments, the thickness and area of the layer structure with the same front and back surfaces may be different.

The copper grid lines 410 on the surface of the copper layer 400 away from the TCO layer 300 can be used to collect the current generated by the photovoltaic cell 001, and the number and width of the copper grid lines 410 are required to be not too large or too small. Too many and too wide copper grid lines 410 can block sunlight and affect the light absorption efficiency of the photovoltaic cell 001, too small copper grid lines 410 can increase the internal resistance of the photovoltaic cell 001, and too few copper grid lines 410 cannot sufficiently collect generated carriers and can affect the conversion efficiency of the cell; the width of the copper grid line 410 is generally required to be controlled within a range of 20-60 μm, which may be 20 μm, 30 μm, 40 μm, 50 μm or 60 μm; meanwhile, the number of the copper grid lines 410 on the surface of each copper layer 400 also needs to be controlled within a range of 50 to 150, which may be 50, 100, 130 or 150. In this embodiment, the width of each copper gate line 410 is 40 μm and the number of the copper gate lines is 130 on the surface of each copper layer 400.

The copper layer 400 can provide a substrate for the copper gate lines 410 and can also function to protect other layer structures; however, since copper has poor light transmittance, the thickness of the copper layer 400 needs to be controlled within a reasonable range. If the thickness is too large, the light transmittance is reduced, which affects the light absorption efficiency of the photovoltaic cell 001, and if the thickness is too small, the protection effect cannot be achieved well, and the thickness of the copper layer 400 is generally controlled within a range of 150 to 250nm, and more specifically, may be 180 to 220 nm. For example, the thickness of the copper layer 400 may be 160nm, 180nm, 200nm, 220nm, 240 nm. Illustratively, the thickness of the copper layer 400 in this embodiment is 200 nm.

The TCO layer 300 may protect the passivation layer 200 to a certain extent, and the TCO layer 300 needs to have good light transmittance and low resistivity, so as not to hinder the light absorption efficiency of the photovoltaic cell, and not to increase the internal resistance of the cell, and the TCO layer may be made of ITO (Indium tin oxide), SnO (Indium tin oxide), or the like ₂ : f (fluorine doped tin oxide), and the like. In this embodiment, the TCO layer 300 is made of ITO, for example. The thickness of TCO layer 300 cannot be too thick, otherwise light transmittance may be reduced, affecting cell efficiency; nor too thin, which would otherwise degrade the electrical performance of the cell; the thickness of the TCO layer 300 is generally in the range of 80-140 nm, for example, 80nm, 90nm, 100nm, 110nm, 120nm, 140 nm. By way of illustration, TCO layer 300 in this embodiment has a thickness of 110 nm.

The passivation layer 200 can protect the silicon wafer 100 to ensure that the battery has a high open-circuit voltage, and an electrode is required to be disposed to collect carriers to ensure that electrons generated from the battery can be output to the outside of the battery. Therefore, the passivation layer 200 is usually made of amorphous silicon. Since too thick passivation layer 200 may result in poor contact performance with TCO and too thin passivation layer may result in poor passivation effect, the thickness of passivation layer 200 is generally 10-20 nm, for example, 10nm, 12nm, 15nm, 18nm, or 20 nm. Illustratively, in this embodiment, the thickness of the passivation layer 200 is 20 nm.

It should be noted that, in the present embodiment, the material of the "passivation layer 200 is amorphous silicon" is not necessarily a simple silicon substance, and other elements may be doped according to actual needs. Illustratively, the passivation layer 200 in this embodiment includes a p-type amorphous silicon layer 220 and an i-type amorphous silicon layer 210, which are stacked, and the i-type amorphous silicon layer 210 is formed by hydrogenating amorphous silicon and can protect the silicon wafer, so that it is closer to the silicon wafer 100; the p-type amorphous silicon layer 220 is formed by doping amorphous silicon with phosphorus, and can provide an electrode for a photovoltaic cell, so as to play a role in current transportation, and is closer to the TCO layer 300. The thickness of the p-type amorphous silicon layer 220 is generally 5-15 nm, and can be 5nm, 7nm, 10nm, 13nm or 15 nm; the thickness of the i-type amorphous silicon layer 210 is generally 5 to 10nm, and may be 5nm, 6nm, 8nm or 10 nm. Illustratively, in the present embodiment, the p-type amorphous silicon layer 220 has a thickness of 10nm, and the i-type amorphous silicon layer 210 has a thickness of 10 nm.

The material of the silicon wafer 100 is generally crystalline silicon, which can improve the energy conversion efficiency of the cell as much as possible. Since crystalline silicon as a semiconductor generates carriers after being irradiated with sunlight, the thickness of the silicon wafer 100 is also kept within a certain range, generally 100 to 200 μm; for example, it may be 100 μm, 130 μm, 160 μm, 180 μm or 200 μm. If the silicon wafer 100 is too thick, the transmission of carriers is greatly hindered, so that the carriers are not easy to diffuse, and if the silicon wafer is too thin, the number of the generated carriers is small, and the efficiency of the battery is not high. By way of illustration, the thickness of the silicon wafer in this embodiment is 180 μm.

The photovoltaic cell 001 in this example can be prepared by the following method:

firstly, using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method to deposit crystalline silicon with the thickness of 180 mu m to be used as a substrate of the photovoltaic cell 001;

then, simultaneously depositing amorphous silicon with the thickness of 10nm on the front surface and the back surface of the crystalline silicon substrate and passivating to obtain an i-type amorphous silicon layer 210;

then, depositing amorphous silicon with the thickness of 10nm on the surfaces of the two i-type amorphous silicon layers 210 respectively, and then introducing phosphorus oxychloride to obtain a p-type amorphous silicon layer 220;

using ITO as a raw material, and respectively plating a TCO layer 300 with the thickness of 110nm on the surfaces of the two p-type amorphous silicon layers 220 by using a magnetron sputtering method;

respectively plating a copper layer 400 with the thickness of 200nm on the surfaces of the two TCO layers 300 by using a magnetron sputtering method, and continuously cooling the TCO layers 300 during copper plating on the surfaces of the TCO layers 300 to ensure that the temperature of the surfaces of the TCO layers 300 is not higher than 300 ℃;

copper grid lines 410 with the width of 40 μm are respectively formed on the surfaces of the two copper layers 400 by screen printing or electroplating, and the number of the copper grid lines 410 on each surface of the copper layer 400 is 130.

The photovoltaic cell 001 manufactured by the method sequentially comprises, from top to bottom, 200 nm-thick copper layers 400, 110 nm-thick TCO layers 300 made of ITO, 10 nm-thick p-type amorphous silicon layers 220, 10 nm-thick i-type amorphous silicon layers 210, 180 μm-thick crystalline silicon wafers 100, 10 nm-thick i-type amorphous silicon layers 210, 10 nm-thick p-type amorphous silicon layers 220, 110 nm-thick TCO layers 300 made of ITO and 200 nm-thick copper layers 400, and 130 copper grid lines 410 with the width of 40 μm are arranged on the surfaces, away from the TCO layers 300, of the copper layers 400.

The photovoltaic performance of the photovoltaic cell in the first embodiment and the photovoltaic cell in the comparative example (the grid line is a silver grid line, and does not contain a copper layer, and the rest of the structure is the same as that of the photovoltaic cell in the first embodiment) were respectively tested, and the test results are as follows:

table 1 photovoltaic performance parameters of the photovoltaic cells of the first example and the comparative example

Group of	Eta	Voc	Isc	FF	Rs
						First embodiment	100.04％	99.91％	100.11％	100.03％	105.17％
Comparative example	100％	100％	100％	100％	100％

The electrical properties of the photovoltaic cell in the first embodiment were measured using the comparative example as a standard, and it can be seen from table 1 that the grid line of the photovoltaic cell in this embodiment uses copper as a raw material, which hardly affects the conversion efficiency of the cell; and the preparation cost of the battery can be reduced by using a copper layer and a copper grid line.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. The photovoltaic cell is characterized by comprising a silicon wafer, wherein a passivation layer, a TCO layer and a copper layer are sequentially stacked on the front side of the silicon wafer, the passivation layer, the TCO layer and the copper layer are also sequentially stacked on the back side of the silicon wafer, and a copper grid line is arranged on the surface, away from the TCO layer, of each copper layer.

2. The photovoltaic cell of claim 1, wherein each of the copper layers has a thickness of 150 to 250 nm.

3. The photovoltaic cell of claim 2, wherein the copper layer has a thickness of 180 to 220 nm.

4. The photovoltaic cell of claim 1, wherein each of the silicon wafers has a thickness of 100 to 200 μm.

5. The photovoltaic cell of claim 1, wherein each TCO layer has a thickness of 80-140 nm.

6. The photovoltaic cell according to claim 1, wherein the passivation layer is made of amorphous silicon and has a thickness of 10-20 nm.

7. The photovoltaic cell of claim 6, wherein each passivation layer comprises a p-type amorphous silicon layer and an i-type amorphous silicon layer which are stacked, and the i-type amorphous silicon layer is stacked on the surface of the silicon wafer.

8. The photovoltaic cell of claim 7, wherein the p-type amorphous silicon layer has a thickness of 5 to 15 nm.

9. The photovoltaic cell of claim 8, wherein the i-type amorphous silicon layer is 5-10 nm.

10. The photovoltaic cell of claim 1, wherein the width of the copper grid line is 20-60 μm; and/or the number of the copper grid lines on the surface of each copper layer is 50-150.