CN110957388A - Crystalline silicon/amorphous silicon heterojunction battery and preparation method thereof - Google Patents
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- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 136
- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 55
- 238000002360 preparation method Methods 0.000 title claims description 10
- 239000010408 film Substances 0.000 claims abstract description 86
- 239000010409 thin film Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims description 62
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 31
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 229910052709 silver Inorganic materials 0.000 claims description 14
- 239000004332 silver Substances 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 238000005245 sintering Methods 0.000 claims description 11
- 238000007650 screen-printing Methods 0.000 claims description 9
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 6
- 239000012670 alkaline solution Substances 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 9
- 238000011049 filling Methods 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 2
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- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
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- 238000002834 transmittance Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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Abstract
The invention discloses a crystalline silicon/amorphous silicon heterojunction battery, comprising: the substrate is a crystal silicon wafer; the i-type intrinsic amorphous silicon thin film, the P-type amorphous silicon thin film and the multilayer TCO thin film are sequentially grown on the front surface of the substrate; an i-type intrinsic amorphous silicon thin film, an N-type amorphous silicon thin film and a multilayer TCO thin film are sequentially grown on the back of the substrate; and a metal electrode disposed on the TCO film. The battery is made into a plurality of TCO films, so that the whole passivation effect is further greatly enhanced, the minority carrier lifetime key parameter is greatly improved, the purposes of improving open-circuit voltage, short-circuit current and filling factor can be achieved, and the efficiency of the HJT battery is greatly improved.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a crystalline silicon/amorphous silicon heterojunction cell and a preparation method thereof.
Background
Heterojunction (HJT) refers to a junction composed of two different semiconductor materials, and the interface formed by amorphous silicon/crystalline silicon belongs to the heterojunction interface. The concept of heterojunction has been proposed by Grigorovici as early as 1951, but successful heterojunction devices were not first fabricated until 1960.
There are several milestone events in the study of amorphous/crystalline silicon-based heterojunctions: (1) and a first amorphous silicon/crystalline silicon heterojunction device. The amorphous silicon/crystalline silicon heterojunction is firstly reported to be realized on a monocrystalline silicon substrate in 1968 by Grigorovici and the like, and then amorphous silicon is deposited by adopting a thermal evaporation method, so that an amorphous silicon layer does not contain hydrogen, and the defect density of the prepared amorphous silicon film is higher. (2) And a first hydrogenated amorphous silicon/crystalline silicon heterojunction device. With the development of the PECVD technology, the amorphous silicon film deposited by adopting the PECVD method has low defect density because the amorphous silicon film contains hydrogen and can saturate dangling bonds to realize good passivation effect. In 1974, Fuhs et al first realized a hydrogenated amorphous silicon/crystalline silicon (aSi: HcSi) heterojunction device. (3) And the first amorphous silicon/crystalline silicon heterojunction is used for the solar cell. The photovoltaic response of amorphous/crystalline silicon heterojunctions has been mentioned from the outset and has attracted considerable interest. In 1983, Okuda et al obtained a laminate battery (battery area of 0.25 cm) having a conversion efficiency of 12.3%2) This is the first reported application of a-Si: H/c-Si heterojunctions. (4) And the first amorphous silicon/crystalline silicon heterojunction solar cell with the intrinsic thin film layer. In 1991, the Japan Sanyo electric machine (incorporated into Songhua corporation) used the intrinsic amorphous silicon thin film for the first time for amorphous silicon/crystalA layer of intrinsic amorphous silicon is inserted between p-n heterojunction of p-type amorphous silicon and n-type monocrystalline silicon of the bulk silicon heterojunction solar cell to realize good passivation effect of heterojunction interface, and the obtained cell efficiency reaches 18.1% (the cell area is 1 cm)2) At a low temperature of (<200 ℃ C.) to form the highest efficiency of PN junction solar cells. They named the cell as an HIT (Heterojunction with intrinsic thin-layer) cell. Taking different initials, also called HJT cells. (5) And the amorphous silicon/crystalline silicon heterojunction solar cells realize batch production. In 1997, the HIT cells of the san yang company were mass-produced and proposed HJT cell modules for different applications. (6) And the conversion efficiency of the amorphous silicon/crystalline silicon heterojunction solar cell is continuously improved. The Sanyo company has been in the leading position in the research and development and production fields of amorphous silicon/bulk silicon heterojunction solar cells with intrinsic thin film layers, and the research and development area size is 100cm2The conversion efficiency of the HJT batteries on the left and the right continuously breaks through 20%, 21%, 22% and 23% of important gateways. In 2 months 2013, panasonic corporation (having purchased the Sanyo company) announced that the conversion efficiency of HJT cells, which had an area of 1018cm, was 24.7% at the highest, exceeding the maximum efficiency (24.2%) of Sunpower corporation's IBC cells and breaking the world record of large area solar cells2Open circuit voltage of 750mV and short circuit current density of 39.5mA cm2The fill factor was 83.2%.
Since the break of UNSW by 25.6% of Panasonic in early 2014 maintained the record for nearly 20 years, Panasonic, shrarp and Kaneka surpassed 25% one after the other. Researchers from Kaneka Corporation, a japanese chemical manufacturer, promoted the photoelectric conversion rate of HJT cells to 26.3% by 2016, breaking the previous record of 25.6% loose. Currently, HJT cells stacked with IBC technology can exhibit more striking conversion efficiency, which is currently up to 26.63%.
In order to greatly improve the efficiency of the HJT battery, a need exists in the art for a heterojunction battery that can greatly improve the minority carrier lifetime as a key parameter.
Disclosure of Invention
In view of this, the present invention provides a crystalline silicon/amorphous silicon heterojunction cell and a method for manufacturing the same, which can improve the open-circuit voltage, the short-circuit current and the fill factor, thereby greatly improving the efficiency of the HJT cell.
In order to achieve the purpose, the invention adopts the following technical scheme: a crystalline/amorphous silicon heterojunction cell, comprising:
the substrate is a crystal silicon wafer;
the i-type intrinsic amorphous silicon thin film, the P-type amorphous silicon thin film and the multilayer TCO thin film are sequentially grown on the front surface of the substrate;
an i-type intrinsic amorphous silicon thin film, an N-type amorphous silicon thin film and a multilayer TCO thin film are sequentially grown on the back of the substrate;
and a metal electrode disposed on the TCO film.
The invention has the beneficial effects that: the battery is made into a plurality of TCO films, so that the whole passivation effect is further greatly enhanced, the minority carrier lifetime key parameter is greatly improved, the purposes of improving open-circuit voltage, short-circuit current and filling factor can be achieved, and the efficiency of the HJT battery is greatly improved.
Preferably, the crystal silicon wafer is an N-type single crystal silicon wafer or a P-type single crystal silicon wafer; the thickness of the i-type intrinsic amorphous silicon film is 5-20 nm; the metal electrode is a metal silver electrode.
By adopting the preferable scheme, the thickness of the i-layer amorphous silicon film is designed to be 5-20nm, so that a better passivation effect can be achieved, the open-circuit voltage is improved, the passivation effect is reduced when the thickness is less than 5nm, the conductivity is reduced when the thickness is more than 20nm, and the filling factor value is reduced. The metal silver electrode is adopted mainly because of the conductivity of the metal silver electrode and the maturity of the screen printing scheme, and is considered from the perspective of being suitable for mass production.
More preferably, the crystalline silicon wafer is an N-type monocrystalline silicon wafer, and the thickness of the crystalline silicon wafer is 130-200 μm; compared with a P-type monocrystalline silicon wafer, the N-type monocrystalline silicon wafer has longer minority carrier lifetime and easier passivation under the same doping concentration, and the N-type monocrystalline silicon wafer is selected to have no B-O composite attenuation in the aspect of optics. More preferably, the thickness is 150-.
More preferably, the thickness of the i-type intrinsic amorphous silicon thin film is 5-10nm, and the radicals in the thickness range are favorable for the transmission of carriers and can reduce the absorption of short-wave light.
Preferably, the number of the TCO thin films is 2-4; the TCO film is a low-power sputtering TCO film and a high-power sputtering TCO film; the thickness of the low-power sputtering TCO film is 10-40nm, and the thickness of the high-power sputtering TCO film is 50-100 nm.
More preferably, the number of TCO film layers is 2.
With the above preferred scheme, 2 layers are preferred, mainly aiming at the contact layer of the amorphous silicon thin film, namely the first layer (the first layer must be selected to use a low-power thin film for reducing the damage of the amorphous silicon layer in the invention), and 2 layers are the best scheme from the angle, and more than 2 layers affect the film forming quality of the TCO film layer.
Preferably, the thickness of the superposition of the low-power sputtering TCO film and the high-power sputtering TCO film is 60-140nm, and more preferably, the thickness of the superposition is 80-110 nm.
By adopting the preferable scheme, the conductive capability of the film with the thickness of less than 80nm is reduced, the filling value is lost, the cost of the film with the thickness of more than 110nm is increased, and the achieved effect is kept equal to that of 110nm
The TCO film is an ITO film, an AZO film or an ITIO film. More preferably an ITO thin film.
The invention also provides a preparation method of the crystalline silicon/amorphous silicon heterojunction battery, which comprises the following steps:
step (1): texturing and cleaning a crystal silicon wafer;
step (2): growing i-type intrinsic amorphous silicon thin films on the front side and the back side of the crystalline silicon wafer in the step (1) by utilizing plasma chemical vapor deposition;
and (3): growing a P-type and/or N-type amorphous silicon film on the i-type intrinsic amorphous silicon film in the step (2) by utilizing plasma chemical vapor deposition;
and (4): growing a plurality of TCO films on the P-type and/or N-type amorphous silicon films in the step (3) by utilizing physical vapor deposition magnetron sputtering and adopting low-power sputtering or high-power sputtering;
and (5): and (4) forming a metal electrode on the TCO film in the step (4) in a screen printing mode to obtain the crystalline silicon/amorphous silicon heterojunction cell.
The invention has the following beneficial effects: the invention aims to obtain TCO film layering by controlling different powers by adopting physical vapor deposition magnetron sputtering, reduce the damage of an amorphous silicon film layer generated in the process by controlling the bombardment influence on the amorphous silicon surface in the TCO deposition process, furthest exert the passivation characteristic of the amorphous silicon while not influencing the film layer quality of TCO deposition, further greatly enhance the whole passivation effect by the TCO film layer, greatly improve the key parameter of minority carrier lifetime, achieve the aim of improving open-circuit voltage, short-circuit current and filling factor, and greatly improve the efficiency of the HJT battery.
Preferably, in the texturing process in the step (1), an alkaline solution is adopted to corrode the texturing process to form a crystal face, and the textured structure is a light receiving face of a pyramid structure; the thickness of the light receiving surface is 1 to 7 μm.
More preferably, the light receiving surface has a thickness of 3 to 5 μm.
Preferably, the alkaline solution is NaOH or KOH, and the volume concentration ratio of the alkaline solution is 2-10%.
More preferably, a KOH solution is used as the etching solution, and in order to reduce the risk of Potential Induced Degradation (PID), a KOH solution is selected.
Preferably, in the step (4), the low-power sputtering TCO film is formed by low-power deposition sputtering, and the high-power sputtering TCO film is formed by high-power deposition sputtering; and the low power of the low power sputtering is 1-4kw, and the high power of the high power sputtering is 4-20 kw.
Preferably, in the step (5), the metallic silver electrode is formed by screen printing, the silver electrode includes a main grid and a secondary grid line, the main grid line and the secondary grid line are vertically distributed, the number of the main grid lines is 5-18, the number of the secondary grid lines is 70-200, and the width of the grid line is 30-60 μm.
Preferably, the method further comprises the following steps: sintering after the crystalline silicon/amorphous silicon heterojunction battery is obtained in the step (5); the sintering temperature is 180-200 ℃, and the sintering time is 25-33 min. And the silver electrode is solidified in a sintering mode, so that good ohmic contact between the metal and the silver electrode is realized.
According to the technical scheme, compared with the prior art, the invention discloses and provides the crystalline silicon/amorphous silicon heterojunction battery and the preparation method thereof, further optimization of the front surface and the back surface of the HJT battery is realized, the passivation characteristic of the original amorphous silicon layer is greatly kept by introducing the concept of power layering, the passivation effect brought by the TCO layer is greatly improved, the minority carrier lifetime is greatly prolonged, and meanwhile, the light transmittance is improved by matching with enough high-power kinetic energy, so that several electrical performance parameters can be improved, and the improvement of the efficiency is greatly promoted.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a TCO film provided in a comparative example as a layer;
FIG. 2 is a schematic diagram of a two-layer TCO film according to the present invention;
1. the thin film solar cell comprises a silver metal electrode, 2 parts of a low-power sputtering ITO thin film, 3 parts of a P-type amorphous silicon thin film, 4 parts of an N-type amorphous silicon thin film, 5 parts of an i-type intrinsic amorphous silicon thin film, 6 parts of an N-type monocrystalline silicon piece and 7 parts of a high-power sputtering ITO thin film.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
A crystalline/amorphous silicon heterojunction cell, comprising: a substrate of an N-type monocrystalline silicon wafer 6 with a thickness of 180 μm;
an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, a P-type amorphous silicon thin film 3 with the thickness of 10nm, a low-power sputtering ITO thin film 4 with the thickness of 20nm and two high-power sputtering ITO thin films 7 with the thickness of 40nm are sequentially grown on the front surface of an N-type monocrystalline silicon wafer 6;
an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, an N-type amorphous silicon thin film 4 with the thickness of 8nm, a low-power sputtering ITO thin film 4 with the thickness of 20nm and two high-power sputtering ITO thin films 7 with the thickness of 40nm are sequentially grown on the back surface of an N-type monocrystalline silicon wafer 6;
and a silver metal electrode 1 provided on the high-power sputtered ITO film 7.
The preparation method of the crystalline silicon/amorphous silicon heterojunction battery comprises the following steps:
step (1): carrying out texturing treatment on an N-type monocrystalline silicon wafer 6 with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;
step (2): growing an i-type intrinsic amorphous silicon film 5 with the thickness of 10nm on the front surface and the back surface of the N-type monocrystalline silicon wafer 6 in the step (1) by utilizing plasma chemical vapor deposition;
and (3): growing a P-type amorphous silicon film 3 with the thickness of 10nm on the surface of the i-type intrinsic amorphous silicon film 5 growing on the front surface in the step (2) by utilizing plasma chemical vapor deposition; and (3) growing an N-type amorphous silicon thin film 4 with the thickness of 8nm on the surface of the i-type intrinsic amorphous silicon thin film 5 grown on the back surface in the step (2).
And (4): depositing an ITO film by magnetron sputtering, respectively depositing and sputtering a first low-power sputtering ITO film 4 with the thickness of 20nm on the surfaces of the P-type amorphous silicon and the N-type amorphous silicon in the step (3) by adopting low sputtering power of 2.5kw, and depositing and sputtering a second high-power sputtering ITO film 7 with the same thickness of 40nm and a third high-power sputtering ITO film 7 with the total thickness of 80nm by adopting high power of 5 kw.
And (5): forming silver metal electrodes 1 on the front surface and the back surface by screen printing, wherein the width of a main grid is 0.8mm, the number of the main grids is 5, the width of silver auxiliary grid lines on the front surface and the back surface is 50 mu m, and the number of the lines is 100; and sintering to obtain the crystalline silicon/amorphous silicon heterojunction battery. And testing the electrical property of the cell by using the crystalline silicon/amorphous silicon heterojunction cell.
Example 2
A crystalline/amorphous silicon heterojunction cell, comprising: a substrate of an N-type monocrystalline silicon wafer 6 with a thickness of 180 μm;
an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, a P-type amorphous silicon thin film 3 with the thickness of 10nm, two low-power sputtering ITO thin films 4 with the thickness of 25nm and a high-power sputtering ITO thin film 7 with the thickness of 50nm are sequentially grown on the front surface of an N-type monocrystalline silicon wafer 6;
an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, an N-type amorphous silicon thin film 4 with the thickness of 8nm, two low-power sputtering ITO thin films 4 with the thickness of 25nm and a high-power sputtering ITO thin film 7 with the thickness of 50nm are sequentially grown on the back surface of an N-type monocrystalline silicon wafer 6;
and a silver metal electrode 1 provided on the high-power sputtered ITO film 7.
The preparation method of the crystalline silicon/amorphous silicon heterojunction battery comprises the following steps:
step (1): carrying out texturing treatment on an N-type monocrystalline silicon wafer 6 with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;
step (2): growing an i-type intrinsic amorphous silicon film 5 with the thickness of 10nm on the front surface and the back surface of the N-type monocrystalline silicon wafer 6 in the step (1) by utilizing plasma chemical vapor deposition;
and (3): growing a P-type amorphous silicon film 3 with the thickness of 10nm on the surface of the i-type intrinsic amorphous silicon film 5 growing on the front surface in the step (2) by utilizing plasma chemical vapor deposition; and (3) growing an N-type amorphous silicon thin film 4 with the thickness of 8nm on the surface of the i-type intrinsic amorphous silicon thin film 5 grown on the back surface in the step (2).
And (4): and (3) depositing an ITO film by magnetron sputtering, respectively depositing and sputtering a first layer and a second layer of low-power sputtering ITO film 4 with the thickness of 25nm on the surfaces of the P-type amorphous silicon and the N-type amorphous silicon in the step (3) by adopting low sputtering power of 2.5kw, and depositing and sputtering a third layer of high-power sputtering ITO film 7 with the thickness of 50nm by adopting high power of 5 kw.
And (5): forming front and back silver metal electrodes by screen printing, wherein the width of a main grid is 0.8mm, the number of the main grids is 5, the width of a front and back silver auxiliary grid line is 50 mu m, and the number of lines is 100; and sintering to obtain the crystalline silicon/amorphous silicon heterojunction battery. And testing the electrical property of the cell by using the crystalline silicon/amorphous silicon heterojunction cell.
Example 3
A crystalline/amorphous silicon heterojunction cell, comprising: a substrate of an N-type monocrystalline silicon wafer 6 with a thickness of 180 μm;
the method comprises the following steps of sequentially growing an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, a P-type amorphous silicon thin film 3 with the thickness of 10nm, a low-power sputtering ITO thin film 4 with the thickness of 13.4nm, a high-power sputtering ITO thin film 7 with the thickness of 26.6nm and a high-power sputtering ITO thin film 7 with the thickness of 60nm on the front surface of an N-type monocrystalline silicon wafer 6;
an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, an N-type amorphous silicon thin film 4 with the thickness of 8nm, two low-power sputtering ITO thin films 4 with the thickness of 25nm and a high-power sputtering ITO thin film 7 with the thickness of 40nm are sequentially grown on the back surface of an N-type monocrystalline silicon wafer 6;
and a silver metal electrode 1 provided on the high-power sputtered ITO film 7.
The preparation method of the crystalline silicon/amorphous silicon heterojunction battery comprises the following steps:
step (1): carrying out texturing treatment on an N-type monocrystalline silicon wafer 6 with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;
step (2): growing an i-type intrinsic amorphous silicon film 5 with the thickness of 10nm on the front surface and the back surface of the N-type monocrystalline silicon wafer 6 in the step (1) by utilizing plasma chemical vapor deposition;
and (3): growing a P-type amorphous silicon film 3 with the thickness of 10nm on the surface of the i-type intrinsic amorphous silicon film 5 growing on the front surface in the step (2) by utilizing plasma chemical vapor deposition; and (3) growing an N-type amorphous silicon thin film 4 with the thickness of 8nm on the surface of the i-type intrinsic amorphous silicon thin film 5 grown on the back surface in the step (2).
And (4): and (3) depositing an ITO film by magnetron sputtering, depositing and sputtering a first layer of low-power sputtering ITO film 4 with the thickness of 13.4nm on the surfaces of the P-type amorphous silicon and the N-type amorphous silicon in the step (3) by adopting low sputtering power of 2kw, depositing and sputtering a second layer of high-power sputtering ITO film 7 with the thickness of 26.6nm by adopting high power of 4kw, depositing and sputtering a third layer of high-power sputtering ITO film 7 with the thickness of 60nm by adopting high power of 9kw, wherein the total thickness of the high-power sputtering ITO film 7 is 86.6 nm.
And (5): forming front and back silver metal electrodes by screen printing, wherein the width of a main grid is 0.8mm, the number of the main grids is 5, the width of a front and back silver auxiliary grid line is 50 mu m, and the number of lines is 100; and sintering to obtain the crystalline silicon/amorphous silicon heterojunction battery. And testing the electrical property of the cell by using the crystalline silicon/amorphous silicon heterojunction cell.
Comparative example
A crystalline/amorphous silicon heterojunction cell, comprising: a substrate of an N-type monocrystalline silicon wafer 6 with a thickness of 180 μm;
an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm, a P-type amorphous silicon thin film 3 with the thickness of 10nm and an ITO thin film 4 with the thickness of 100nm are sequentially grown on the front surface of an N-type monocrystalline silicon wafer 6;
an i-type intrinsic amorphous silicon thin film 5 with the thickness of 10nm and an ITO thin film 4 with the thickness of 100nm are sequentially grown on the back of an N-type monocrystalline silicon wafer 6;
and a silver metal electrode 1 provided on the ITO film 4.
The preparation method of the crystalline silicon/amorphous silicon heterojunction battery comprises the following steps:
step (1): carrying out texturing treatment on an N-type monocrystalline silicon wafer with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;
step (2): growing an i-type intrinsic amorphous silicon film with the thickness of 10nm on the front surface and the back surface of the N-type monocrystalline silicon wafer in the step (1) by utilizing plasma chemical vapor deposition;
and (3): growing a P-type amorphous silicon film with the thickness of 10nm on the surface of the i-type intrinsic amorphous silicon film grown on the front surface in the step (2) by utilizing plasma chemical vapor deposition; and (3) growing an N-type amorphous silicon film with the thickness of 8nm on the surface of the i-type intrinsic amorphous silicon film grown on the back surface in the step (2).
And (4): and (4) depositing an ITO film by magnetron sputtering, and depositing and sputtering the ITO film with the thickness of 100nm on the surfaces of the P-type amorphous silicon and the N-type amorphous silicon in the step (3) by adopting sputtering power of 5 kw.
And (5): forming front and back silver metal electrodes by screen printing, wherein the width of a main grid is 0.8mm, the number of the main grids is 5, the width of a front and back silver auxiliary grid line is 50 mu m, and the number of lines is 100; and sintering to obtain the crystalline silicon/amorphous silicon heterojunction battery. And testing the electrical property of the cell by using the crystalline silicon/amorphous silicon heterojunction cell.
Performance testing
The electrical performance results of the cells of examples 1-3 and comparative example are compared to those of table 1:
the embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A crystalline/amorphous silicon heterojunction cell, comprising:
the substrate is a crystal silicon wafer;
the i-type intrinsic amorphous silicon thin film, the P-type amorphous silicon thin film and the multilayer TCO thin film are sequentially grown on the front surface of the substrate;
an i-type intrinsic amorphous silicon thin film, an N-type amorphous silicon thin film and a multilayer TCO thin film are sequentially grown on the back of the substrate;
and a metal electrode disposed on the TCO film.
2. The crystalline silicon/amorphous silicon heterojunction cell according to claim 1, wherein the crystalline silicon wafer is an N-type monocrystalline silicon wafer or a P-type monocrystalline silicon wafer; the thickness of the i-type intrinsic amorphous silicon film is 5-20 nm; the metal electrode is a metal silver electrode.
3. The crystalline silicon/amorphous silicon heterojunction cell as claimed in claim 1, wherein the number of TCO thin films is 2-4; the TCO film is a low-power sputtering TCO film and a high-power sputtering TCO film; the thickness of the low-power sputtering TCO film is 10-40nm, and the thickness of the high-power sputtering TCO film is 50-100 nm.
4. The crystalline silicon/amorphous silicon heterojunction cell as claimed in claim 3, wherein the TCO film is an ITO film, an AZO film or an ITiO film.
5. A preparation method of a crystalline silicon/amorphous silicon heterojunction battery is characterized by comprising the following steps:
step (1): texturing and cleaning a crystal silicon wafer;
step (2): growing i-type intrinsic amorphous silicon thin films on the front side and the back side of the crystalline silicon wafer in the step (1) by utilizing plasma chemical vapor deposition;
and (3): growing a P-type and/or N-type amorphous silicon thin film on the i-type intrinsic amorphous silicon thin film in the step (2) by utilizing plasma chemical vapor deposition;
and (4): growing a plurality of TCO films on the P-type and/or N-type amorphous silicon films in the step (3) by utilizing physical vapor deposition magnetron sputtering and adopting low-power sputtering or high-power sputtering;
and (5): and (4) forming a metal electrode on the TCO film in the step (4) in a screen printing mode to obtain the crystalline silicon/amorphous silicon heterojunction cell.
6. The method for preparing a crystalline silicon/amorphous silicon heterojunction battery as in claim 5, wherein in the texturing step (1), an alkaline solution is adopted to etch a textured surface, and the textured structure is a light receiving surface of a pyramid structure.
7. The method for preparing a crystalline silicon/amorphous silicon heterojunction battery as in claim 6, wherein the alkaline solution is NaOH or KOH, and the volume concentration ratio of the alkaline solution is 2-10%.
8. The method for preparing a crystalline silicon/amorphous silicon heterojunction battery as claimed in claim 5, wherein in the step (4), the low-power sputtering TCO film is formed by low-power deposition sputtering, and the high-power sputtering TCO film is formed by high-power deposition sputtering; and the low power of the low power sputtering is 1-4kw, and the high power of the high power sputtering is 4-20 kw.
9. The method for preparing a crystalline silicon/amorphous silicon heterojunction battery as in claim 5, wherein in the step (5), the metallic silver electrode is formed by screen printing, the silver electrode comprises main grid lines and auxiliary grid lines, the main grid lines and the fine grid lines are vertically distributed, the number of the main grid lines is 5-18, the number of the auxiliary grid lines is 70-200, and the width of the grid lines is 30-60 μm.
10. The method for preparing a crystalline silicon/amorphous silicon heterojunction battery as in claim 5, further comprising the following steps: sintering after the crystalline silicon/amorphous silicon heterojunction battery is obtained in the step (5); the sintering temperature is 180-200 ℃, and the sintering time is 25-33 min.
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| CN108231928A (en) * | 2017-12-21 | 2018-06-29 | 君泰创新（北京）科技有限公司 | A kind of HJT hetero-junction solar cells and its multi-layer transparent electroconductive film |
| CN110310999A (en) * | 2019-07-22 | 2019-10-08 | 江苏爱康能源研究院有限公司 | The hetero-junction solar cell structure and preparation method thereof of gradual change lamination TCO conductive film |
| CN211238272U (en) * | 2019-11-29 | 2020-08-11 | 晋能光伏技术有限责任公司 | Crystalline silicon/amorphous silicon heterojunction battery |
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| CN108231928A (en) * | 2017-12-21 | 2018-06-29 | 君泰创新（北京）科技有限公司 | A kind of HJT hetero-junction solar cells and its multi-layer transparent electroconductive film |
| CN110310999A (en) * | 2019-07-22 | 2019-10-08 | 江苏爱康能源研究院有限公司 | The hetero-junction solar cell structure and preparation method thereof of gradual change lamination TCO conductive film |
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