CN116779693A - High-efficiency heterojunction solar cell and manufacturing method thereof - Google Patents
High-efficiency heterojunction solar cell and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 84
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims abstract description 82
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 73
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 73
- 239000010703 silicon Substances 0.000 claims abstract description 73
- 239000002131 composite material Substances 0.000 claims abstract description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims description 47
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 38
- 229910000077 silane Inorganic materials 0.000 claims description 38
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 29
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 21
- 229910052739 hydrogen Inorganic materials 0.000 claims description 20
- 239000001257 hydrogen Substances 0.000 claims description 20
- 239000012495 reaction gas Substances 0.000 claims description 20
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 16
- 239000001569 carbon dioxide Substances 0.000 claims description 16
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 16
- 239000005922 Phosphane Substances 0.000 claims description 13
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 13
- 229910000064 phosphane Inorganic materials 0.000 claims description 13
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 5
- 150000002431 hydrogen Chemical class 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- -1 diborane Chemical compound 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 13
- 238000002161 passivation Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 4
- 230000003287 optical effect Effects 0.000 abstract description 4
- 230000006872 improvement Effects 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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Abstract
The application discloses a high-efficiency heterojunction solar cell and a manufacturing method thereof, wherein the cell comprises the following components: the N-type silicon wafer is sequentially arranged on the first intrinsic amorphous silicon layer, the N-type doped layer, the transparent conducting layer and the metal grid line layer on the front surface of the silicon wafer, and the second intrinsic amorphous silicon layer, the P-type doped layer, the transparent conducting layer and the metal grid line layer on the back surface of the silicon wafer. The N-type doped layer or/and the P-type doped layer is/are of a multi-layer composite structure, namely a multi-layer composite structure comprising a seed layer, a microcrystalline silicon oxide layer and a microcrystalline silicon layer; and particularly discloses a manufacturing method of the N-type doped layer and the P-type doped layer of the multilayer composite structure. The multilayer composite structure has the advantages that the large optical band gap brings about great improvement of short-circuit current of the battery, meanwhile, the seed layer at the interface with the intrinsic passivation layer improves the film growth quality and passivation effect, and the N-type microcrystalline silicon layer at the interface with the TCO film forms good contact, so that the conversion efficiency of the battery is obviously improved.
Description
Technical Field
The application relates to the field of crystalline silicon solar cells, in particular to a high-efficiency heterojunction solar cell and a manufacturing method thereof.
Background
The heterojunction solar cell has the advantages of simple preparation process steps, low process temperature, high power generation quantity, high stability, no attenuation and low cost, and along with continuous technical progress and policy promotion of industry, the heterojunction solar cell has the advantages of cost performance and is possible to replace a crystalline silicon solar cell to become a next generation mainstream photovoltaic cell.
At present, the conventional heterojunction solar cell uses an N-type monocrystalline silicon wafer as a substrate, and a phosphorus-doped amorphous silicon N layer is used as a window layer of a light receiving surface, so that the cell has higher conversion efficiency; in order to further improve the efficiency of the heterojunction battery, in the prior art, an amorphous silicon N layer serving as a window layer is doped with carbon dioxide to form an N-type silicon oxide film with a wider band gap, so that the short-circuit current of the battery is greatly improved. However, the addition of carbon dioxide results in an increase in the defect state density of the material, a decrease in conductivity, and a significant decrease in the cell fill factor.
Disclosure of Invention
In view of the above problems, the application provides a high-efficiency heterojunction solar cell and a manufacturing method thereof, wherein the influences of short-circuit current, open-circuit voltage and filling factor of the cell can be simultaneously improved by adopting N-type doped layers or/and P-type doped layers of a multi-layer composite structure, so that the cell efficiency can be obviously improved.
In order to achieve the above object, the present application provides a high efficiency heterojunction solar cell comprising: the N-type silicon wafer is sequentially arranged on the first intrinsic amorphous silicon layer, the N-type doped layer, the front transparent conductive layer and the front metal grid line layer on the front surface of the silicon wafer. The second intrinsic amorphous silicon layer, the P-type doped layer, the back transparent conductive layer and the back metal grid line layer are sequentially arranged on the back of the silicon wafer; the semiconductor device is characterized in that the N-type doped layer or/and the P-type doped layer is of a multilayer composite structure; the N-type doped layer of the multilayer composite layer structure comprises an N-face seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer; the P-type doped layer of the multilayer composite layer structure comprises a P-face seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon layer.
Further, the thickness of the N-face seed layer is 1-4nm; the thickness of the N-type microcrystalline silicon oxide layer is 4-8nm, and the thickness of the N-type microcrystalline silicon layer is 1-4nm.
Further, the thickness of the P-surface seed layer is 1-4nm; the thickness of the P-type microcrystalline silicon oxide layer is 2-6nm, and the thickness of the P-type microcrystalline silicon layer is 8-20nm.
The application also provides a manufacturing method of the high-efficiency heterojunction solar cell, which comprises the following steps:
providing an N-type silicon wafer which is subjected to texturing and cleaning;
depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer by PECVD,
depositing a first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD;
depositing an N-type doped layer or sequentially depositing an N-face seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front face of the silicon wafer by PECVD to form an N-type doped layer with a multi-layer composite layer structure;
depositing a P-type doped layer or sequentially depositing a P-face seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back of the silicon wafer by PECVD to form a P-type doped layer with a multilayer composite layer structure;
depositing transparent conductive layers on the front N-type doped layer and the back P-type doped layer of the silicon wafer through PVD magnetron sputtering respectively;
and manufacturing metal grid line electrodes on the transparent conductive layers on the front side and the back side of the silicon wafer respectively.
The application also provides a back contact heterojunction solar cell (HBC), which comprises an N-type monocrystalline silicon wafer, a pyramid suede, an intrinsic amorphous silicon layer and an anti-reflection layer, wherein the pyramid suede, the intrinsic amorphous silicon layer and the anti-reflection layer are sequentially arranged on the front surface of the silicon wafer. The intrinsic amorphous silicon layer, the P-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the P area on the back surface of the silicon wafer. The intrinsic amorphous silicon layer, the N-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the N area on the back surface of the silicon wafer. The N-type amorphous silicon layer is replaced by adopting the N-type doped layer with the multi-layer composite layer structure or/and the P-type amorphous silicon layer is replaced by adopting the P-type doped layer with the multi-layer composite layer structure.
The high-efficiency heterojunction solar cell and the manufacturing method thereof have the beneficial effects that:
(1) An undoped seed layer is formed on the bottom layer of the N-type doped layer or/and the P-type doped layer, so that the quality of the subsequent film growth is improved, and meanwhile, passivation effect reduction caused by diffusion of doped impurities into an intrinsic passivation layer is reduced;
(2) The second layer of the N-type doped layer or/and the second layer of the P-type doped layer is doped by introducing carbon dioxide to form an N-type microcrystalline silicon oxide layer or/and a P-type microcrystalline silicon oxide layer, and the optical band gap of the N-type microcrystalline silicon oxide layer or/and the P-type microcrystalline silicon oxide layer is larger, so that the absorption of the cell to light is increased; the PN junction interface can bring larger energy band bending, so that the open-circuit voltage of the battery is improved;
(3) Carbon dioxide doping is not carried out on the third layer of the N-type doping layer or/and the P-type doping layer, so that good electrical contact with a subsequent TCO film is maintained, and series resistance is reduced;
in summary, according to the high-efficiency heterojunction solar cell and the manufacturing method thereof provided by the application, the N-type doped layer or/and the P-type doped layer adopts a multi-layer composite structure, namely an N-side seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer composite layer or a P-side seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon oxide layer, the larger optical band gap brings about a great improvement of cell short-circuit current, and meanwhile, the seed layer at the interface with the intrinsic passivation layer improves the film growth quality and passivation effect, and the N-type microcrystalline silicon layer or/and the P-type microcrystalline silicon layer at the interface with the TCO film form good contact, so that the cell conversion efficiency is obviously improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
fig. 1 is a schematic structural diagram of an embodiment 1 of a high-efficiency heterojunction solar cell provided by the application.
Fig. 2 is a schematic structural diagram of embodiment 2 of the high-efficiency heterojunction solar cell provided by the application.
Fig. 3 is a schematic structural diagram of embodiment 3 of the high-efficiency heterojunction solar cell provided by the application.
Fig. 4 is a flowchart of a method for fabricating a high-efficiency heterojunction solar cell according to the present application.
Reference numerals illustrate: the semiconductor device comprises an N-type silicon wafer 10, a first intrinsic amorphous silicon layer 20, an N-type doped layer 30, a front transparent conductive layer 60-1, a front metal grid line layer 70-1, a second intrinsic amorphous silicon layer 40, a P-type doped layer 50, a back transparent conductive layer 60-2, a back metal grid line layer 70-2, an N-side seed layer 31, an N-type microcrystalline silicon oxide layer 32, an N-type microcrystalline silicon layer 33, a P-side seed layer 51, a P-type microcrystalline silicon oxide layer 52 and a P-type microcrystalline silicon layer 53.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
As shown in fig. 1 to 3, the present application provides a high-efficiency heterojunction solar cell, comprising: the N-type silicon wafer 10 is sequentially arranged on the first intrinsic amorphous silicon layer 20, the N-type doped layer 30, the front transparent conductive layer 60-1 and the front metal grid line layer 70-1 on the front surface of the silicon wafer 10. The second intrinsic amorphous silicon layer 40, the P-type doped layer 50 and the back transparent conductive layer 60-2 and the back metal gate line layer 70-2 are sequentially arranged on the back of the silicon wafer 10; the N-type doped layer 30 and/or the P-type doped layer 50 are/is a multi-layer composite structure, and the N-type doped layer of the multi-layer composite structure comprises an N-side seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer; the P-type doped layer 50 of the multi-layer composite structure comprises a P-surface seed layer 51, a P-type microcrystalline silicon oxide layer 52 and a P-type microcrystalline silicon layer 53.
The N-type silicon wafer is a monocrystalline silicon wafer or a polycrystalline silicon wafer.
The thickness of the N-side seed layer 31 is 1-4nm; the thickness of the N-type microcrystalline silicon oxide layer 32 is 4-8nm; the thickness 33 of the N-type microcrystalline silicon layer is 1-4nm.
The thickness of the P-surface seed layer 51 is 1-4nm; the thickness of the P-type microcrystalline silicon oxide layer 52 is 2-6nm; the thickness 53 of the P-type microcrystalline silicon layer is 8-20nm.
As shown in fig. 4, the method for manufacturing the high-efficiency heterojunction solar cell comprises the following steps:
s01, providing an N-type silicon wafer which is subjected to texturing and cleaning;
s02, depositing a second intrinsic amorphous silicon layer on the back surface of the silicon wafer by PECVD;
s03, depositing a first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD;
s04, depositing an N-type doped layer or sequentially depositing an N-face seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front face of the silicon wafer by PECVD to form an N-type doped layer with a multilayer composite structure;
s05, depositing a P-type doped layer or sequentially depositing a P-face seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back of the silicon wafer by PECVD to form a P-type doped layer with a multilayer composite structure;
s06, depositing a transparent conductive layer on the front N-type doped layer and the back P-type doped layer of the silicon wafer through PVD magnetron sputtering respectively;
s07, manufacturing metal grid line electrodes on the transparent conductive layers on the front side and the back side of the silicon wafer respectively;
the process of depositing the N-surface seed layer in the step S04 and the P-surface seed layer in the step S05 is to introduce mixed gas of silane and hydrogen, and the pressure of the reaction gas is 100 Pa to 300Pa.
The process for depositing the N-type microcrystalline silicon oxide layer in the step S04 comprises the steps of introducing mixed gas of silane, phosphane, hydrogen and carbon dioxide, wherein the pressure of the reaction gas is 150-400Pa, the ratio of the phosphane to the silane is 1% -10%, and the ratio of the carbon dioxide to the silane is 50% -100%.
And in the step S04, the mixed gas of silane, phosphane and hydrogen is introduced in the process of depositing the N-type microcrystalline silicon layer, the pressure of the reaction gas is 150-400Pa, and the ratio of the phosphane to the silane is 1-10%.
The PECVD preset film forming temperature in the step S04 is 150-250 ℃.
The process of depositing the P-type microcrystalline silicon oxide layer in the step S05 comprises the steps of presetting the PECVD film forming temperature to be 150-250 ℃, then introducing mixed gas of silane, diborane, hydrogen and carbon dioxide, wherein the pressure of the reaction gas is 150-400Pa, the ratio of diborane to silane is 1% -10%, and the ratio of carbon dioxide to silane is 50% -100%.
The process of depositing the P-type microcrystalline silicon layer in the step S05 comprises the steps of presetting the PECVD film forming temperature to be 150-250 ℃, and then introducing mixed gas of silane, diborane and hydrogen, wherein the pressure of the reaction gas is 150-400Pa, and the ratio of diborane to silane is 1% -10%.
A back contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, a pyramid suede, an intrinsic amorphous silicon layer and an anti-reflection layer, wherein the pyramid suede, the intrinsic amorphous silicon layer and the anti-reflection layer are sequentially arranged on the front surface of the silicon wafer. The intrinsic amorphous silicon layer, the P-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the P area on the back surface of the silicon wafer. The intrinsic amorphous silicon layer, the N-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the N area on the back surface of the silicon wafer. The N-type amorphous silicon layer is replaced by the N-type doped layer with the multi-layer composite layer structure or/and the P-type amorphous silicon layer is replaced by the P-type doped layer with the multi-layer composite layer structure.
Example 1
As shown in fig. 1, a high efficiency heterojunction solar cell comprises: the N-type silicon wafer 10 is sequentially arranged on the first intrinsic amorphous silicon layer 20, the N-type doped layer 30, the front transparent conductive layer 60-1 and the front metal grid line layer 70-1 on the front surface of the silicon wafer 10. The second intrinsic amorphous silicon layer 40, the P-type doped layer 50 and the back transparent conductive layer 60-2 and the back metal gate line layer 70-2 are sequentially arranged on the back of the silicon wafer 10; the N-type doped layer 30 and the P-type doped layer 50 are both of a multi-layer composite structure, and the N-type doped layer of the multi-layer composite structure comprises an N-side seed layer 31, an N-type microcrystalline silicon oxide layer 32 and an N-type microcrystalline silicon layer 33; the P-type doped layer 50 of the multi-layer composite structure comprises a P-surface seed layer 51, a P-type microcrystalline silicon oxide layer 52 and a P-type microcrystalline silicon layer 53.
The manufacturing method of the high-efficiency heterojunction solar cell comprises the following specific processes:
s01, providing an N-type silicon wafer which is subjected to texturing and cleaning; the method comprises the specific processes that pyramid suede is formed on the surface of an N-type silicon wafer in a velvet making and cleaning mode, and the surface is kept clean; the N-type silicon wafer is a monocrystalline silicon wafer.
S02, depositing a second intrinsic amorphous silicon layer on the back surface of the silicon wafer in the S01 through PECVD; the specific process is that silane and hydrogen are introduced into a reaction cavity; the preset film forming temperature is 150-250 ℃; the pressure of the reaction gas is 30-150Pa; the deposition thickness is 5-10nm.
S03, depositing a first intrinsic amorphous silicon layer on the front side of the silicon wafer in S02 through PECVD; the specific process is that silane and hydrogen are introduced into a reaction cavity; the preset film forming temperature is 150-250 ℃; the pressure of the reaction gas is 30-150Pa; the deposition thickness is 4-7nm.
S04, sequentially depositing an N-face seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front face of the silicon wafer in the S03 through PECVD to form an N-type doped layer with a multi-layer composite structure; the specific process is that the preset film forming temperature is 150-250 ℃; firstly, introducing mixed gas of silane and hydrogen into a reaction cavity, wherein the pressure of the reaction gas is 100-300Pa, and depositing a first layer serving as a seed layer, wherein the thickness of the first layer is 1-4nm; then introducing mixed gas of silane, phosphane, hydrogen and carbon dioxide into a reaction cavity, wherein the ratio of the phosphane to the silane is 1-10%, the ratio of the carbon dioxide to the silane is 50-100%, the pressure of the reaction gas is 150-400Pa, and the deposited second layer is an N-type microcrystalline silicon oxide layer with the thickness of 4-8nm; finally, introducing mixed gas of silane, phosphane and hydrogen into the reaction cavity, wherein the ratio of the phosphane to the silane is 1-10%, the pressure of the reaction gas is 150-400Pa, and the deposited third layer is an N-type microcrystalline silicon layer, and the thickness of the third layer is 1-4nm; the deposition power density is 0.03-0.3W/cm 2 。
S05, depositing a P-surface seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back of the silicon wafer in the S04 through PECVD to form a P-type doped layer with a multilayer composite structure; the specific process is that the preset film forming temperature is 150-250 ℃; in the reactionFirstly, introducing mixed gas of silane and hydrogen into a cavity, wherein the pressure of the reaction gas is 100-300Pa, and depositing a first layer serving as a P-surface seed layer, wherein the thickness of the first layer is 1-4nm; then, introducing mixed gas of silane, diborane, hydrogen and carbon dioxide into a reaction cavity, wherein the ratio of diborane to silane is 1-10%, the ratio of carbon dioxide to silane is 50-100%, the pressure of reaction gas is 150-400Pa, and the deposited second layer is a P-type microcrystalline silicon oxide layer with the thickness of 2-6nm; finally, introducing mixed gas of silane, diborane and hydrogen into a reaction cavity, wherein the ratio of diborane to silane is 1% -10%, the pressure of the reaction gas is 150-400Pa, and the deposited third layer is a P-type microcrystalline silicon layer, and the thickness of the third layer is 8-20nm; the deposition power density is 0.05-0.4W/cm 2 。
S06, depositing an ITO transparent conductive layer on the front N-type doped layer and the back P-type doped layer of the silicon wafer in the S05 through PVD magnetron sputtering; the deposition thickness is 90-110nm.
S07, manufacturing silver grid line electrodes on the transparent conductive layers on the front side and the back side of the silicon wafer in S06 through screen printing.
Example 2
As shown in fig. 2, a high efficiency heterojunction solar cell comprises: the N-type silicon wafer 10 is sequentially arranged on the first intrinsic amorphous silicon layer 20, the N-type doped layer 30, the front transparent conductive layer 60-1 and the front metal grid line layer 70 on the front surface of the silicon wafer 10. The second intrinsic amorphous silicon layer 40, the P-type doped layer 50 and the back transparent conductive layer 60-2 and the back metal gate line layer 70-2 are sequentially arranged on the back of the silicon wafer 10; the N-type doped layer 30 is a multi-layer composite structure, and the N-type doped layer of the multi-layer composite structure includes an N-surface seed layer 31, an N-type microcrystalline silicon oxide layer 32, and an N-type microcrystalline silicon layer 33.
The specific process differs from that of embodiment 1 only in the method for manufacturing the high-efficiency heterojunction solar cell:
s05, depositing a P-type doped layer on the second intrinsic amorphous silicon layer on the back of the silicon wafer in S04 through PECVD; the specific process is that diborane, silane and hydrogen are introduced into a reaction cavity; the preset film forming temperature is 150-250 ℃; the pressure of the reaction gas is 30-150Pa; the deposition thickness is 6-14nm.
Example 3
As shown in fig. 3, a high efficiency heterojunction solar cell comprises: the N-type silicon wafer 10 is sequentially arranged on the first intrinsic amorphous silicon layer 20, the N-type doped layer 30, the front transparent conductive layer 60-1 and the front metal grid line layer 70 on the front surface of the silicon wafer 10. The second intrinsic amorphous silicon layer 40, the P-type doped layer 50 and the back transparent conductive layer 60-2 and the back metal gate line layer 70-2 are sequentially arranged on the back of the silicon wafer 10; the P-type doped layer 50 is a multi-layer composite structure, and the P-type doped layer 50 of the multi-layer composite structure comprises a P-surface seed layer 51, a P-type microcrystalline silicon oxide layer 52 and a P-type microcrystalline silicon layer 53.
The specific process differs from that of embodiment 1 only in the method for manufacturing the high-efficiency heterojunction solar cell:
s04, depositing an N-type doped layer on the first intrinsic amorphous silicon layer on the front side of the silicon wafer in S03 through PECVD; the specific process is that phosphane, silane and hydrogen are introduced into a reaction cavity; the preset film forming temperature is 150-250 ℃; the pressure of the reaction gas is 30-150Pa; the deposition thickness is 4-7nm.
Example 4
A back contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, a pyramid suede, an intrinsic amorphous silicon layer and an anti-reflection layer, wherein the pyramid suede, the intrinsic amorphous silicon layer and the anti-reflection layer are sequentially arranged on the front surface of the silicon wafer. The intrinsic amorphous silicon layer, the P-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the P area on the back surface of the silicon wafer. The intrinsic amorphous silicon layer, the N-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the N area on the back surface of the silicon wafer. The N-type amorphous silicon layer and the P-type amorphous silicon layer are respectively replaced by the P-type doped layer with the multi-layer composite layer structure of the N-type doped layer with the multi-layer composite layer structure of the embodiment 1, and the manufacturing method is adopted.
Example 5
A back contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, a pyramid suede, an intrinsic amorphous silicon layer and an anti-reflection layer, wherein the pyramid suede, the intrinsic amorphous silicon layer and the anti-reflection layer are sequentially arranged on the front surface of the silicon wafer. The intrinsic amorphous silicon layer, the P-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the P area on the back surface of the silicon wafer. The intrinsic amorphous silicon layer, the N-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the N area on the back surface of the silicon wafer. Only the N-type amorphous silicon layer was replaced with the N-type doped layer of the multilayer composite layer structure described in example 1, and the fabrication method was used.
Example 6
A back contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, a pyramid suede, an intrinsic amorphous silicon layer and an anti-reflection layer, wherein the pyramid suede, the intrinsic amorphous silicon layer and the anti-reflection layer are sequentially arranged on the front surface of the silicon wafer. The intrinsic amorphous silicon layer, the P-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the P area on the back surface of the silicon wafer. The intrinsic amorphous silicon layer, the N-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the N area on the back surface of the silicon wafer. Only the P-type amorphous silicon layer is replaced by the P-type doped layer with the multi-layer composite layer structure described in embodiment 1, and the manufacturing method is adopted.
Table 1 shows the efficiency comparison of the heterojunction solar cell provided by the application and the conventional heterojunction solar cell, and the result shows that the heterojunction solar cell provided by the application shows more excellent performance in terms of electrical performance, and the specific following is shown:
in summary, according to the high-efficiency heterojunction solar cell and the manufacturing method thereof provided by the application, the N-type doped layer or/and the P-type doped layer adopt a multi-layer composite structure, namely the N-side seed layer, the N-type microcrystalline silicon oxide layer and the N-type microcrystalline silicon layer composite layer or the P-side seed layer, the P-type microcrystalline silicon oxide layer and the P-type microcrystalline silicon oxide layer, the larger optical band gap brings about a great improvement of the short-circuit current of the cell, meanwhile, the seed layer at the interface with the intrinsic passivation layer improves the film growth quality and passivation effect, and the N-type microcrystalline silicon layer at the interface with the TCO film forms good contact, so that the conversion efficiency of the cell is obviously improved. In addition, the N-type doped layer of the multilayer composite structure or/and the P-type doped layer of the multilayer composite structure are also suitable for back contact heterojunction solar cells (HBCs), and can be used for replacing the N-type amorphous silicon layer or the P-type amorphous silicon layer of the existing HBC cells and a preparation process thereof.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.
Claims (10)
1. The utility model provides a high-efficient heterojunction solar cell which characterized in that: the high-efficiency heterojunction solar cell includes: the N-type silicon wafer is sequentially arranged on the first intrinsic amorphous silicon layer, the N-type doped layer, the front transparent conductive layer and the front metal grid line layer on the front surface of the silicon wafer; the second intrinsic amorphous silicon layer, the P-type doped layer, the back transparent conductive layer and the back metal grid line layer are sequentially arranged on the back of the silicon wafer; the N-type doped layer or/and the P-type doped layer is/are of a multi-layer composite layer structure; the N-type doped layer of the multilayer composite layer structure comprises an N-face seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer; the P-type doped layer of the multilayer composite layer structure comprises a P-face seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon layer.
2. The efficient heterojunction solar cell of claim 1, further characterized by: the thickness of the N-side seed layer is 1-4nm; the thickness of the N-type microcrystalline silicon oxide layer is 4-8nm; the thickness of the N-type microcrystalline silicon layer is 1-4nm.
3. The efficient heterojunction solar cell of claim 1, further characterized by: the thickness of the P-surface seed layer is 1-4nm; the thickness of the P-type microcrystalline silicon oxide layer is 2-6nm; the thickness of the P-type microcrystalline silicon layer is 8-20nm.
4. A method of fabricating a high efficiency heterojunction solar cell as claimed in any one of claims 1 to 3, further characterized by: the method comprises the following steps:
providing an N-type silicon wafer which is subjected to texturing and cleaning;
depositing a second intrinsic amorphous silicon layer on the back surface of the silicon wafer by PECVD;
depositing a first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD;
depositing an N-type doped layer or sequentially depositing an N-face seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front face of the silicon wafer by PECVD to form an N-type doped layer with a multi-layer composite layer structure;
depositing a P-type doped layer or sequentially depositing a P-face seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back of the silicon wafer by PECVD to form a P-type doped layer with a multilayer composite layer structure;
depositing transparent conductive layers on the front N-type doped layer and the back P-type doped layer of the silicon wafer through PVD magnetron sputtering respectively;
and manufacturing metal grid line electrodes on the transparent conductive layers on the front side and the back side of the silicon wafer respectively.
5. The method of manufacturing a high efficiency heterojunction solar cell of claim 4, further characterized by: the technological process of depositing the N-side seed layer and the P-side seed layer includes presetting PECVD film forming temperature at 150-250 deg.c, and introducing mixed gas of silane and hydrogen at reaction gas pressure of 100-300Pa.
6. The method of manufacturing a high efficiency heterojunction solar cell of claim 4, further characterized by: the technological process of depositing the N-type microcrystalline silicon oxide layer comprises the steps of presetting a PECVD film forming temperature to be 150-250 ℃, then introducing mixed gas of silane, phosphane, hydrogen and carbon dioxide, wherein the pressure of the reaction gas is 150-400Pa, the ratio of the phosphane to the silane is 1-10%, and the ratio of the carbon dioxide to the silane is 50-100%.
7. The method of manufacturing a high efficiency heterojunction solar cell of claim 4, further characterized by: the technological process of depositing the N-type microcrystalline silicon layer comprises the steps of presetting the PECVD film forming temperature to be 150-250 ℃, and then introducing mixed gas of silane, phosphane and hydrogen, wherein the pressure of the reaction gas is 150-400Pa, and the ratio of the phosphane to the silane is 1% -10%.
8. The method of manufacturing a high efficiency heterojunction solar cell of claim 4, further characterized by: the process of depositing the P-type microcrystalline silicon oxide layer comprises the steps of presetting a PECVD film forming temperature to be 150-250 ℃, then introducing mixed gas of silane, diborane, hydrogen and carbon dioxide, wherein the pressure of the reaction gas is 150-400Pa, the ratio of diborane to silane is 1% -10%, and the ratio of carbon dioxide to silane is 50% -100%.
9. The method of manufacturing a high efficiency heterojunction solar cell of claim 4, further characterized by: the process of depositing the P-type microcrystalline silicon layer comprises the steps of presetting a PECVD film forming temperature to 150-250 ℃, and then introducing mixed gas of silane, diborane and hydrogen, wherein the pressure of the reaction gas is 150-400Pa, and the ratio of diborane to silane is 1% -10%.
10. A back contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, a pyramid suede, an intrinsic amorphous silicon layer and an anti-reflection layer, wherein the pyramid suede, the intrinsic amorphous silicon layer and the anti-reflection layer are sequentially arranged on the front surface of the silicon wafer. The intrinsic amorphous silicon layer, the P-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the P area on the back surface of the silicon wafer. The intrinsic amorphous silicon layer, the N-type amorphous silicon layer, the transparent conductive film layer and the metal grid line layer are sequentially arranged on the surface of the N area on the back side of the silicon wafer; the method is characterized in that the N-type amorphous silicon layer is replaced by the N-type doped layer with the multi-layer composite layer structure or/and the P-type amorphous silicon layer is replaced by the P-type doped layer with the multi-layer composite layer structure.
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